1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra30.dtsi"
3
4 /*
5 * Toradex Colibri T30 Module Device Tree
6 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
7 */
8 / {
9 memory@80000000 {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 host1x@50000000 {
14 hdmi@54280000 {
15 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
16 nvidia,hpd-gpio =
17 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
18 pll-supply = <®_1v8_avdd_hdmi_pll>;
19 vdd-supply = <®_3v3_avdd_hdmi>;
20 };
21 };
22
23 gpio: gpio@6000d000 {
24 lan-reset-n-hog {
25 gpio-hog;
26 gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
27 output-high;
28 line-name = "LAN_RESET#";
29 };
30 };
31
32 pinmux@70000868 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 /* Analogue Audio (On-module) */
38 clk1-out-pw4 {
39 nvidia,pins = "clk1_out_pw4";
40 nvidia,function = "extperiph1";
41 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
42 nvidia,tristate = <TEGRA_PIN_DISABLE>;
43 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 };
45 dap3-fs-pp0 {
46 nvidia,pins = "dap3_fs_pp0",
47 "dap3_sclk_pp3",
48 "dap3_din_pp1",
49 "dap3_dout_pp2";
50 nvidia,function = "i2s2";
51 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
52 nvidia,tristate = <TEGRA_PIN_DISABLE>;
53 };
54
55 /* Colibri Address/Data Bus (GMI) */
56 gmi-ad0-pg0 {
57 nvidia,pins = "gmi_ad0_pg0",
58 "gmi_ad2_pg2",
59 "gmi_ad3_pg3",
60 "gmi_ad4_pg4",
61 "gmi_ad5_pg5",
62 "gmi_ad6_pg6",
63 "gmi_ad7_pg7",
64 "gmi_ad8_ph0",
65 "gmi_ad9_ph1",
66 "gmi_ad10_ph2",
67 "gmi_ad11_ph3",
68 "gmi_ad12_ph4",
69 "gmi_ad13_ph5",
70 "gmi_ad14_ph6",
71 "gmi_ad15_ph7",
72 "gmi_adv_n_pk0",
73 "gmi_clk_pk1",
74 "gmi_cs4_n_pk2",
75 "gmi_cs2_n_pk3",
76 "gmi_iordy_pi5",
77 "gmi_oe_n_pi1",
78 "gmi_wait_pi7",
79 "gmi_wr_n_pi0",
80 "dap1_fs_pn0",
81 "dap1_din_pn1",
82 "dap1_dout_pn2",
83 "dap1_sclk_pn3",
84 "dap2_fs_pa2",
85 "dap2_sclk_pa3",
86 "dap2_din_pa4",
87 "dap2_dout_pa5",
88 "spi1_sck_px5",
89 "spi1_mosi_px4",
90 "spi1_cs0_n_px6",
91 "spi2_cs0_n_px3",
92 "spi2_miso_px1",
93 "spi2_mosi_px0",
94 "spi2_sck_px2",
95 "uart2_cts_n_pj5",
96 "uart2_rts_n_pj6";
97 nvidia,function = "gmi";
98 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
99 nvidia,tristate = <TEGRA_PIN_DISABLE>;
100 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
101 };
102 /* Further pins may be used as GPIOs */
103 dap4-din-pp5 {
104 nvidia,pins = "dap4_din_pp5",
105 "dap4_dout_pp6",
106 "dap4_fs_pp4",
107 "dap4_sclk_pp7",
108 "pbb7",
109 "sdmmc1_clk_pz0",
110 "sdmmc1_cmd_pz1",
111 "sdmmc1_dat0_py7",
112 "sdmmc1_dat1_py6",
113 "sdmmc1_dat3_py4",
114 "uart3_cts_n_pa1",
115 "uart3_txd_pw6",
116 "uart3_rxd_pw7";
117 nvidia,function = "rsvd2";
118 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
119 nvidia,tristate = <TEGRA_PIN_DISABLE>;
120 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
121 };
122 lcd-d18-pm2 {
123 nvidia,pins = "lcd_d18_pm2",
124 "lcd_d19_pm3",
125 "lcd_d20_pm4",
126 "lcd_d21_pm5",
127 "lcd_d22_pm6",
128 "lcd_d23_pm7",
129 "lcd_dc0_pn6",
130 "pex_l2_clkreq_n_pcc7";
131 nvidia,function = "rsvd3";
132 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
133 nvidia,tristate = <TEGRA_PIN_DISABLE>;
134 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135 };
136 lcd-cs0-n-pn4 {
137 nvidia,pins = "lcd_cs0_n_pn4",
138 "lcd_sdin_pz2",
139 "pu0",
140 "pu1",
141 "pu2",
142 "pu3",
143 "pu4",
144 "pu5",
145 "pu6",
146 "spi1_miso_px7",
147 "uart3_rts_n_pc0";
148 nvidia,function = "rsvd4";
149 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
150 nvidia,tristate = <TEGRA_PIN_DISABLE>;
151 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
152 };
153 lcd-pwr0-pb2 {
154 nvidia,pins = "lcd_pwr0_pb2",
155 "lcd_sck_pz4",
156 "lcd_sdout_pn5",
157 "lcd_wr_n_pz3";
158 nvidia,function = "hdcp";
159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
161 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
162 };
163 pbb4 {
164 nvidia,pins = "pbb4",
165 "pbb5",
166 "pbb6";
167 nvidia,function = "displayb";
168 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
169 nvidia,tristate = <TEGRA_PIN_DISABLE>;
170 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
171 };
172 /* Multiplexed RDnWR and therefore disabled */
173 lcd-cs1-n-pw0 {
174 nvidia,pins = "lcd_cs1_n_pw0";
175 nvidia,function = "rsvd4";
176 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
177 nvidia,tristate = <TEGRA_PIN_ENABLE>;
178 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
179 };
180 /* Multiplexed GMI_CLK and therefore disabled */
181 owr {
182 nvidia,pins = "owr";
183 nvidia,function = "rsvd3";
184 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
185 nvidia,tristate = <TEGRA_PIN_ENABLE>;
186 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
187 };
188 /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
189 sdmmc3-dat4-pd1 {
190 nvidia,pins = "sdmmc3_dat4_pd1";
191 nvidia,function = "sdmmc3";
192 nvidia,pull = <TEGRA_PIN_PULL_UP>;
193 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
195 };
196 /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
197 sdmmc3-dat5-pd0 {
198 nvidia,pins = "sdmmc3_dat5_pd0";
199 nvidia,function = "sdmmc3";
200 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
202 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
203 };
204
205 /* Colibri BL_ON */
206 pv2 {
207 nvidia,pins = "pv2";
208 nvidia,function = "rsvd4";
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212
213 /* Colibri Backlight PWM<A> */
214 sdmmc3-dat3-pb4 {
215 nvidia,pins = "sdmmc3_dat3_pb4";
216 nvidia,function = "pwm0";
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 };
220
221 /* Colibri CAN_INT */
222 kb-row8-ps0 {
223 nvidia,pins = "kb_row8_ps0";
224 nvidia,function = "kbc";
225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
228 };
229
230 /* Colibri DDC */
231 ddc-scl-pv4 {
232 nvidia,pins = "ddc_scl_pv4",
233 "ddc_sda_pv5";
234 nvidia,function = "i2c4";
235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238 };
239
240 /* Colibri EXT_IO* */
241 gen2-i2c-scl-pt5 {
242 nvidia,pins = "gen2_i2c_scl_pt5",
243 "gen2_i2c_sda_pt6";
244 nvidia,function = "rsvd4";
245 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
246 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
247 nvidia,tristate = <TEGRA_PIN_DISABLE>;
248 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
249 };
250 spdif-in-pk6 {
251 nvidia,pins = "spdif_in_pk6";
252 nvidia,function = "hda";
253 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
255 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
256 };
257
258 /* Colibri GPIO */
259 clk2-out-pw5 {
260 nvidia,pins = "clk2_out_pw5",
261 "pcc2",
262 "pv3",
263 "sdmmc1_dat2_py5";
264 nvidia,function = "rsvd2";
265 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
266 nvidia,tristate = <TEGRA_PIN_DISABLE>;
267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
268 };
269 lcd-pwr1-pc1 {
270 nvidia,pins = "lcd_pwr1_pc1",
271 "pex_l1_clkreq_n_pdd6",
272 "pex_l1_rst_n_pdd5";
273 nvidia,function = "rsvd3";
274 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
275 nvidia,tristate = <TEGRA_PIN_DISABLE>;
276 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
277 };
278 pv1 {
279 nvidia,pins = "pv1",
280 "sdmmc3_dat0_pb7",
281 "sdmmc3_dat1_pb6";
282 nvidia,function = "rsvd1";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
286 };
287
288 /* Colibri HOTPLUG_DETECT (HDMI) */
289 hdmi-int-pn7 {
290 nvidia,pins = "hdmi_int_pn7";
291 nvidia,function = "hdmi";
292 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
293 nvidia,tristate = <TEGRA_PIN_ENABLE>;
294 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
295 };
296
297 /* Colibri I2C */
298 gen1-i2c-scl-pc4 {
299 nvidia,pins = "gen1_i2c_scl_pc4",
300 "gen1_i2c_sda_pc5";
301 nvidia,function = "i2c1";
302 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
305 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
306 };
307
308 /* Colibri LCD (L_* resp. LDD<*>) */
309 lcd-d0-pe0 {
310 nvidia,pins = "lcd_d0_pe0",
311 "lcd_d1_pe1",
312 "lcd_d2_pe2",
313 "lcd_d3_pe3",
314 "lcd_d4_pe4",
315 "lcd_d5_pe5",
316 "lcd_d6_pe6",
317 "lcd_d7_pe7",
318 "lcd_d8_pf0",
319 "lcd_d9_pf1",
320 "lcd_d10_pf2",
321 "lcd_d11_pf3",
322 "lcd_d12_pf4",
323 "lcd_d13_pf5",
324 "lcd_d14_pf6",
325 "lcd_d15_pf7",
326 "lcd_d16_pm0",
327 "lcd_d17_pm1",
328 "lcd_de_pj1",
329 "lcd_hsync_pj3",
330 "lcd_pclk_pb3",
331 "lcd_vsync_pj4";
332 nvidia,function = "displaya";
333 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
334 nvidia,tristate = <TEGRA_PIN_DISABLE>;
335 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
336 };
337 /*
338 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
339 * today's display need DE, disable LCD_M1
340 */
341 lcd-m1-pw1 {
342 nvidia,pins = "lcd_m1_pw1";
343 nvidia,function = "rsvd3";
344 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
345 nvidia,tristate = <TEGRA_PIN_ENABLE>;
346 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347 };
348
349 /* Colibri MMC */
350 kb-row10-ps2 {
351 nvidia,pins = "kb_row10_ps2";
352 nvidia,function = "sdmmc2";
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 };
356 kb-row11-ps3 {
357 nvidia,pins = "kb_row11_ps3",
358 "kb_row12_ps4",
359 "kb_row13_ps5",
360 "kb_row14_ps6",
361 "kb_row15_ps7";
362 nvidia,function = "sdmmc2";
363 nvidia,pull = <TEGRA_PIN_PULL_UP>;
364 nvidia,tristate = <TEGRA_PIN_DISABLE>;
365 };
366 /* Colibri MMC_CD */
367 gmi-wp-n-pc7 {
368 nvidia,pins = "gmi_wp_n_pc7";
369 nvidia,function = "rsvd1";
370 nvidia,pull = <TEGRA_PIN_PULL_UP>;
371 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
373 };
374 /* Multiplexed and therefore disabled */
375 cam-mclk-pcc0 {
376 nvidia,pins = "cam_mclk_pcc0";
377 nvidia,function = "vi_alt3";
378 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
379 nvidia,tristate = <TEGRA_PIN_ENABLE>;
380 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
381 };
382 cam-i2c-scl-pbb1 {
383 nvidia,pins = "cam_i2c_scl_pbb1",
384 "cam_i2c_sda_pbb2";
385 nvidia,function = "rsvd3";
386 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
387 nvidia,tristate = <TEGRA_PIN_ENABLE>;
388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
390 };
391 pbb0 {
392 nvidia,pins = "pbb0",
393 "pcc1";
394 nvidia,function = "rsvd2";
395 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
396 nvidia,tristate = <TEGRA_PIN_ENABLE>;
397 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
398 };
399 pbb3 {
400 nvidia,pins = "pbb3";
401 nvidia,function = "displayb";
402 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
403 nvidia,tristate = <TEGRA_PIN_ENABLE>;
404 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
405 };
406
407 /* Colibri nRESET_OUT */
408 gmi-rst-n-pi4 {
409 nvidia,pins = "gmi_rst_n_pi4";
410 nvidia,function = "gmi";
411 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412 nvidia,tristate = <TEGRA_PIN_DISABLE>;
413 };
414
415 /*
416 * Colibri Parallel Camera (Optional)
417 * pins multiplexed with others and therefore disabled
418 */
419 vi-vsync-pd6 {
420 nvidia,pins = "vi_d0_pt4",
421 "vi_d1_pd5",
422 "vi_d2_pl0",
423 "vi_d3_pl1",
424 "vi_d4_pl2",
425 "vi_d5_pl3",
426 "vi_d6_pl4",
427 "vi_d7_pl5",
428 "vi_d8_pl6",
429 "vi_d9_pl7",
430 "vi_d10_pt2",
431 "vi_d11_pt3",
432 "vi_hsync_pd7",
433 "vi_mclk_pt1",
434 "vi_pclk_pt0",
435 "vi_vsync_pd6";
436 nvidia,function = "vi";
437 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
438 nvidia,tristate = <TEGRA_PIN_ENABLE>;
439 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
440 };
441
442 /* Colibri PWM<B> */
443 sdmmc3-dat2-pb5 {
444 nvidia,pins = "sdmmc3_dat2_pb5";
445 nvidia,function = "pwm1";
446 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
447 nvidia,tristate = <TEGRA_PIN_DISABLE>;
448 };
449
450 /* Colibri PWM<C> */
451 sdmmc3-clk-pa6 {
452 nvidia,pins = "sdmmc3_clk_pa6";
453 nvidia,function = "pwm2";
454 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
455 nvidia,tristate = <TEGRA_PIN_DISABLE>;
456 };
457
458 /* Colibri PWM<D> */
459 sdmmc3-cmd-pa7 {
460 nvidia,pins = "sdmmc3_cmd_pa7";
461 nvidia,function = "pwm3";
462 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463 nvidia,tristate = <TEGRA_PIN_DISABLE>;
464 };
465
466 /* Colibri SSP */
467 ulpi-clk-py0 {
468 nvidia,pins = "ulpi_clk_py0",
469 "ulpi_dir_py1",
470 "ulpi_nxt_py2",
471 "ulpi_stp_py3";
472 nvidia,function = "spi1";
473 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
474 nvidia,tristate = <TEGRA_PIN_DISABLE>;
475 };
476 /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
477 sdmmc3-dat6-pd3 {
478 nvidia,pins = "sdmmc3_dat6_pd3",
479 "sdmmc3_dat7_pd4";
480 nvidia,function = "spdif";
481 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
482 nvidia,tristate = <TEGRA_PIN_ENABLE>;
483 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
484 };
485
486 /* Colibri UART-A */
487 ulpi-data0 {
488 nvidia,pins = "ulpi_data0_po1",
489 "ulpi_data1_po2",
490 "ulpi_data2_po3",
491 "ulpi_data3_po4",
492 "ulpi_data4_po5",
493 "ulpi_data5_po6",
494 "ulpi_data6_po7",
495 "ulpi_data7_po0";
496 nvidia,function = "uarta";
497 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
498 nvidia,tristate = <TEGRA_PIN_DISABLE>;
499 };
500
501 /* Colibri UART-B */
502 gmi-a16-pj7 {
503 nvidia,pins = "gmi_a16_pj7",
504 "gmi_a17_pb0",
505 "gmi_a18_pb1",
506 "gmi_a19_pk7";
507 nvidia,function = "uartd";
508 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
509 nvidia,tristate = <TEGRA_PIN_DISABLE>;
510 };
511
512 /* Colibri UART-C */
513 uart2-rxd {
514 nvidia,pins = "uart2_rxd_pc3",
515 "uart2_txd_pc2";
516 nvidia,function = "uartb";
517 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
518 nvidia,tristate = <TEGRA_PIN_DISABLE>;
519 };
520
521 /* Colibri USBC_DET */
522 spdif-out-pk5 {
523 nvidia,pins = "spdif_out_pk5";
524 nvidia,function = "rsvd2";
525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
527 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
528 };
529
530 /* Colibri USBH_PEN */
531 spi2-cs1-n-pw2 {
532 nvidia,pins = "spi2_cs1_n_pw2";
533 nvidia,function = "spi2_alt";
534 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
535 nvidia,tristate = <TEGRA_PIN_DISABLE>;
536 };
537
538 /* Colibri USBH_OC */
539 spi2-cs2-n-pw3 {
540 nvidia,pins = "spi2_cs2_n_pw3";
541 nvidia,function = "spi2_alt";
542 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
543 nvidia,tristate = <TEGRA_PIN_DISABLE>;
544 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
545 };
546
547 /* Colibri VGA not supported and therefore disabled */
548 crt-hsync-pv6 {
549 nvidia,pins = "crt_hsync_pv6",
550 "crt_vsync_pv7";
551 nvidia,function = "rsvd2";
552 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
553 nvidia,tristate = <TEGRA_PIN_ENABLE>;
554 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
555 };
556
557 /* eMMC (On-module) */
558 sdmmc4-clk-pcc4 {
559 nvidia,pins = "sdmmc4_clk_pcc4",
560 "sdmmc4_cmd_pt7",
561 "sdmmc4_rst_n_pcc3";
562 nvidia,function = "sdmmc4";
563 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
564 nvidia,tristate = <TEGRA_PIN_DISABLE>;
565 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
566 };
567 sdmmc4-dat0-paa0 {
568 nvidia,pins = "sdmmc4_dat0_paa0",
569 "sdmmc4_dat1_paa1",
570 "sdmmc4_dat2_paa2",
571 "sdmmc4_dat3_paa3",
572 "sdmmc4_dat4_paa4",
573 "sdmmc4_dat5_paa5",
574 "sdmmc4_dat6_paa6",
575 "sdmmc4_dat7_paa7";
576 nvidia,function = "sdmmc4";
577 nvidia,pull = <TEGRA_PIN_PULL_UP>;
578 nvidia,tristate = <TEGRA_PIN_DISABLE>;
579 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
580 };
581
582 /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
583 pex-l0-rst-n-pdd1 {
584 nvidia,pins = "pex_l0_rst_n_pdd1",
585 "pex_wake_n_pdd3";
586 nvidia,function = "rsvd3";
587 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588 nvidia,tristate = <TEGRA_PIN_DISABLE>;
589 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
590 };
591 /* LAN_V_BUS, LAN_RESET# (On-module) */
592 pex-l0-clkreq-n-pdd2 {
593 nvidia,pins = "pex_l0_clkreq_n_pdd2",
594 "pex_l0_prsnt_n_pdd0";
595 nvidia,function = "rsvd3";
596 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
597 nvidia,tristate = <TEGRA_PIN_DISABLE>;
598 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
599 };
600
601 /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
602 pex-l2-rst-n-pcc6 {
603 nvidia,pins = "pex_l2_rst_n_pcc6",
604 "pex_l2_prsnt_n_pdd7";
605 nvidia,function = "rsvd3";
606 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
607 nvidia,tristate = <TEGRA_PIN_DISABLE>;
608 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
609 };
610
611 /* Not connected and therefore disabled */
612 clk1-req-pee2 {
613 nvidia,pins = "clk1_req_pee2",
614 "pex_l1_prsnt_n_pdd4";
615 nvidia,function = "rsvd3";
616 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
617 nvidia,tristate = <TEGRA_PIN_ENABLE>;
618 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
619 };
620 clk2-req-pcc5 {
621 nvidia,pins = "clk2_req_pcc5",
622 "clk3_out_pee0",
623 "clk3_req_pee1",
624 "clk_32k_out_pa0",
625 "hdmi_cec_pee3",
626 "sys_clk_req_pz5";
627 nvidia,function = "rsvd2";
628 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
629 nvidia,tristate = <TEGRA_PIN_ENABLE>;
630 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
631 };
632 gmi-dqs-pi2 {
633 nvidia,pins = "gmi_dqs_pi2",
634 "kb_col2_pq2",
635 "kb_col3_pq3",
636 "kb_col4_pq4",
637 "kb_col5_pq5",
638 "kb_row4_pr4";
639 nvidia,function = "rsvd4";
640 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
641 nvidia,tristate = <TEGRA_PIN_ENABLE>;
642 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
643 };
644 kb-col0-pq0 {
645 nvidia,pins = "kb_col0_pq0",
646 "kb_col1_pq1",
647 "kb_col6_pq6",
648 "kb_col7_pq7",
649 "kb_row5_pr5",
650 "kb_row6_pr6",
651 "kb_row7_pr7",
652 "kb_row9_ps1";
653 nvidia,function = "kbc";
654 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
655 nvidia,tristate = <TEGRA_PIN_ENABLE>;
656 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
657 };
658 kb-row0-pr0 {
659 nvidia,pins = "kb_row0_pr0",
660 "kb_row1_pr1",
661 "kb_row2_pr2",
662 "kb_row3_pr3";
663 nvidia,function = "rsvd3";
664 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
665 nvidia,tristate = <TEGRA_PIN_ENABLE>;
666 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
667 };
668 lcd-pwr2-pc6 {
669 nvidia,pins = "lcd_pwr2_pc6";
670 nvidia,function = "hdcp";
671 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
672 nvidia,tristate = <TEGRA_PIN_ENABLE>;
673 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
674 };
675
676 /* Power I2C (On-module) */
677 pwr-i2c-scl-pz6 {
678 nvidia,pins = "pwr_i2c_scl_pz6",
679 "pwr_i2c_sda_pz7";
680 nvidia,function = "i2cpwr";
681 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
682 nvidia,tristate = <TEGRA_PIN_DISABLE>;
683 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
684 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
685 };
686
687 /*
688 * THERMD_ALERT#, unlatched I2C address pin of LM95245
689 * temperature sensor therefore requires disabling for
690 * now
691 */
692 lcd-dc1-pd2 {
693 nvidia,pins = "lcd_dc1_pd2";
694 nvidia,function = "rsvd3";
695 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
696 nvidia,tristate = <TEGRA_PIN_ENABLE>;
697 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
698 };
699
700 /* TOUCH_PEN_INT# (On-module) */
701 pv0 {
702 nvidia,pins = "pv0";
703 nvidia,function = "rsvd1";
704 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
705 nvidia,tristate = <TEGRA_PIN_DISABLE>;
706 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
707 };
708 };
709 };
710
711 serial@70006040 {
712 compatible = "nvidia,tegra30-hsuart";
713 reset-names = "serial";
714 /delete-property/ reg-shift;
715 };
716
717 serial@70006300 {
718 compatible = "nvidia,tegra30-hsuart";
719 reset-names = "serial";
720 /delete-property/ reg-shift;
721 };
722
723 hdmi_ddc: i2c@7000c700 {
724 clock-frequency = <10000>;
725 };
726
727 /*
728 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
729 * touch screen controller (On-module)
730 */
731 i2c@7000d000 {
732 status = "okay";
733 clock-frequency = <100000>;
734
735 /* SGTL5000 audio codec */
736 sgtl5000: codec@a {
737 compatible = "fsl,sgtl5000";
738 reg = <0x0a>;
739 #sound-dai-cells = <0>;
740 VDDA-supply = <®_module_3v3_audio>;
741 VDDD-supply = <®_1v8_vio>;
742 VDDIO-supply = <®_module_3v3>;
743 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
744 };
745
746 pmic: pmic@2d {
747 compatible = "ti,tps65911";
748 reg = <0x2d>;
749
750 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
751 #interrupt-cells = <2>;
752 interrupt-controller;
753 wakeup-source;
754
755 ti,system-power-controller;
756
757 #gpio-cells = <2>;
758 gpio-controller;
759
760 vcc1-supply = <®_module_3v3>;
761 vcc2-supply = <®_module_3v3>;
762 vcc3-supply = <®_1v8_vio>;
763 vcc4-supply = <®_module_3v3>;
764 vcc5-supply = <®_module_3v3>;
765 vcc6-supply = <®_1v8_vio>;
766 vcc7-supply = <®_5v0_charge_pump>;
767 vccio-supply = <®_module_3v3>;
768
769 regulators {
770 vdd1_reg: vdd1 {
771 regulator-name = "+V1.35_VDDIO_DDR";
772 regulator-min-microvolt = <1350000>;
773 regulator-max-microvolt = <1350000>;
774 regulator-always-on;
775 };
776
777 /* SW2: unused */
778
779 vddctrl_reg: vddctrl {
780 regulator-name = "+V1.0_VDD_CPU";
781 regulator-min-microvolt = <800000>;
782 regulator-max-microvolt = <1250000>;
783 regulator-coupled-with = <&vdd_core>;
784 regulator-coupled-max-spread = <300000>;
785 regulator-max-step-microvolt = <100000>;
786 regulator-always-on;
787
788 nvidia,tegra-cpu-regulator;
789 };
790
791 reg_1v8_vio: vio {
792 regulator-name = "+V1.8";
793 regulator-min-microvolt = <1800000>;
794 regulator-max-microvolt = <1800000>;
795 regulator-always-on;
796 };
797
798 /* LDO1: unused */
799
800 /*
801 * EN_+V3.3 switching via FET:
802 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
803 * see also +V3.3 fixed supply
804 */
805 ldo2_reg: ldo2 {
806 regulator-name = "EN_+V3.3";
807 regulator-min-microvolt = <3300000>;
808 regulator-max-microvolt = <3300000>;
809 regulator-always-on;
810 };
811
812 /* LDO3: unused */
813
814 ldo4_reg: ldo4 {
815 regulator-name = "+V1.2_VDD_RTC";
816 regulator-min-microvolt = <1200000>;
817 regulator-max-microvolt = <1200000>;
818 regulator-always-on;
819 };
820
821 /*
822 * +V2.8_AVDD_VDAC:
823 * only required for (unsupported) analog RGB
824 */
825 ldo5_reg: ldo5 {
826 regulator-name = "+V2.8_AVDD_VDAC";
827 regulator-min-microvolt = <2800000>;
828 regulator-max-microvolt = <2800000>;
829 regulator-always-on;
830 };
831
832 /*
833 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
834 * but LDO6 can't set voltage in 50mV
835 * granularity
836 */
837 ldo6_reg: ldo6 {
838 regulator-name = "+V1.05_AVDD_PLLE";
839 regulator-min-microvolt = <1100000>;
840 regulator-max-microvolt = <1100000>;
841 };
842
843 ldo7_reg: ldo7 {
844 regulator-name = "+V1.2_AVDD_PLL";
845 regulator-min-microvolt = <1200000>;
846 regulator-max-microvolt = <1200000>;
847 regulator-always-on;
848 };
849
850 ldo8_reg: ldo8 {
851 regulator-name = "+V1.0_VDD_DDR_HS";
852 regulator-min-microvolt = <1000000>;
853 regulator-max-microvolt = <1000000>;
854 regulator-always-on;
855 };
856 };
857 };
858
859 /* STMPE811 touch screen controller */
860 touchscreen@41 {
861 compatible = "st,stmpe811";
862 reg = <0x41>;
863 irq-gpio = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
864 id = <0>;
865 blocks = <0x5>;
866 irq-trigger = <0x1>;
867 /* 3.25 MHz ADC clock speed */
868 st,adc-freq = <1>;
869 /* 12-bit ADC */
870 st,mod-12b = <1>;
871 /* internal ADC reference */
872 st,ref-sel = <0>;
873 /* ADC converstion time: 80 clocks */
874 st,sample-time = <4>;
875 /* forbid to use ADC channels 3-0 (touch) */
876
877 stmpe_adc {
878 compatible = "st,stmpe-adc";
879 st,norequest-mask = <0x0F>;
880 };
881
882 stmpe_touchscreen {
883 compatible = "st,stmpe-ts";
884 /* 8 sample average control */
885 st,ave-ctrl = <3>;
886 /* 7 length fractional part in z */
887 st,fraction-z = <7>;
888 /*
889 * 50 mA typical 80 mA max touchscreen drivers
890 * current limit value
891 */
892 st,i-drive = <1>;
893 /* 1 ms panel driver settling time */
894 st,settling = <3>;
895 /* 5 ms touch detect interrupt delay */
896 st,touch-det-delay = <5>;
897 };
898 };
899
900 /*
901 * LM95245 temperature sensor
902 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
903 */
904 temp-sensor@4c {
905 compatible = "national,lm95245";
906 reg = <0x4c>;
907 };
908
909 /* SW: +V1.2_VDD_CORE */
910 vdd_core: regulator@60 {
911 compatible = "ti,tps62362";
912 reg = <0x60>;
913
914 regulator-name = "tps62362-vout";
915 regulator-min-microvolt = <900000>;
916 regulator-max-microvolt = <1400000>;
917 regulator-coupled-with = <&vddctrl_reg>;
918 regulator-coupled-max-spread = <300000>;
919 regulator-max-step-microvolt = <100000>;
920 regulator-boot-on;
921 regulator-always-on;
922
923 nvidia,tegra-core-regulator;
924 };
925 };
926
927 pmc@7000e400 {
928 nvidia,invert-interrupt;
929 nvidia,suspend-mode = <1>;
930 nvidia,cpu-pwr-good-time = <5000>;
931 nvidia,cpu-pwr-off-time = <5000>;
932 nvidia,core-pwr-good-time = <3845 3845>;
933 nvidia,core-pwr-off-time = <0>;
934 nvidia,core-power-req-active-high;
935 nvidia,sys-clock-req-active-high;
936 core-supply = <&vdd_core>;
937
938 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
939 i2c-thermtrip {
940 nvidia,i2c-controller-id = <4>;
941 nvidia,bus-addr = <0x2d>;
942 nvidia,reg-addr = <0x3f>;
943 nvidia,reg-data = <0x1>;
944 };
945 };
946
947 hda@70030000 {
948 status = "okay";
949 };
950
951 ahub@70080000 {
952 i2s@70080500 {
953 status = "okay";
954 };
955 };
956
957 /* eMMC */
958 mmc@78000600 {
959 status = "okay";
960 bus-width = <8>;
961 non-removable;
962 vmmc-supply = <®_module_3v3>; /* VCC */
963 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
964 mmc-ddr-1_8v;
965 };
966
967 /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
968 usb@7d004000 {
969 status = "okay";
970 #address-cells = <1>;
971 #size-cells = <0>;
972
973 ethernet@1 {
974 compatible = "usbb95,772b";
975 reg = <1>;
976 local-mac-address = [00 00 00 00 00 00];
977 };
978 };
979
980 usb-phy@7d004000 {
981 status = "okay";
982 vbus-supply = <®_lan_v_bus>;
983 };
984
985 clk32k_in: clock-xtal1 {
986 compatible = "fixed-clock";
987 #clock-cells = <0>;
988 clock-frequency = <32768>;
989 };
990
991 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
992 compatible = "regulator-fixed";
993 regulator-name = "+V1.8_AVDD_HDMI_PLL";
994 regulator-min-microvolt = <1800000>;
995 regulator-max-microvolt = <1800000>;
996 enable-active-high;
997 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
998 vin-supply = <®_1v8_vio>;
999 };
1000
1001 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1002 compatible = "regulator-fixed";
1003 regulator-name = "+V3.3_AVDD_HDMI";
1004 regulator-min-microvolt = <3300000>;
1005 regulator-max-microvolt = <3300000>;
1006 enable-active-high;
1007 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1008 vin-supply = <®_module_3v3>;
1009 };
1010
1011 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1012 compatible = "regulator-fixed";
1013 regulator-name = "+V5.0";
1014 regulator-min-microvolt = <5000000>;
1015 regulator-max-microvolt = <5000000>;
1016 regulator-always-on;
1017 };
1018
1019 reg_lan_v_bus: regulator-lan-v-bus {
1020 compatible = "regulator-fixed";
1021 regulator-name = "LAN_V_BUS";
1022 regulator-min-microvolt = <5000000>;
1023 regulator-max-microvolt = <5000000>;
1024 enable-active-high;
1025 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
1026 };
1027
1028 reg_module_3v3: regulator-module-3v3 {
1029 compatible = "regulator-fixed";
1030 regulator-name = "+V3.3";
1031 regulator-min-microvolt = <3300000>;
1032 regulator-max-microvolt = <3300000>;
1033 regulator-always-on;
1034 };
1035
1036 reg_module_3v3_audio: regulator-module-3v3-audio {
1037 compatible = "regulator-fixed";
1038 regulator-name = "+V3.3_AUDIO_AVDD_S";
1039 regulator-min-microvolt = <3300000>;
1040 regulator-max-microvolt = <3300000>;
1041 regulator-always-on;
1042 };
1043
1044 sound {
1045 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
1046 "nvidia,tegra-audio-sgtl5000";
1047 nvidia,model = "Toradex Colibri T30";
1048 nvidia,audio-routing =
1049 "Headphone Jack", "HP_OUT",
1050 "LINE_IN", "Line In Jack",
1051 "MIC_IN", "Mic Jack";
1052 nvidia,i2s-controller = <&tegra_i2s2>;
1053 nvidia,audio-codec = <&sgtl5000>;
1054 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1055 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1056 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1057 clock-names = "pll_a", "pll_a_out0", "mclk";
1058
1059 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1060 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1061
1062 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1063 <&tegra_car TEGRA30_CLK_EXTERN1>;
1064 };
1065 };
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