1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2014 Soeren Moch <smoch@web.de>
4
5 /dts-v1/;
6
7 #include "imx6q.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10
11 / {
12 model = "TBS2910 Matrix ARM mini PC";
13 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
14
15 chosen {
16 stdout-path = &uart1;
17 };
18
19 aliases {
20 mmc0 = &usdhc2;
21 mmc1 = &usdhc3;
22 mmc2 = &usdhc4;
23 /delete-property/ mmc3;
24 };
25
26 memory@10000000 {
27 device_type = "memory";
28 reg = <0x10000000 0x80000000>;
29 };
30
31 fan {
32 compatible = "gpio-fan";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_fan>;
35 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
36 gpio-fan,speed-map = <0 0
37 3000 1>;
38 };
39
40 ir_recv {
41 compatible = "gpio-ir-receiver";
42 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_ir>;
45 };
46
47 leds {
48 compatible = "gpio-leds";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_gpio_leds>;
51
52 led-blue {
53 label = "blue_status_led";
54 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
55 default-state = "keep";
56 };
57 };
58
59 reg_2p5v: regulator-2p5v {
60 compatible = "regulator-fixed";
61 regulator-name = "2P5V";
62 regulator-min-microvolt = <2500000>;
63 regulator-max-microvolt = <2500000>;
64 };
65
66 reg_3p3v: regulator-3p3v {
67 compatible = "regulator-fixed";
68 regulator-name = "3P3V";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 };
72
73 reg_5p0v: regulator-5p0v {
74 compatible = "regulator-fixed";
75 regulator-name = "5P0V";
76 regulator-min-microvolt = <5000000>;
77 regulator-max-microvolt = <5000000>;
78 };
79
80 sound-sgtl5000 {
81 audio-codec = <&sgtl5000>;
82 audio-routing =
83 "MIC_IN", "Mic Jack",
84 "Mic Jack", "Mic Bias",
85 "Headphone Jack", "HP_OUT";
86 compatible = "fsl,imx-audio-sgtl5000";
87 model = "On-board Codec";
88 mux-ext-port = <3>;
89 mux-int-port = <1>;
90 ssi-controller = <&ssi1>;
91 };
92
93 spdif_out: spdif-out {
94 compatible = "linux,spdif-dit";
95 #sound-dai-cells = <0>;
96 };
97
98 sound-spdif {
99 compatible = "fsl,imx-audio-spdif";
100 model = "On-board SPDIF";
101 audio-cpu = <&spdif>;
102 audio-codec = <&spdif_out>;
103 };
104 };
105
106 &audmux {
107 status = "okay";
108 };
109
110 &fec {
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_enet>;
113 phy-mode = "rgmii-id";
114 phy-handle = <&phy>;
115 status = "okay";
116
117 mdio {
118 #address-cells = <1>;
119 #size-cells = <0>;
120
121 phy: ethernet-phy@4 {
122 reg = <4>;
123 qca,clk-out-frequency = <125000000>;
124 reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
125 reset-assert-us = <10000>;
126 };
127 };
128 };
129
130 &hdmi {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_hdmi>;
133 ddc-i2c-bus = <&i2c2>;
134 status = "okay";
135 };
136
137 &i2c1 {
138 clock-frequency = <100000>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c1>;
141 status = "okay";
142
143 sgtl5000: sgtl5000@a {
144 clocks = <&clks IMX6QDL_CLK_CKO>;
145 compatible = "fsl,sgtl5000";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_sgtl5000>;
148 reg = <0x0a>;
149 #sound-dai-cells = <0>;
150 VDDA-supply = <®_2p5v>;
151 VDDIO-supply = <®_3p3v>;
152 };
153 };
154
155 &i2c2 {
156 clock-frequency = <100000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c2>;
159 status = "okay";
160 };
161
162 &i2c3 {
163 clock-frequency = <100000>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c3>;
166 status = "okay";
167
168 rtc: rtc@68 {
169 compatible = "dallas,ds1307";
170 reg = <0x68>;
171 };
172 };
173
174 &pcie {
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_pcie>;
177 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
178 status = "okay";
179 };
180
181 &sata {
182 fsl,transmit-level-mV = <1104>;
183 fsl,transmit-boost-mdB = <3330>;
184 fsl,transmit-atten-16ths = <16>;
185 fsl,receive-eq-mdB = <3000>;
186 status = "okay";
187 };
188
189 &snvs_poweroff {
190 status = "okay";
191 };
192
193 &spdif {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_spdif>;
196 status = "okay";
197 };
198
199 &ssi1 {
200 status = "okay";
201 };
202
203 &uart1 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_uart1>;
206 status = "okay";
207 };
208
209 &uart2 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_uart2>;
212 status = "okay";
213 };
214
215 &usbh1 {
216 vbus-supply = <®_5p0v>;
217 status = "okay";
218 };
219
220 &usbotg {
221 vbus-supply = <®_5p0v>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_usbotg>;
224 disable-over-current;
225 status = "okay";
226 };
227
228 &usdhc2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_usdhc2>;
231 bus-width = <4>;
232 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
233 vmmc-supply = <®_3p3v>;
234 vqmmc-supply = <®_3p3v>;
235 voltage-ranges = <3300 3300>;
236 no-1-8-v;
237 status = "okay";
238 };
239
240 &usdhc3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_usdhc3>;
243 bus-width = <4>;
244 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
245 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
246 vmmc-supply = <®_3p3v>;
247 vqmmc-supply = <®_3p3v>;
248 voltage-ranges = <3300 3300>;
249 no-1-8-v;
250 status = "okay";
251 };
252
253 &usdhc4 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_usdhc4>;
256 bus-width = <8>;
257 vmmc-supply = <®_3p3v>;
258 vqmmc-supply = <®_3p3v>;
259 voltage-ranges = <3300 3300>;
260 non-removable;
261 no-1-8-v;
262 status = "okay";
263 };
264
265 &iomuxc {
266 pinctrl_enet: enetgrp {
267 fsl,pins = <
268 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
269 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
270 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
271 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
272 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
273 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
274 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
275 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
276 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
277 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
278 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
279 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
280 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
281 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
282 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
283 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
284 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
285 >;
286 };
287
288 pinctrl_gpio_fan: gpiofangrp {
289 fsl,pins = <
290 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
291 >;
292 };
293
294 pinctrl_gpio_leds: gpioledsgrp {
295 fsl,pins = <
296 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
297 >;
298 };
299
300 pinctrl_hdmi: hdmigrp {
301 fsl,pins = <
302 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
303 >;
304 };
305
306 pinctrl_i2c1: i2c1grp {
307 fsl,pins = <
308 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
309 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
310 >;
311 };
312
313 pinctrl_i2c2: i2c2grp {
314 fsl,pins = <
315 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
316 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
317 >;
318 };
319
320 pinctrl_i2c3: i2c3grp {
321 fsl,pins = <
322 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
323 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
324 >;
325 };
326
327 pinctrl_ir: irgrp {
328 fsl,pins = <
329 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
330 >;
331 };
332
333 pinctrl_pcie: pciegrp {
334 fsl,pins = <
335 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
336 >;
337 };
338
339 pinctrl_sgtl5000: sgtl5000grp {
340 fsl,pins = <
341 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
342 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
343 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
344 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
345 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
346 >;
347 };
348
349 pinctrl_spdif: spdifgrp {
350 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
351 >;
352 };
353
354 pinctrl_uart1: uart1grp {
355 fsl,pins = <
356 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
357 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
358 >;
359 };
360
361 pinctrl_uart2: uart2grp {
362 fsl,pins = <
363 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
364 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
365 >;
366 };
367
368 pinctrl_usbotg: usbotggrp {
369 fsl,pins = <
370 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
371 >;
372 };
373
374 pinctrl_usdhc2: usdhc2grp {
375 fsl,pins = <
376 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
377 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
378 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
379 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
380 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
381 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
382 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
383 >;
384 };
385
386 pinctrl_usdhc3: usdhc3grp {
387 fsl,pins = <
388 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
389 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
390 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
391 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
392 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
393 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
394 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
395 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
396 >;
397 };
398
399 pinctrl_usdhc4: usdhc4grp {
400 fsl,pins = <
401 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
402 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
403 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
404 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
405 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
406 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
407 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
408 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
409 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
410 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
411 >;
412 };
413 };
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