1 // SPDX-License-Identifier: GPL-2.0 OR X11
2 /*
3 * Copyright 2017 (C) Priit Laes <plaes@plaes.org>
4 * Copyright 2018 (C) Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
5 * Copyright 2019 (C) Pengutronix, Marco Felsch <kernel@pengutronix.de>
6 *
7 * Based on initial work by Nikita Yushchenko <nyushchenko at dev.rtsoft.ru>
8 */
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/sound/fsl-imx-audmux.h>
12
13 / {
14 reg_1p0v_s0: regulator-1p0v-s0 {
15 compatible = "regulator-fixed";
16 regulator-name = "V_1V0_S0";
17 regulator-min-microvolt = <1000000>;
18 regulator-max-microvolt = <1000000>;
19 regulator-always-on;
20 regulator-boot-on;
21 vin-supply = <®_smarc_suppy>;
22 };
23
24 reg_1p35v_vcoredig_s5: regulator-1p35v-vcoredig-s5 {
25 compatible = "regulator-fixed";
26 regulator-name = "V_1V35_VCOREDIG_S5";
27 regulator-min-microvolt = <1350000>;
28 regulator-max-microvolt = <1350000>;
29 regulator-always-on;
30 regulator-boot-on;
31 vin-supply = <®_3p3v_s5>;
32 };
33
34 reg_1p8v_s5: regulator-1p8v-s5 {
35 compatible = "regulator-fixed";
36 regulator-name = "V_1V8_S5";
37 regulator-min-microvolt = <1800000>;
38 regulator-max-microvolt = <1800000>;
39 regulator-always-on;
40 regulator-boot-on;
41 vin-supply = <®_3p3v_s5>;
42 };
43
44 reg_3p3v_s0: regulator-3p3v-s0 {
45 compatible = "regulator-fixed";
46 regulator-name = "V_3V3_S0";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 regulator-always-on;
50 regulator-boot-on;
51 vin-supply = <®_3p3v_s5>;
52 };
53
54 reg_3p3v_s5: regulator-3p3v-s5 {
55 compatible = "regulator-fixed";
56 regulator-name = "V_3V3_S5";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-always-on;
60 regulator-boot-on;
61 vin-supply = <®_smarc_suppy>;
62 };
63
64 reg_sdio: regulator-sdio {
65 compatible = "regulator-fixed";
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_reg_sdio>;
68 regulator-name = "V_3V3_SD";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 off-on-delay-us = <20000>;
74 };
75
76 reg_smarc_lcdbklt: regulator-smarc-lcdbklt {
77 compatible = "regulator-fixed";
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_lcdbklt_en>;
80 regulator-name = "LCD_BKLT_EN";
81 regulator-min-microvolt = <1800000>;
82 regulator-max-microvolt = <1800000>;
83 gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 reg_smarc_lcdvdd: regulator-smarc-lcdvdd {
88 compatible = "regulator-fixed";
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_lcdvdd_en>;
91 regulator-name = "LCD_VDD_EN";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
95 enable-active-high;
96 };
97
98 reg_smarc_rtc: regulator-smarc-rtc {
99 compatible = "regulator-fixed";
100 regulator-name = "V_IN_RTC_BATT";
101 regulator-min-microvolt = <3300000>;
102 regulator-max-microvolt = <3300000>;
103 regulator-always-on;
104 regulator-boot-on;
105 };
106
107 /* Module supply range can be 3.00V ... 5.25V */
108 reg_smarc_suppy: regulator-smarc-supply {
109 compatible = "regulator-fixed";
110 regulator-name = "V_IN_WIDE";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 regulator-always-on;
114 regulator-boot-on;
115 };
116
117 lcd: lcd {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 compatible = "fsl,imx-parallel-display";
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_lcd>;
123 status = "disabled";
124
125 port@0 {
126 reg = <0>;
127
128 lcd_in: endpoint {
129 };
130 };
131
132 port@1 {
133 reg = <1>;
134
135 lcd_out: endpoint {
136 };
137 };
138 };
139
140 lcd_backlight: lcd-backlight {
141 compatible = "pwm-backlight";
142 pwms = <&pwm4 0 5000000 0>;
143 pwm-names = "LCD_BKLT_PWM";
144
145 brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
146 default-brightness-level = <4>;
147
148 power-supply = <®_smarc_lcdbklt>;
149 status = "disabled";
150 };
151
152 i2c_intern: i2c-0 {
153 compatible = "i2c-gpio";
154 pinctrl-names = "default";
155 pinctrl-0 = <&pinctrl_i2c_gpio_intern>;
156 sda-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
157 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
158 i2c-gpio,delay-us = <2>; /* ~100 kHz */
159 #address-cells = <1>;
160 #size-cells = <0>;
161 };
162
163 i2c_lcd: i2c-1 {
164 compatible = "i2c-gpio";
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_i2c_gpio_lcd>;
167 sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
168 scl-gpios = <&gpio1 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
169 i2c-gpio,delay-us = <2>; /* ~100 kHz */
170 #address-cells = <1>;
171 #size-cells = <0>;
172 status = "disabled";
173 };
174
175 i2c_cam: i2c-2 {
176 compatible = "i2c-gpio";
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c_gpio_cam>;
179 sda-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
180 scl-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
181 i2c-gpio,delay-us = <2>; /* ~100 kHz */
182 #address-cells = <1>;
183 #size-cells = <0>;
184 status = "disabled";
185 };
186 };
187
188 /* I2S0, I2S1 */
189 &audmux {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_audmux>;
192
193 mux-ssi1 {
194 fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
195 fsl,port-config = <
196 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) |
197 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT3) |
198 IMX_AUDMUX_V2_PTCR_SYN |
199 IMX_AUDMUX_V2_PTCR_TFSDIR |
200 IMX_AUDMUX_V2_PTCR_TCLKDIR)
201 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT3)
202 >;
203 };
204
205 mux-aud3 {
206 fsl,audmux-port = <MX51_AUDMUX_PORT3>;
207 fsl,port-config = <
208 IMX_AUDMUX_V2_PTCR_SYN
209 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
210 >;
211 };
212
213 mux-ssi2 {
214 fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>;
215 fsl,port-config = <
216 (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) |
217 IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT4) |
218 IMX_AUDMUX_V2_PTCR_SYN |
219 IMX_AUDMUX_V2_PTCR_TFSDIR |
220 IMX_AUDMUX_V2_PTCR_TCLKDIR)
221 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT4)
222 >;
223 };
224
225 mux-aud4 {
226 fsl,audmux-port = <MX51_AUDMUX_PORT4>;
227 fsl,port-config = <
228 IMX_AUDMUX_V2_PTCR_SYN
229 IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT2_SSI1)
230 >;
231 };
232 };
233
234 /* CAN0 */
235 &can1 {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_flexcan1>;
238 };
239
240 /* CAN1 */
241 &can2 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_flexcan2>;
244 };
245
246 /* SPI1 */
247 &ecspi2 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_ecspi2>;
250 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>,
251 <&gpio2 27 GPIO_ACTIVE_LOW>;
252 };
253
254 /* SPI0 */
255 &ecspi4 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_ecspi4>;
258 cs-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>,
259 <&gpio3 29 GPIO_ACTIVE_LOW>,
260 <&gpio3 25 GPIO_ACTIVE_LOW>;
261 status = "okay";
262
263 /* default boot source: workaround #1 for errata ERR006282 */
264 smarc_flash: flash@0 {
265 compatible = "jedec,spi-nor";
266 reg = <0>;
267 spi-max-frequency = <20000000>;
268 };
269 };
270
271 /* GBE */
272 &fec {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_enet>;
275 phy-connection-type = "rgmii-id";
276 phy-handle = <ðphy>;
277
278 mdio {
279 #address-cells = <1>;
280 #size-cells = <0>;
281
282 ethphy: ethernet-phy@1 {
283 compatible = "ethernet-phy-ieee802.3-c22";
284 reg = <1>;
285 reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
286 reset-assert-us = <1000>;
287 };
288 };
289 };
290
291 &hdmi {
292 ddc-i2c-bus = <&i2c2>;
293 };
294
295 &i2c_intern {
296 pmic@8 {
297 compatible = "fsl,pfuze100";
298 reg = <0x08>;
299
300 regulators {
301 reg_v_core_s0: sw1ab {
302 regulator-name = "V_CORE_S0";
303 regulator-min-microvolt = <300000>;
304 regulator-max-microvolt = <1875000>;
305 regulator-boot-on;
306 regulator-always-on;
307 };
308
309 reg_vddsoc_s0: sw1c {
310 regulator-name = "V_VDDSOC_S0";
311 regulator-min-microvolt = <300000>;
312 regulator-max-microvolt = <1875000>;
313 regulator-boot-on;
314 regulator-always-on;
315 };
316
317 reg_3p15v_s0: sw2 {
318 regulator-name = "V_3V15_S0";
319 regulator-min-microvolt = <800000>;
320 regulator-max-microvolt = <3300000>;
321 regulator-boot-on;
322 regulator-always-on;
323 };
324
325 /* sw3a/b is used in dual mode, but driver does not
326 * support it. Although, there's no need to control
327 * DDR power - so just leaving dummy entries for sw3a
328 * and sw3b for now.
329 */
330 sw3a {
331 regulator-min-microvolt = <400000>;
332 regulator-max-microvolt = <1975000>;
333 regulator-boot-on;
334 regulator-always-on;
335 };
336
337 sw3b {
338 regulator-min-microvolt = <400000>;
339 regulator-max-microvolt = <1975000>;
340 regulator-boot-on;
341 regulator-always-on;
342 };
343
344 reg_1p8v_s0: sw4 {
345 regulator-name = "V_1V8_S0";
346 regulator-min-microvolt = <800000>;
347 regulator-max-microvolt = <3300000>;
348 regulator-boot-on;
349 regulator-always-on;
350 };
351
352 /* Regulator for USB */
353 reg_5p0v_s0: swbst {
354 regulator-name = "V_5V0_S0";
355 regulator-min-microvolt = <5000000>;
356 regulator-max-microvolt = <5150000>;
357 regulator-boot-on;
358 };
359
360 reg_vsnvs: vsnvs {
361 regulator-min-microvolt = <1000000>;
362 regulator-max-microvolt = <3000000>;
363 regulator-boot-on;
364 regulator-always-on;
365 };
366
367 reg_vrefddr: vrefddr {
368 regulator-boot-on;
369 regulator-always-on;
370 };
371
372 vgen1 {
373 regulator-min-microvolt = <800000>;
374 regulator-max-microvolt = <1550000>;
375 };
376
377 vgen2 {
378 regulator-min-microvolt = <800000>;
379 regulator-max-microvolt = <1550000>;
380 };
381
382 vgen3 {
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <3300000>;
385 };
386
387 vgen4 {
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <3300000>;
390 };
391
392 vgen5 {
393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <3300000>;
395 };
396
397 vgen6 {
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <3300000>;
400 };
401 };
402 };
403 };
404
405 /* I2C_GP */
406 &i2c1 {
407 clock-frequency = <375000>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_i2c1>;
410 };
411
412 /* HDMI_CTRL */
413 &i2c2 {
414 clock-frequency = <100000>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_i2c2>;
417 };
418
419 /* I2C_PM */
420 &i2c3 {
421 clock-frequency = <375000>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_i2c3>;
424 status = "okay";
425
426 smarc_eeprom: eeprom@50 {
427 compatible = "atmel,24c32";
428 reg = <0x50>;
429 pagesize = <32>;
430 };
431 };
432
433 &iomuxc {
434 pinctrl-names = "default";
435 pinctrl-0 = <&pinctrl_mgmt_gpios &pinctrl_gpio>;
436
437 pinctrl_audmux: audmuxgrp {
438 fsl,pins = <
439 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
440 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
441 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
442 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
443
444 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
445 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
446 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
447 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
448
449 /* AUDIO MCLK */
450 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x000b0
451 >;
452 };
453
454 pinctrl_ecspi2: ecspi2grp {
455 fsl,pins = <
456 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
457 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
458 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
459
460 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b0 /* CS0 */
461 MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b0 /* CS1 */
462 >;
463 };
464
465 pinctrl_ecspi4: ecspi4grp {
466 fsl,pins = <
467 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
468 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
469 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
470
471 /* SPI_IMX_CS2# - connected to internal flash */
472 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x1b0b0
473 /* SPI_IMX_CS0# - connected to SMARC SPI0_CS0# */
474 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
475 /* SPI4_CS3# - connected to SMARC SPI0_CS1# */
476 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x1b0b0
477 >;
478 };
479
480 pinctrl_flexcan1: flexcan1grp {
481 fsl,pins = <
482 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
483 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
484 >;
485 };
486
487 pinctrl_flexcan2: flexcan2grp {
488 fsl,pins = <
489 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
490 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
491 >;
492 };
493
494 pinctrl_gpio: gpiogrp {
495 fsl,pins = <
496 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b0 /* GPIO0 / CAM0_PWR# */
497 MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b0 /* GPIO1 / CAM1_PWR# */
498 MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b0 /* GPIO2 / CAM0_RST# */
499 MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b0 /* GPIO3 / CAM1_RST# */
500 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b0 /* GPIO4 / HDA_RST# */
501 MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b0 /* GPIO5 / PWM_OUT */
502 MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b0 /* GPIO6 / TACHIN */
503 MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 /* GPIO7 / PCAM_FLD */
504 MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b0 /* GPIO8 / CAN0_ERR# */
505 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b0 /* GPIO9 / CAN1_ERR# */
506 MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b0 /* GPIO10 */
507 MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b0 /* GPIO11 */
508 >;
509 };
510
511 pinctrl_enet: enetgrp {
512 fsl,pins = <
513 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
514 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
515 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
516 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
517 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
518 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
519 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
520 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
521 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
522 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
523 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
524 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
525
526 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
527 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
528 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
529 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */
530 >;
531 };
532
533 pinctrl_i2c_gpio_cam: i2c-gpiocamgrp {
534 fsl,pins = <
535 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* SCL */
536 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* SDA */
537 >;
538 };
539
540 pinctrl_i2c_gpio_intern: i2c-gpiointerngrp {
541 fsl,pins = <
542 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* SCL */
543 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* SDA */
544 >;
545 };
546
547 pinctrl_i2c_gpio_lcd: i2c-gpiolcdgrp {
548 fsl,pins = <
549 MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 /* SCL */
550 MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0 /* SDA */
551 >;
552 };
553
554 pinctrl_i2c1: i2c1grp {
555 fsl,pins = <
556 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
557 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
558 >;
559 };
560
561 pinctrl_i2c2: i2c2grp {
562 fsl,pins = <
563 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
564 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
565 >;
566 };
567
568 pinctrl_i2c3: i2c3grp {
569 fsl,pins = <
570 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
571 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
572 >;
573 };
574
575 pinctrl_lcd: lcdgrp {
576 fsl,pins = <
577 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100f1
578 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100f1
579 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100f1
580 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100f1
581 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100f1
582 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100f1
583 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100f1
584 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100f1
585 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100f1
586 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100f1
587 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100f1
588 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100f1
589 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100f1
590 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100f1
591 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100f1
592 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100f1
593 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100f1
594 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100f1
595 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x100f1
596 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x100f1
597 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x100f1
598 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x100f1
599 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x100f1
600 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x100f1
601
602 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f1
603 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100f1 /* DE */
604 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100f1 /* HSYNC */
605 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100f1 /* VSYNC */
606 >;
607 };
608
609 pinctrl_lcdbklt_en: lcdbkltengrp {
610 fsl,pins = <
611 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b1
612 >;
613 };
614
615 pinctrl_lcdvdd_en: lcdvddengrp {
616 fsl,pins = <
617 MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
618 >;
619 };
620
621 pinctrl_mipi_csi: mipi-csigrp {
622 fsl,pins = <
623 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x000b0 /* CSI0/1 MCLK */
624 >;
625 };
626
627 pinctrl_mgmt_gpios: mgmt-gpiosgrp {
628 fsl,pins = <
629 MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b0 /* LID# */
630 MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x1b0b0 /* SLEEP# */
631 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 /* CHARGING# */
632 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* CHARGER_PRSNT# */
633 MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0 /* CARRIER_STBY# */
634 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 /* BATLOW# */
635 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0 /* TEST# */
636 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 /* VDD_IO_SEL_D# */
637 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 /* POWER_BTN# */
638 >;
639 };
640
641 pinctrl_pcie: pciegrp {
642 fsl,pins = <
643 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 /* PCI_A_PRSNT# */
644 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 /* RST_PCIE_A# */
645 MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 /* PCIE_WAKE# */
646 >;
647 };
648
649 pinctrl_pwm4: pwm4grp {
650 fsl,pins = <
651 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
652 >;
653 };
654
655 pinctrl_reg_sdio: reg-sdiogrp {
656 fsl,pins = <
657 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* SDIO_PWR_EN */
658 >;
659 };
660
661 pinctrl_uart1: uart1grp {
662 fsl,pins = <
663 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
664 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
665 MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1
666 MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1
667 >;
668 };
669
670 pinctrl_uart2: uart2grp {
671 fsl,pins = <
672 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
673 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
674 >;
675 };
676
677 pinctrl_uart4: uart4grp {
678 fsl,pins = <
679 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
680 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
681 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
682 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
683 >;
684 };
685
686 pinctrl_uart5: uart5grp {
687 fsl,pins = <
688 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
689 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
690 >;
691 };
692
693 pinctrl_usbotg: usbotggrp {
694 fsl,pins = <
695 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1f8b0
696 /* power, oc muxed but not used by the driver */
697 MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0 /* USB power */
698 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0 /* USB OC */
699 >;
700 };
701
702 pinctrl_usdhc3: usdhc3grp {
703 fsl,pins = <
704 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x17059
705 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
706 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
707 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
708 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
709 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
710
711 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */
712 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */
713 >;
714 };
715
716 pinctrl_usdhc4: usdhc4grp {
717 fsl,pins = <
718 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059
719 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
720 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
721 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
722 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
723 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
724 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
725 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
726 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
727 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
728 >;
729 };
730
731 pinctrl_wdog1: wdog1rp {
732 fsl,pins = <
733 MX6QDL_PAD_GPIO_9__WDOG1_B 0x1b0b0
734 >;
735 };
736 };
737
738 &mipi_csi {
739 pinctrl-names = "default";
740 pinctrl-0 = <&pinctrl_mipi_csi>;
741 };
742
743 &pcie {
744 pinctrl-names = "default";
745 pinctrl-0 = <&pinctrl_pcie>;
746 reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>;
747 };
748
749 /* LCD_BKLT_PWM */
750 &pwm4 {
751 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_pwm4>;
753 };
754
755 ®_arm {
756 vin-supply = <®_v_core_s0>;
757 };
758
759 ®_pu {
760 vin-supply = <®_vddsoc_s0>;
761 };
762
763 ®_soc {
764 vin-supply = <®_vddsoc_s0>;
765 };
766
767 /* SER0 */
768 &uart1 {
769 pinctrl-names = "default";
770 pinctrl-0 = <&pinctrl_uart1>;
771 uart-has-rtscts;
772 };
773
774 /* SER1 */
775 &uart2 {
776 pinctrl-names = "default";
777 pinctrl-0 = <&pinctrl_uart2>;
778 };
779
780 /* SER2 */
781 &uart4 {
782 pinctrl-names = "default";
783 pinctrl-0 = <&pinctrl_uart4>;
784 uart-has-rtscts;
785 };
786
787 /* SER3 */
788 &uart5 {
789 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_uart5>;
791 };
792
793 /* USB0 */
794 &usbotg {
795 /*
796 * no 'imx6-usb-charger-detection'
797 * since USB_OTG_CHD_B pin is not wired
798 */
799 pinctrl-names = "default";
800 pinctrl-0 = <&pinctrl_usbotg>;
801 };
802
803 /* USB1/2 via hub */
804 &usbh1 {
805 vbus-supply = <®_5p0v_s0>;
806 };
807
808 /* SDIO */
809 &usdhc3 {
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_usdhc3>;
812 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
813 wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
814 vmmc-supply = <®_sdio>;
815 no-1-8-v;
816 };
817
818 /* SDMMC */
819 &usdhc4 {
820 pinctrl-names = "default";
821 pinctrl-0 = <&pinctrl_usdhc4>;
822 bus-width = <8>;
823 no-sdio;
824 no-sd;
825 non-removable;
826 vmmc-supply = <®_3p3v_s0>;
827 vqmmc-supply = <®_1p8v_s0>;
828 status = "okay";
829 };
830
831 &wdog1 {
832 /* CPLD is feeded by watchdog (hardwired) */
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_wdog1>;
835 fsl,ext-reset-output;
836 status = "okay";
837 };
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