1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7
8 / {
9 aliases {
10 rtc0 = &i2c_rtc;
11 };
12
13 backlight: backlight {
14 compatible = "pwm-backlight";
15 brightness-levels = <0 4 8 16 32 64 128 255>;
16 default-brightness-level = <7>;
17 power-supply = <®_backlight>;
18 pwms = <&pwm1 0 5000000 0>;
19 status = "okay";
20 };
21
22 gpio_leds: leds {
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpioleds>;
26 status = "disabled";
27
28 led-red {
29 label = "phyboard-mira:red";
30 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
31 };
32
33 led-green {
34 label = "phyboard-mira:green";
35 gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
36 };
37
38 led-blue {
39 label = "phyboard-mira:blue";
40 gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
41 linux,default-trigger = "mmc0";
42 };
43 };
44
45 reg_backlight: regulator-backlight {
46 compatible = "regulator-fixed";
47 regulator-name = "backlight_3v3";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 regulator-always-on;
51 };
52
53 reg_en_switch: regulator-en-switch {
54 compatible = "regulator-fixed";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_en_switch>;
57 regulator-name = "Enable Switch";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 enable-active-high;
61 gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
62 regulator-always-on;
63 };
64
65 reg_flexcan1: regulator-flexcan1 {
66 compatible = "regulator-fixed";
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_flexcan1_en>;
69 regulator-name = "flexcan1-reg";
70 regulator-min-microvolt = <1500000>;
71 regulator-max-microvolt = <1500000>;
72 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
76 reg_panel: regulator-panel {
77 compatible = "regulator-fixed";
78 regulator-name = "panel-power-supply";
79 regulator-min-microvolt = <12000000>;
80 regulator-max-microvolt = <12000000>;
81 regulator-always-on;
82 };
83
84 reg_pcie: regulator-pcie {
85 compatible = "regulator-fixed";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_pcie_reg>;
88 regulator-name = "mPCIe_1V5";
89 regulator-min-microvolt = <1500000>;
90 regulator-max-microvolt = <1500000>;
91 gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94
95 reg_usb_h1_vbus: usb-h1-vbus {
96 compatible = "regulator-fixed";
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_usbh1_vbus>;
99 regulator-name = "usb_h1_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
103 enable-active-high;
104 };
105
106 reg_usbotg_vbus: usbotg-vbus {
107 compatible = "regulator-fixed";
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_usbotg_vbus>;
110 regulator-name = "usb_otg_vbus";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
114 enable-active-high;
115 };
116
117 panel {
118 compatible = "auo,g104sn02";
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_panel_en>;
121 power-supply = <®_panel>;
122 enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
123 backlight = <&backlight>;
124
125 port {
126 panel_in: endpoint {
127 remote-endpoint = <&lvds0_out>;
128 };
129 };
130 };
131 };
132
133 &can1 {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_flexcan1>;
136 xceiver-supply = <®_flexcan1>;
137 status = "disabled";
138 };
139
140 &hdmi {
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_hdmicec>;
143 ddc-i2c-bus = <&i2c2>;
144 status = "disabled";
145 };
146
147 &i2c1 {
148 pinctrl-names = "default", "gpio";
149 pinctrl-0 = <&pinctrl_i2c1>;
150 pinctrl-1 = <&pinctrl_i2c1_gpio>;
151 scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
152 sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
153 clock-frequency = <400000>;
154 status = "disabled";
155
156 stmpe: touchctrl@44 {
157 compatible = "st,stmpe811";
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_stmpe>;
160 reg = <0x44>;
161 interrupt-parent = <&gpio7>;
162 interrupts = <12 IRQ_TYPE_NONE>;
163 status = "disabled";
164
165 stmpe_touchscreen {
166 compatible = "st,stmpe-ts";
167 st,sample-time = <4>;
168 st,mod-12b = <1>;
169 st,ref-sel = <0>;
170 st,adc-freq = <1>;
171 st,ave-ctrl = <1>;
172 st,touch-det-delay = <2>;
173 st,settling = <2>;
174 st,fraction-z = <7>;
175 st,i-drive = <1>;
176 };
177 };
178
179 i2c_rtc: rtc@68 {
180 compatible = "microcrystal,rv4162";
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_rtc_int>;
183 reg = <0x68>;
184 interrupt-parent = <&gpio7>;
185 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
186 status = "disabled";
187 };
188 };
189
190 &i2c2 {
191 pinctrl-names = "default", "gpio";
192 pinctrl-0 = <&pinctrl_i2c2>;
193 pinctrl-1 = <&pinctrl_i2c2_gpio>;
194 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
195 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
196 clock-frequency = <100000>;
197 status = "disabled";
198 };
199
200 &ldb {
201 status = "okay";
202
203 lvds-channel@0 {
204 fsl,data-mapping = "spwg";
205 fsl,data-width = <24>;
206 status = "disabled";
207
208 port@4 {
209 reg = <4>;
210
211 lvds0_out: endpoint {
212 remote-endpoint = <&panel_in>;
213 };
214 };
215 };
216 };
217
218 &pcie {
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_pcie>;
221 reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
222 vpcie-supply = <®_pcie>;
223 status = "disabled";
224 };
225
226 &pwm1 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_pwm1>;
229 status = "okay";
230 };
231
232 &uart2 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_uart2>;
235 status = "okay";
236 };
237
238 &uart3 {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_uart3>;
241 uart-has-rtscts;
242 status = "disabled";
243 };
244
245 &usbh1 {
246 vbus-supply = <®_usb_h1_vbus>;
247 disable-over-current;
248 status = "disabled";
249 };
250
251 &usbotg {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_usbotg>;
254 vbus-supply = <®_usbotg_vbus>;
255 disable-over-current;
256 status = "disabled";
257 };
258
259 &usdhc1 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_usdhc1>;
262 cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
263 no-1-8-v;
264 disable-wp;
265 status = "disabled";
266 };
267
268 &iomuxc {
269 pinctrl_panel_en: panelen1grp {
270 fsl,pins = <
271 MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
272 >;
273 };
274
275 pinctrl_en_switch: enswitchgrp {
276 fsl,pins = <
277 MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1
278 >;
279 };
280
281 pinctrl_flexcan1: flexcan1grp {
282 fsl,pins = <
283 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
284 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
285 >;
286 };
287
288 pinctrl_flexcan1_en: flexcan1engrp {
289 fsl,pins = <
290 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1
291 >;
292 };
293
294 pinctrl_gpioleds: gpioledsgrp {
295 fsl,pins = <
296 MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
297 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
298 MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0
299 >;
300 };
301
302 pinctrl_hdmicec: hdmicecgrp {
303 fsl,pins = <
304 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
305 >;
306 };
307
308 pinctrl_i2c1: i2c1grp {
309 fsl,pins = <
310 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
311 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
312 >;
313 };
314
315 pinctrl_i2c1_gpio: i2c1gpiogrp {
316 fsl,pins = <
317 MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
318 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
319 >;
320 };
321
322 pinctrl_i2c2: i2c2grp {
323 fsl,pins = <
324 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
325 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
326 >;
327 };
328
329 pinctrl_i2c2_gpio: i2c2gpiogrp {
330 fsl,pins = <
331 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
332 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
333 >;
334 };
335
336 pinctrl_pcie: pciegrp {
337 fsl,pins = <
338 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1
339 >;
340 };
341
342 pinctrl_pcie_reg: pciereggrp {
343 fsl,pins = <
344 MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1
345 >;
346 };
347
348 pinctrl_pwm1: pwm1grp {
349 fsl,pins = <
350 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
351 >;
352 };
353
354 pinctrl_rtc_int: rtcintgrp {
355 fsl,pins = <
356 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
357 >;
358 };
359
360 pinctrl_stmpe: stmpegrp {
361 fsl,pins = <
362 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
363 >;
364 };
365
366 pinctrl_uart2: uart2grp {
367 fsl,pins = <
368 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
369 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
370 >;
371 };
372
373 pinctrl_uart3: uart3grp {
374 fsl,pins = <
375 MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
376 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
377 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
378 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
379 >;
380 };
381
382 pinctrl_usbh1_vbus: usbh1vbusgrp {
383 fsl,pins = <
384 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1
385 >;
386 };
387
388 pinctrl_usbotg: usbotggrp {
389 fsl,pins = <
390 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
391 >;
392 };
393
394 pinctrl_usbotg_vbus: usbotgvbusgrp {
395 fsl,pins = <
396 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1
397 >;
398 };
399
400 pinctrl_usdhc1: usdhc1grp {
401 fsl,pins = <
402 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
403 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
404 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
405 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
406 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
407 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
408 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */
409 >;
410 };
411 };
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