1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 * Dong Aisheng <aisheng.dong@nxp.com>
6 */
7
8 /dts-v1/;
9
10 #include "imx7ulp.dtsi"
11
12 / {
13 model = "NXP i.MX7ULP EVK";
14 compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
15
16 chosen {
17 stdout-path = &lpuart4;
18 };
19
20 memory@60000000 {
21 device_type = "memory";
22 reg = <0x60000000 0x40000000>;
23 };
24
25 backlight {
26 compatible = "pwm-backlight";
27 pwms = <&tpm4 1 50000 0>;
28 brightness-levels = <0 20 25 30 35 40 100>;
29 default-brightness-level = <6>;
30 status = "okay";
31 };
32
33 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
34 compatible = "regulator-fixed";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_usbotg1_vbus>;
37 regulator-name = "usb_otg1_vbus";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 reg_vsd_3v3: regulator-vsd-3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "VSD_3V3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_usdhc0_rst>;
51 gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 };
54 };
55
56 &lpuart4 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_lpuart4>;
59 status = "okay";
60 };
61
62 &tpm4 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pwm0>;
65 status = "okay";
66 };
67
68 &usbotg1 {
69 vbus-supply = <®_usb_otg1_vbus>;
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_usbotg1_id>;
72 srp-disable;
73 hnp-disable;
74 adp-disable;
75 disable-over-current;
76 status = "okay";
77 };
78
79 &usdhc0 {
80 assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
81 assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_usdhc0>;
84 cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
85 vmmc-supply = <®_vsd_3v3>;
86 status = "okay";
87 };
88
89 &iomuxc1 {
90 pinctrl_lpuart4: lpuart4grp {
91 fsl,pins = <
92 IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
93 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
94 >;
95 bias-pull-up;
96 };
97
98 pinctrl_pwm0: pwm0grp {
99 fsl,pins = <
100 IMX7ULP_PAD_PTF2__TPM4_CH1 0x2
101 >;
102 };
103
104 pinctrl_usbotg1_vbus: otg1vbusgrp {
105 fsl,pins = <
106 IMX7ULP_PAD_PTC0__PTC0 0x20000
107 >;
108 };
109
110 pinctrl_usbotg1_id: otg1idgrp {
111 fsl,pins = <
112 IMX7ULP_PAD_PTC13__USB0_ID 0x10003
113 >;
114 };
115
116 pinctrl_usdhc0: usdhc0grp {
117 fsl,pins = <
118 IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
119 IMX7ULP_PAD_PTD2__SDHC0_CLK 0x40
120 IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
121 IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
122 IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
123 IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
124 IMX7ULP_PAD_PTC10__PTC10 0x3 /* CD */
125 >;
126 };
127
128 pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
129 fsl,pins = <
130 IMX7ULP_PAD_PTD0__PTD0 0x3
131 >;
132 };
133 };
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