1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PHYTEC phyCORE-LPC3250 board
4 *
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
6 * Copyright 2012 Roland Stigge <stigge@antcom.de>
7 */
8
9 /dts-v1/;
10 #include "lpc32xx.dtsi"
11
12 / {
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
14 compatible = "phytec,phy3250", "nxp,lpc3250";
15
16 memory@80000000 {
17 device_type = "memory";
18 reg = <0x80000000 0x4000000>;
19 };
20
21 leds {
22 compatible = "gpio-leds";
23
24 led0 { /* red */
25 gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
26 default-state = "off";
27 };
28
29 led1 { /* green */
30 gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
31 linux,default-trigger = "heartbeat";
32 };
33 };
34
35 panel: panel {
36 compatible = "sharp,lq035q7db03";
37 power-supply = <®_lcd>;
38
39 port {
40 panel_input: endpoint {
41 remote-endpoint = <&cldc_output>;
42 };
43 };
44 };
45
46 reg_backlight: regulator-backlight {
47 compatible = "regulator-fixed";
48 regulator-name = "backlight";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 gpio = <&gpio 5 4 0>;
52 enable-active-high;
53 regulator-boot-on;
54 };
55
56 reg_lcd: regulator-lcd {
57 compatible = "regulator-fixed";
58 regulator-name = "lcd";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <1800000>;
61 gpio = <&gpio 5 0 0>;
62 enable-active-high;
63 regulator-boot-on;
64 };
65
66 reg_sd: regulator-sd {
67 compatible = "regulator-fixed";
68 regulator-name = "sd";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 gpio = <&gpio 5 5 0>;
72 enable-active-high;
73 regulator-boot-on;
74 };
75 };
76
77 &clcd {
78 max-memory-bandwidth = <18710000>;
79 status = "okay";
80
81 port {
82 cldc_output: endpoint {
83 remote-endpoint = <&panel_input>;
84 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
85 };
86 };
87 };
88
89 &i2c1 {
90 clock-frequency = <100000>;
91
92 uda1380: uda1380@18 {
93 compatible = "nxp,uda1380";
94 reg = <0x18>;
95 power-gpio = <&gpio 3 10 0>;
96 reset-gpio = <&gpio 3 2 0>;
97 dac-clk = "wspll";
98 };
99
100 pcf8563: rtc@51 {
101 compatible = "nxp,pcf8563";
102 reg = <0x51>;
103 };
104 };
105
106 &i2c2 {
107 clock-frequency = <100000>;
108 };
109
110 &i2cusb {
111 clock-frequency = <100000>;
112
113 isp1301: usb-transceiver@2c {
114 compatible = "nxp,isp1301";
115 reg = <0x2c>;
116 };
117 };
118
119 &key {
120 keypad,num-rows = <1>;
121 keypad,num-columns = <1>;
122 nxp,debounce-delay-ms = <3>;
123 nxp,scan-delay-ms = <34>;
124 linux,keymap = <0x00000002>;
125 status = "okay";
126 };
127
128 &mac {
129 phy-mode = "rmii";
130 use-iram;
131 status = "okay";
132 };
133
134 /* Here, choose exactly one from: ohci, usbd */
135 &ohci /* &usbd */ {
136 transceiver = <&isp1301>;
137 status = "okay";
138 };
139
140 &sd {
141 wp-gpios = <&gpio 3 0 0>;
142 cd-gpios = <&gpio 3 1 0>;
143 cd-inverted;
144 bus-width = <4>;
145 vmmc-supply = <®_sd>;
146 status = "okay";
147 };
148
149 /* 64MB Flash via SLC NAND controller */
150 &slc {
151 status = "okay";
152
153 nxp,wdr-clks = <14>;
154 nxp,wwidth = <40000000>;
155 nxp,whold = <100000000>;
156 nxp,wsetup = <100000000>;
157 nxp,rdr-clks = <14>;
158 nxp,rwidth = <40000000>;
159 nxp,rhold = <66666666>;
160 nxp,rsetup = <100000000>;
161 nand-on-flash-bbt;
162 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
163
164 partitions {
165 compatible = "fixed-partitions";
166 #address-cells = <1>;
167 #size-cells = <1>;
168
169 mtd0@0 {
170 label = "phy3250-boot";
171 reg = <0x00000000 0x00064000>;
172 read-only;
173 };
174
175 mtd1@64000 {
176 label = "phy3250-uboot";
177 reg = <0x00064000 0x00190000>;
178 read-only;
179 };
180
181 mtd2@1f4000 {
182 label = "phy3250-ubt-prms";
183 reg = <0x001f4000 0x00010000>;
184 };
185
186 mtd3@204000 {
187 label = "phy3250-kernel";
188 reg = <0x00204000 0x00400000>;
189 };
190
191 mtd4@604000 {
192 label = "phy3250-rootfs";
193 reg = <0x00604000 0x039fc000>;
194 };
195 };
196 };
197
198 &ssp0 {
199 num-cs = <1>;
200 cs-gpios = <&gpio 3 5 0>;
201 status = "okay";
202
203 eeprom: at25@0 {
204 compatible = "atmel,at25";
205 reg = <0>;
206 spi-max-frequency = <5000000>;
207
208 pl022,interface = <0>;
209 pl022,com-mode = <0>;
210 pl022,rx-level-trig = <1>;
211 pl022,tx-level-trig = <1>;
212 pl022,ctrl-len = <11>;
213 pl022,wait-state = <0>;
214 pl022,duplex = <0>;
215
216 at25,byte-len = <0x8000>;
217 at25,addr-mode = <2>;
218 at25,page-size = <64>;
219 };
220 };
221
222 &tsc {
223 status = "okay";
224 };
225
226 &uart2 {
227 status = "okay";
228 };
229
230 &uart3 {
231 status = "okay";
232 };
233
234 &uart5 {
235 status = "okay";
236 };
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