1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Qualcomm IPQ8064";
18 compatible = "qcom,ipq8064";
19 interrupt-parent = <&intc>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 compatible = "qcom,krait";
27 enable-method = "qcom,kpss-acc-v1";
28 device_type = "cpu";
29 reg = <0>;
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc0>;
32 qcom,saw = <&saw0>;
33 };
34
35 cpu1: cpu@1 {
36 compatible = "qcom,krait";
37 enable-method = "qcom,kpss-acc-v1";
38 device_type = "cpu";
39 reg = <1>;
40 next-level-cache = <&L2>;
41 qcom,acc = <&acc1>;
42 qcom,saw = <&saw1>;
43 };
44
45 L2: l2-cache {
46 compatible = "cache";
47 cache-level = <2>;
48 cache-unified;
49 };
50 };
51
52 thermal-zones {
53 sensor0-thermal {
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
57
58 trips {
59 cpu-critical {
60 temperature = <105000>;
61 hysteresis = <2000>;
62 type = "critical";
63 };
64
65 cpu-hot {
66 temperature = <95000>;
67 hysteresis = <2000>;
68 type = "hot";
69 };
70 };
71 };
72
73 sensor1-thermal {
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
76 thermal-sensors = <&tsens 1>;
77
78 trips {
79 cpu-critical {
80 temperature = <105000>;
81 hysteresis = <2000>;
82 type = "critical";
83 };
84
85 cpu-hot {
86 temperature = <95000>;
87 hysteresis = <2000>;
88 type = "hot";
89 };
90 };
91 };
92
93 sensor2-thermal {
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
96 thermal-sensors = <&tsens 2>;
97
98 trips {
99 cpu-critical {
100 temperature = <105000>;
101 hysteresis = <2000>;
102 type = "critical";
103 };
104
105 cpu-hot {
106 temperature = <95000>;
107 hysteresis = <2000>;
108 type = "hot";
109 };
110 };
111 };
112
113 sensor3-thermal {
114 polling-delay-passive = <0>;
115 polling-delay = <0>;
116 thermal-sensors = <&tsens 3>;
117
118 trips {
119 cpu-critical {
120 temperature = <105000>;
121 hysteresis = <2000>;
122 type = "critical";
123 };
124
125 cpu-hot {
126 temperature = <95000>;
127 hysteresis = <2000>;
128 type = "hot";
129 };
130 };
131 };
132
133 sensor4-thermal {
134 polling-delay-passive = <0>;
135 polling-delay = <0>;
136 thermal-sensors = <&tsens 4>;
137
138 trips {
139 cpu-critical {
140 temperature = <105000>;
141 hysteresis = <2000>;
142 type = "critical";
143 };
144
145 cpu-hot {
146 temperature = <95000>;
147 hysteresis = <2000>;
148 type = "hot";
149 };
150 };
151 };
152
153 sensor5-thermal {
154 polling-delay-passive = <0>;
155 polling-delay = <0>;
156 thermal-sensors = <&tsens 5>;
157
158 trips {
159 cpu-critical {
160 temperature = <105000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164
165 cpu-hot {
166 temperature = <95000>;
167 hysteresis = <2000>;
168 type = "hot";
169 };
170 };
171 };
172
173 sensor6-thermal {
174 polling-delay-passive = <0>;
175 polling-delay = <0>;
176 thermal-sensors = <&tsens 6>;
177
178 trips {
179 cpu-critical {
180 temperature = <105000>;
181 hysteresis = <2000>;
182 type = "critical";
183 };
184
185 cpu-hot {
186 temperature = <95000>;
187 hysteresis = <2000>;
188 type = "hot";
189 };
190 };
191 };
192
193 sensor7-thermal {
194 polling-delay-passive = <0>;
195 polling-delay = <0>;
196 thermal-sensors = <&tsens 7>;
197
198 trips {
199 cpu-critical {
200 temperature = <105000>;
201 hysteresis = <2000>;
202 type = "critical";
203 };
204
205 cpu-hot {
206 temperature = <95000>;
207 hysteresis = <2000>;
208 type = "hot";
209 };
210 };
211 };
212
213 sensor8-thermal {
214 polling-delay-passive = <0>;
215 polling-delay = <0>;
216 thermal-sensors = <&tsens 8>;
217
218 trips {
219 cpu-critical {
220 temperature = <105000>;
221 hysteresis = <2000>;
222 type = "critical";
223 };
224
225 cpu-hot {
226 temperature = <95000>;
227 hysteresis = <2000>;
228 type = "hot";
229 };
230 };
231 };
232
233 sensor9-thermal {
234 polling-delay-passive = <0>;
235 polling-delay = <0>;
236 thermal-sensors = <&tsens 9>;
237
238 trips {
239 cpu-critical {
240 temperature = <105000>;
241 hysteresis = <2000>;
242 type = "critical";
243 };
244
245 cpu-hot {
246 temperature = <95000>;
247 hysteresis = <2000>;
248 type = "hot";
249 };
250 };
251 };
252
253 sensor10-thermal {
254 polling-delay-passive = <0>;
255 polling-delay = <0>;
256 thermal-sensors = <&tsens 10>;
257
258 trips {
259 cpu-critical {
260 temperature = <105000>;
261 hysteresis = <2000>;
262 type = "critical";
263 };
264
265 cpu-hot {
266 temperature = <95000>;
267 hysteresis = <2000>;
268 type = "hot";
269 };
270 };
271 };
272 };
273
274 memory {
275 device_type = "memory";
276 reg = <0x0 0x0>;
277 };
278
279 cpu-pmu {
280 compatible = "qcom,krait-pmu";
281 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
282 IRQ_TYPE_LEVEL_HIGH)>;
283 };
284
285 reserved-memory {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289
290 nss@40000000 {
291 reg = <0x40000000 0x1000000>;
292 no-map;
293 };
294
295 smem: smem@41000000 {
296 compatible = "qcom,smem";
297 reg = <0x41000000 0x200000>;
298 no-map;
299
300 hwlocks = <&sfpb_mutex 3>;
301 };
302 };
303
304 clocks {
305 cxo_board: cxo_board {
306 compatible = "fixed-clock";
307 #clock-cells = <0>;
308 clock-frequency = <25000000>;
309 };
310
311 pxo_board: pxo_board {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <25000000>;
315 };
316
317 sleep_clk: sleep_clk {
318 compatible = "fixed-clock";
319 clock-frequency = <32768>;
320 #clock-cells = <0>;
321 };
322 };
323
324 firmware {
325 scm {
326 compatible = "qcom,scm-ipq806x", "qcom,scm";
327 };
328 };
329
330 stmmac_axi_setup: stmmac-axi-config {
331 snps,wr_osr_lmt = <7>;
332 snps,rd_osr_lmt = <7>;
333 snps,blen = <16 0 0 0 0 0 0>;
334 };
335
336 vsdcc_fixed: vsdcc-regulator {
337 compatible = "regulator-fixed";
338 regulator-name = "SDCC Power";
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
341 regulator-always-on;
342 };
343
344 soc: soc {
345 #address-cells = <1>;
346 #size-cells = <1>;
347 ranges;
348 compatible = "simple-bus";
349
350 rpm: rpm@108000 {
351 compatible = "qcom,rpm-ipq8064";
352 reg = <0x00108000 0x1000>;
353 qcom,ipc = <&l2cc 0x8 2>;
354
355 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-names = "ack", "err", "wakeup";
359
360 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
361 clock-names = "ram";
362
363 rpmcc: clock-controller {
364 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
365 #clock-cells = <1>;
366 };
367 };
368
369 ssbi@500000 {
370 compatible = "qcom,ssbi";
371 reg = <0x00500000 0x1000>;
372 qcom,controller-type = "pmic-arbiter";
373 };
374
375 qfprom: efuse@700000 {
376 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
377 reg = <0x00700000 0x1000>;
378 #address-cells = <1>;
379 #size-cells = <1>;
380 speedbin_efuse: speedbin@c0 {
381 reg = <0xc0 0x4>;
382 };
383 tsens_calib: calib@400 {
384 reg = <0x400 0xb>;
385 };
386 tsens_calib_backup: calib_backup@410 {
387 reg = <0x410 0xb>;
388 };
389 };
390
391 qcom_pinmux: pinmux@800000 {
392 compatible = "qcom,ipq8064-pinctrl";
393 reg = <0x00800000 0x4000>;
394
395 gpio-controller;
396 gpio-ranges = <&qcom_pinmux 0 0 69>;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
401
402 pcie0_pins: pcie0_pinmux {
403 mux {
404 pins = "gpio3";
405 function = "pcie1_rst";
406 drive-strength = <12>;
407 bias-disable;
408 };
409 };
410
411 pcie1_pins: pcie1_pinmux {
412 mux {
413 pins = "gpio48";
414 function = "pcie2_rst";
415 drive-strength = <12>;
416 bias-disable;
417 };
418 };
419
420 pcie2_pins: pcie2_pinmux {
421 mux {
422 pins = "gpio63";
423 function = "pcie3_rst";
424 drive-strength = <12>;
425 bias-disable;
426 };
427 };
428
429 i2c4_pins: i2c4-default {
430 pins = "gpio12", "gpio13";
431 function = "gsbi4";
432 drive-strength = <12>;
433 bias-disable;
434 };
435
436 spi_pins: spi_pins {
437 mux {
438 pins = "gpio18", "gpio19", "gpio21";
439 function = "gsbi5";
440 drive-strength = <10>;
441 bias-none;
442 };
443 };
444
445 leds_pins: leds_pins {
446 mux {
447 pins = "gpio7", "gpio8", "gpio9",
448 "gpio26", "gpio53";
449 function = "gpio";
450 drive-strength = <2>;
451 bias-pull-down;
452 output-low;
453 };
454 };
455
456 buttons_pins: buttons_pins {
457 mux {
458 pins = "gpio54";
459 drive-strength = <2>;
460 bias-pull-up;
461 };
462 };
463
464 nand_pins: nand_pins {
465 mux {
466 pins = "gpio34", "gpio35", "gpio36",
467 "gpio37", "gpio38", "gpio39",
468 "gpio40", "gpio41", "gpio42",
469 "gpio43", "gpio44", "gpio45",
470 "gpio46", "gpio47";
471 function = "nand";
472 drive-strength = <10>;
473 bias-disable;
474 };
475
476 pullups {
477 pins = "gpio39";
478 function = "nand";
479 drive-strength = <10>;
480 bias-pull-up;
481 };
482
483 hold {
484 pins = "gpio40", "gpio41", "gpio42",
485 "gpio43", "gpio44", "gpio45",
486 "gpio46", "gpio47";
487 function = "nand";
488 drive-strength = <10>;
489 bias-bus-hold;
490 };
491 };
492
493 mdio0_pins: mdio0-pins {
494 mux {
495 pins = "gpio0", "gpio1";
496 function = "mdio";
497 drive-strength = <8>;
498 bias-disable;
499 };
500 };
501
502 rgmii2_pins: rgmii2-pins {
503 mux {
504 pins = "gpio27", "gpio28", "gpio29",
505 "gpio30", "gpio31", "gpio32",
506 "gpio51", "gpio52", "gpio59",
507 "gpio60", "gpio61", "gpio62";
508 function = "rgmii2";
509 drive-strength = <8>;
510 bias-disable;
511 };
512 };
513 };
514
515 gcc: clock-controller@900000 {
516 compatible = "qcom,gcc-ipq8064", "syscon";
517 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
518 clock-names = "pxo", "cxo", "pll4";
519 reg = <0x00900000 0x4000>;
520 #clock-cells = <1>;
521 #reset-cells = <1>;
522
523 tsens: thermal-sensor {
524 compatible = "qcom,ipq8064-tsens";
525
526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
527 nvmem-cell-names = "calib", "calib_backup";
528 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
529 interrupt-names = "uplow";
530
531 #qcom,sensors = <11>;
532 #thermal-sensor-cells = <1>;
533 };
534 };
535
536 sfpb_mutex: hwlock@1200600 {
537 compatible = "qcom,sfpb-mutex";
538 reg = <0x01200600 0x100>;
539
540 #hwlock-cells = <1>;
541 };
542
543 intc: interrupt-controller@2000000 {
544 compatible = "qcom,msm-qgic2";
545 interrupt-controller;
546 #interrupt-cells = <3>;
547 reg = <0x02000000 0x1000>,
548 <0x02002000 0x1000>;
549 };
550
551 timer@200a000 {
552 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer",
553 "qcom,msm-timer";
554 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
555 IRQ_TYPE_EDGE_RISING)>,
556 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
557 IRQ_TYPE_EDGE_RISING)>,
558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
559 IRQ_TYPE_EDGE_RISING)>,
560 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
561 IRQ_TYPE_EDGE_RISING)>,
562 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
563 IRQ_TYPE_EDGE_RISING)>;
564 reg = <0x0200a000 0x100>;
565 clock-frequency = <25000000>;
566 clocks = <&sleep_clk>;
567 clock-names = "sleep";
568 cpu-offset = <0x80000>;
569 };
570
571 l2cc: clock-controller@2011000 {
572 compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
573 reg = <0x02011000 0x1000>;
574 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
575 clock-names = "pll8_vote", "pxo";
576 #clock-cells = <0>;
577 };
578
579 acc0: clock-controller@2088000 {
580 compatible = "qcom,kpss-acc-v1";
581 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
582 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
583 clock-names = "pll8_vote", "pxo";
584 clock-output-names = "acpu0_aux";
585 #clock-cells = <0>;
586 };
587
588 saw0: power-manager@2089000 {
589 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
590 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
591 };
592
593 acc1: clock-controller@2098000 {
594 compatible = "qcom,kpss-acc-v1";
595 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
596 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
597 clock-names = "pll8_vote", "pxo";
598 clock-output-names = "acpu1_aux";
599 #clock-cells = <0>;
600 };
601
602 saw1: power-manager@2099000 {
603 compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
604 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
605 };
606
607 nss_common: syscon@3000000 {
608 compatible = "syscon";
609 reg = <0x03000000 0x0000FFFF>;
610 };
611
612 usb3_0: usb@100f8800 {
613 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
614 #address-cells = <1>;
615 #size-cells = <1>;
616 reg = <0x100f8800 0x8000>;
617 clocks = <&gcc USB30_0_MASTER_CLK>;
618 clock-names = "core";
619
620 ranges;
621
622 resets = <&gcc USB30_0_MASTER_RESET>;
623
624 status = "disabled";
625
626 dwc3_0: usb@10000000 {
627 compatible = "snps,dwc3";
628 reg = <0x10000000 0xcd00>;
629 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
630 phys = <&hs_phy_0>, <&ss_phy_0>;
631 phy-names = "usb2-phy", "usb3-phy";
632 dr_mode = "host";
633 snps,dis_u3_susphy_quirk;
634 };
635 };
636
637 hs_phy_0: phy@100f8800 {
638 compatible = "qcom,ipq806x-usb-phy-hs";
639 reg = <0x100f8800 0x30>;
640 clocks = <&gcc USB30_0_UTMI_CLK>;
641 clock-names = "ref";
642 #phy-cells = <0>;
643
644 status = "disabled";
645 };
646
647 ss_phy_0: phy@100f8830 {
648 compatible = "qcom,ipq806x-usb-phy-ss";
649 reg = <0x100f8830 0x30>;
650 clocks = <&gcc USB30_0_MASTER_CLK>;
651 clock-names = "ref";
652 #phy-cells = <0>;
653
654 status = "disabled";
655 };
656
657 usb3_1: usb@110f8800 {
658 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
659 #address-cells = <1>;
660 #size-cells = <1>;
661 reg = <0x110f8800 0x8000>;
662 clocks = <&gcc USB30_1_MASTER_CLK>;
663 clock-names = "core";
664
665 ranges;
666
667 resets = <&gcc USB30_1_MASTER_RESET>;
668
669 status = "disabled";
670
671 dwc3_1: usb@11000000 {
672 compatible = "snps,dwc3";
673 reg = <0x11000000 0xcd00>;
674 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
675 phys = <&hs_phy_1>, <&ss_phy_1>;
676 phy-names = "usb2-phy", "usb3-phy";
677 dr_mode = "host";
678 snps,dis_u3_susphy_quirk;
679 };
680 };
681
682 hs_phy_1: phy@110f8800 {
683 compatible = "qcom,ipq806x-usb-phy-hs";
684 reg = <0x110f8800 0x30>;
685 clocks = <&gcc USB30_1_UTMI_CLK>;
686 clock-names = "ref";
687 #phy-cells = <0>;
688
689 status = "disabled";
690 };
691
692 ss_phy_1: phy@110f8830 {
693 compatible = "qcom,ipq806x-usb-phy-ss";
694 reg = <0x110f8830 0x30>;
695 clocks = <&gcc USB30_1_MASTER_CLK>;
696 clock-names = "ref";
697 #phy-cells = <0>;
698
699 status = "disabled";
700 };
701
702 sdcc3bam: dma-controller@12182000 {
703 compatible = "qcom,bam-v1.3.0";
704 reg = <0x12182000 0x8000>;
705 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&gcc SDC3_H_CLK>;
707 clock-names = "bam_clk";
708 #dma-cells = <1>;
709 qcom,ee = <0>;
710 };
711
712 sdcc1bam: dma-controller@12402000 {
713 compatible = "qcom,bam-v1.3.0";
714 reg = <0x12402000 0x8000>;
715 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&gcc SDC1_H_CLK>;
717 clock-names = "bam_clk";
718 #dma-cells = <1>;
719 qcom,ee = <0>;
720 };
721
722 amba: amba {
723 compatible = "simple-bus";
724 #address-cells = <1>;
725 #size-cells = <1>;
726 ranges;
727
728 sdcc3: mmc@12180000 {
729 compatible = "arm,pl18x", "arm,primecell";
730 arm,primecell-periphid = <0x00051180>;
731 status = "disabled";
732 reg = <0x12180000 0x2000>;
733 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
735 clock-names = "mclk", "apb_pclk";
736 bus-width = <8>;
737 cap-sd-highspeed;
738 cap-mmc-highspeed;
739 max-frequency = <192000000>;
740 sd-uhs-sdr104;
741 sd-uhs-ddr50;
742 vqmmc-supply = <&vsdcc_fixed>;
743 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
744 dma-names = "tx", "rx";
745 };
746
747 sdcc1: mmc@12400000 {
748 status = "disabled";
749 compatible = "arm,pl18x", "arm,primecell";
750 arm,primecell-periphid = <0x00051180>;
751 reg = <0x12400000 0x2000>;
752 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
754 clock-names = "mclk", "apb_pclk";
755 bus-width = <8>;
756 max-frequency = <96000000>;
757 non-removable;
758 cap-sd-highspeed;
759 cap-mmc-highspeed;
760 vmmc-supply = <&vsdcc_fixed>;
761 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
762 dma-names = "tx", "rx";
763 };
764 };
765
766 gsbi1: gsbi@12440000 {
767 compatible = "qcom,gsbi-v1.0.0";
768 reg = <0x12440000 0x100>;
769 cell-index = <1>;
770 clocks = <&gcc GSBI1_H_CLK>;
771 clock-names = "iface";
772 #address-cells = <1>;
773 #size-cells = <1>;
774 ranges;
775
776 syscon-tcsr = <&tcsr>;
777
778 status = "disabled";
779
780 gsbi1_serial: serial@12450000 {
781 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
782 reg = <0x12450000 0x100>,
783 <0x12400000 0x03>;
784 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
786 clock-names = "core", "iface";
787
788 status = "disabled";
789 };
790
791 gsbi1_i2c: i2c@12460000 {
792 compatible = "qcom,i2c-qup-v1.1.1";
793 reg = <0x12460000 0x1000>;
794 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
796 clock-names = "core", "iface";
797 #address-cells = <1>;
798 #size-cells = <0>;
799
800 status = "disabled";
801 };
802 };
803
804 gsbi2: gsbi@12480000 {
805 compatible = "qcom,gsbi-v1.0.0";
806 cell-index = <2>;
807 reg = <0x12480000 0x100>;
808 clocks = <&gcc GSBI2_H_CLK>;
809 clock-names = "iface";
810 #address-cells = <1>;
811 #size-cells = <1>;
812 ranges;
813 status = "disabled";
814
815 syscon-tcsr = <&tcsr>;
816
817 gsbi2_serial: serial@12490000 {
818 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
819 reg = <0x12490000 0x1000>,
820 <0x12480000 0x1000>;
821 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
823 clock-names = "core", "iface";
824 status = "disabled";
825 };
826
827 gsbi2_i2c: i2c@124a0000 {
828 compatible = "qcom,i2c-qup-v1.1.1";
829 reg = <0x124a0000 0x1000>;
830 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
831
832 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
833 clock-names = "core", "iface";
834 status = "disabled";
835
836 #address-cells = <1>;
837 #size-cells = <0>;
838 };
839 };
840
841 gsbi4: gsbi@16300000 {
842 compatible = "qcom,gsbi-v1.0.0";
843 cell-index = <4>;
844 reg = <0x16300000 0x100>;
845 clocks = <&gcc GSBI4_H_CLK>;
846 clock-names = "iface";
847 #address-cells = <1>;
848 #size-cells = <1>;
849 ranges;
850 status = "disabled";
851
852 syscon-tcsr = <&tcsr>;
853
854 gsbi4_serial: serial@16340000 {
855 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
856 reg = <0x16340000 0x1000>,
857 <0x16300000 0x1000>;
858 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
860 clock-names = "core", "iface";
861 status = "disabled";
862 };
863
864 i2c@16380000 {
865 compatible = "qcom,i2c-qup-v1.1.1";
866 reg = <0x16380000 0x1000>;
867 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
868
869 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
870 clock-names = "core", "iface";
871 status = "disabled";
872
873 #address-cells = <1>;
874 #size-cells = <0>;
875 };
876 };
877
878 gsbi6: gsbi@16500000 {
879 compatible = "qcom,gsbi-v1.0.0";
880 reg = <0x16500000 0x100>;
881 cell-index = <6>;
882 clocks = <&gcc GSBI6_H_CLK>;
883 clock-names = "iface";
884 #address-cells = <1>;
885 #size-cells = <1>;
886 ranges;
887
888 syscon-tcsr = <&tcsr>;
889
890 status = "disabled";
891
892 gsbi6_i2c: i2c@16580000 {
893 compatible = "qcom,i2c-qup-v1.1.1";
894 reg = <0x16580000 0x1000>;
895 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
896
897 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
898 clock-names = "core", "iface";
899
900 #address-cells = <1>;
901 #size-cells = <0>;
902
903 status = "disabled";
904 };
905
906 gsbi6_spi: spi@16580000 {
907 compatible = "qcom,spi-qup-v1.1.1";
908 reg = <0x16580000 0x1000>;
909 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
910
911 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
912 clock-names = "core", "iface";
913
914 #address-cells = <1>;
915 #size-cells = <0>;
916
917 status = "disabled";
918 };
919 };
920
921 gsbi7: gsbi@16600000 {
922 status = "disabled";
923 compatible = "qcom,gsbi-v1.0.0";
924 cell-index = <7>;
925 reg = <0x16600000 0x100>;
926 clocks = <&gcc GSBI7_H_CLK>;
927 clock-names = "iface";
928 #address-cells = <1>;
929 #size-cells = <1>;
930 ranges;
931 syscon-tcsr = <&tcsr>;
932
933 gsbi7_serial: serial@16640000 {
934 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
935 reg = <0x16640000 0x1000>,
936 <0x16600000 0x1000>;
937 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
939 clock-names = "core", "iface";
940 status = "disabled";
941 };
942
943 gsbi7_i2c: i2c@16680000 {
944 compatible = "qcom,i2c-qup-v1.1.1";
945 reg = <0x16680000 0x1000>;
946 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
947
948 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
949 clock-names = "core", "iface";
950
951 #address-cells = <1>;
952 #size-cells = <0>;
953
954 status = "disabled";
955 };
956 };
957
958 adm_dma: dma-controller@18300000 {
959 compatible = "qcom,adm";
960 reg = <0x18300000 0x100000>;
961 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
962 #dma-cells = <1>;
963
964 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
965 clock-names = "core", "iface";
966
967 resets = <&gcc ADM0_RESET>,
968 <&gcc ADM0_PBUS_RESET>,
969 <&gcc ADM0_C0_RESET>,
970 <&gcc ADM0_C1_RESET>,
971 <&gcc ADM0_C2_RESET>;
972 reset-names = "clk", "pbus", "c0", "c1", "c2";
973 qcom,ee = <0>;
974
975 status = "disabled";
976 };
977
978 gsbi5: gsbi@1a200000 {
979 compatible = "qcom,gsbi-v1.0.0";
980 cell-index = <5>;
981 reg = <0x1a200000 0x100>;
982 clocks = <&gcc GSBI5_H_CLK>;
983 clock-names = "iface";
984 #address-cells = <1>;
985
986 #size-cells = <1>;
987 ranges;
988 status = "disabled";
989
990 syscon-tcsr = <&tcsr>;
991
992 gsbi5_serial: serial@1a240000 {
993 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
994 reg = <0x1a240000 0x1000>,
995 <0x1a200000 0x1000>;
996 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
998 clock-names = "core", "iface";
999 status = "disabled";
1000 };
1001
1002 i2c@1a280000 {
1003 compatible = "qcom,i2c-qup-v1.1.1";
1004 reg = <0x1a280000 0x1000>;
1005 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1006
1007 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1008 clock-names = "core", "iface";
1009 status = "disabled";
1010
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 };
1014
1015 spi@1a280000 {
1016 compatible = "qcom,spi-qup-v1.1.1";
1017 reg = <0x1a280000 0x1000>;
1018 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1019
1020 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1021 clock-names = "core", "iface";
1022 status = "disabled";
1023
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1026 };
1027 };
1028
1029 tcsr: syscon@1a400000 {
1030 compatible = "qcom,tcsr-ipq8064", "syscon";
1031 reg = <0x1a400000 0x100>;
1032 };
1033
1034 rng@1a500000 {
1035 compatible = "qcom,prng";
1036 reg = <0x1a500000 0x200>;
1037 clocks = <&gcc PRNG_CLK>;
1038 clock-names = "core";
1039 };
1040
1041 nand: nand-controller@1ac00000 {
1042 compatible = "qcom,ipq806x-nand";
1043 reg = <0x1ac00000 0x800>;
1044
1045 pinctrl-0 = <&nand_pins>;
1046 pinctrl-names = "default";
1047
1048 clocks = <&gcc EBI2_CLK>,
1049 <&gcc EBI2_AON_CLK>;
1050 clock-names = "core", "aon";
1051
1052 dmas = <&adm_dma 3>;
1053 dma-names = "rxtx";
1054 qcom,cmd-crci = <15>;
1055 qcom,data-crci = <3>;
1056
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1059
1060 status = "disabled";
1061 };
1062
1063 sata_phy: sata-phy@1b400000 {
1064 compatible = "qcom,ipq806x-sata-phy";
1065 reg = <0x1b400000 0x200>;
1066
1067 clocks = <&gcc SATA_PHY_CFG_CLK>;
1068 clock-names = "cfg";
1069
1070 #phy-cells = <0>;
1071 status = "disabled";
1072 };
1073
1074 pcie0: pcie@1b500000 {
1075 compatible = "qcom,pcie-ipq8064";
1076 reg = <0x1b500000 0x1000
1077 0x1b502000 0x80
1078 0x1b600000 0x100
1079 0x0ff00000 0x100000>;
1080 reg-names = "dbi", "elbi", "parf", "config";
1081 device_type = "pci";
1082 linux,pci-domain = <0>;
1083 bus-range = <0x00 0xff>;
1084 num-lanes = <1>;
1085 #address-cells = <3>;
1086 #size-cells = <2>;
1087
1088 ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */
1089 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */
1090
1091 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "msi";
1093 #interrupt-cells = <1>;
1094 interrupt-map-mask = <0 0 0 0x7>;
1095 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1096 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1097 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1098 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1099
1100 clocks = <&gcc PCIE_A_CLK>,
1101 <&gcc PCIE_H_CLK>,
1102 <&gcc PCIE_PHY_CLK>,
1103 <&gcc PCIE_AUX_CLK>,
1104 <&gcc PCIE_ALT_REF_CLK>;
1105 clock-names = "core", "iface", "phy", "aux", "ref";
1106
1107 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1108 assigned-clock-rates = <100000000>;
1109
1110 resets = <&gcc PCIE_ACLK_RESET>,
1111 <&gcc PCIE_HCLK_RESET>,
1112 <&gcc PCIE_POR_RESET>,
1113 <&gcc PCIE_PCI_RESET>,
1114 <&gcc PCIE_PHY_RESET>,
1115 <&gcc PCIE_EXT_RESET>;
1116 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1117
1118 pinctrl-0 = <&pcie0_pins>;
1119 pinctrl-names = "default";
1120
1121 status = "disabled";
1122 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1123
1124 pcie@0 {
1125 device_type = "pci";
1126 reg = <0x0 0x0 0x0 0x0 0x0>;
1127 bus-range = <0x01 0xff>;
1128
1129 #address-cells = <3>;
1130 #size-cells = <2>;
1131 ranges;
1132 };
1133 };
1134
1135 pcie1: pcie@1b700000 {
1136 compatible = "qcom,pcie-ipq8064";
1137 reg = <0x1b700000 0x1000
1138 0x1b702000 0x80
1139 0x1b800000 0x100
1140 0x31f00000 0x100000>;
1141 reg-names = "dbi", "elbi", "parf", "config";
1142 device_type = "pci";
1143 linux,pci-domain = <1>;
1144 bus-range = <0x00 0xff>;
1145 num-lanes = <1>;
1146 #address-cells = <3>;
1147 #size-cells = <2>;
1148
1149 ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */
1150 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */
1151
1152 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1153 interrupt-names = "msi";
1154 #interrupt-cells = <1>;
1155 interrupt-map-mask = <0 0 0 0x7>;
1156 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1157 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1158 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1159 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1160
1161 clocks = <&gcc PCIE_1_A_CLK>,
1162 <&gcc PCIE_1_H_CLK>,
1163 <&gcc PCIE_1_PHY_CLK>,
1164 <&gcc PCIE_1_AUX_CLK>,
1165 <&gcc PCIE_1_ALT_REF_CLK>;
1166 clock-names = "core", "iface", "phy", "aux", "ref";
1167
1168 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1169 assigned-clock-rates = <100000000>;
1170
1171 resets = <&gcc PCIE_1_ACLK_RESET>,
1172 <&gcc PCIE_1_HCLK_RESET>,
1173 <&gcc PCIE_1_POR_RESET>,
1174 <&gcc PCIE_1_PCI_RESET>,
1175 <&gcc PCIE_1_PHY_RESET>,
1176 <&gcc PCIE_1_EXT_RESET>;
1177 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1178
1179 pinctrl-0 = <&pcie1_pins>;
1180 pinctrl-names = "default";
1181
1182 status = "disabled";
1183 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1184
1185 pcie@0 {
1186 device_type = "pci";
1187 reg = <0x0 0x0 0x0 0x0 0x0>;
1188 bus-range = <0x01 0xff>;
1189
1190 #address-cells = <3>;
1191 #size-cells = <2>;
1192 ranges;
1193 };
1194 };
1195
1196 pcie2: pcie@1b900000 {
1197 compatible = "qcom,pcie-ipq8064";
1198 reg = <0x1b900000 0x1000
1199 0x1b902000 0x80
1200 0x1ba00000 0x100
1201 0x35f00000 0x100000>;
1202 reg-names = "dbi", "elbi", "parf", "config";
1203 device_type = "pci";
1204 linux,pci-domain = <2>;
1205 bus-range = <0x00 0xff>;
1206 num-lanes = <1>;
1207 #address-cells = <3>;
1208 #size-cells = <2>;
1209
1210 ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */
1211 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */
1212
1213 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1214 interrupt-names = "msi";
1215 #interrupt-cells = <1>;
1216 interrupt-map-mask = <0 0 0 0x7>;
1217 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1218 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1219 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1220 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1221
1222 clocks = <&gcc PCIE_2_A_CLK>,
1223 <&gcc PCIE_2_H_CLK>,
1224 <&gcc PCIE_2_PHY_CLK>,
1225 <&gcc PCIE_2_AUX_CLK>,
1226 <&gcc PCIE_2_ALT_REF_CLK>;
1227 clock-names = "core", "iface", "phy", "aux", "ref";
1228
1229 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1230 assigned-clock-rates = <100000000>;
1231
1232 resets = <&gcc PCIE_2_ACLK_RESET>,
1233 <&gcc PCIE_2_HCLK_RESET>,
1234 <&gcc PCIE_2_POR_RESET>,
1235 <&gcc PCIE_2_PCI_RESET>,
1236 <&gcc PCIE_2_PHY_RESET>,
1237 <&gcc PCIE_2_EXT_RESET>;
1238 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1239
1240 pinctrl-0 = <&pcie2_pins>;
1241 pinctrl-names = "default";
1242
1243 status = "disabled";
1244 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1245
1246 pcie@0 {
1247 device_type = "pci";
1248 reg = <0x0 0x0 0x0 0x0 0x0>;
1249 bus-range = <0x01 0xff>;
1250
1251 #address-cells = <3>;
1252 #size-cells = <2>;
1253 ranges;
1254 };
1255 };
1256
1257 qsgmii_csr: syscon@1bb00000 {
1258 compatible = "syscon";
1259 reg = <0x1bb00000 0x000001FF>;
1260 };
1261
1262 lcc: clock-controller@28000000 {
1263 compatible = "qcom,lcc-ipq8064";
1264 reg = <0x28000000 0x1000>;
1265 #clock-cells = <1>;
1266 #reset-cells = <1>;
1267 };
1268
1269 lpass@28100000 {
1270 compatible = "qcom,lpass-cpu";
1271 status = "disabled";
1272 clocks = <&lcc AHBIX_CLK>,
1273 <&lcc MI2S_OSR_CLK>,
1274 <&lcc MI2S_BIT_CLK>;
1275 clock-names = "ahbix-clk",
1276 "mi2s-osr-clk",
1277 "mi2s-bit-clk";
1278 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1279 interrupt-names = "lpass-irq-lpaif";
1280 reg = <0x28100000 0x10000>;
1281 reg-names = "lpass-lpaif";
1282 };
1283
1284 sata: sata@29000000 {
1285 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1286 reg = <0x29000000 0x180>;
1287
1288 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1289
1290 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1291 <&gcc SATA_H_CLK>,
1292 <&gcc SATA_A_CLK>,
1293 <&gcc SATA_RXOOB_CLK>,
1294 <&gcc SATA_PMALIVE_CLK>;
1295 clock-names = "slave_face", "iface", "core",
1296 "rxoob", "pmalive";
1297
1298 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1299 assigned-clock-rates = <100000000>, <100000000>;
1300
1301 phys = <&sata_phy>;
1302 phy-names = "sata-phy";
1303 status = "disabled";
1304 };
1305
1306 gmac0: ethernet@37000000 {
1307 device_type = "network";
1308 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1309 reg = <0x37000000 0x200000>;
1310 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1311 interrupt-names = "macirq";
1312
1313 snps,axi-config = <&stmmac_axi_setup>;
1314 snps,pbl = <32>;
1315 snps,aal;
1316
1317 qcom,nss-common = <&nss_common>;
1318 qcom,qsgmii-csr = <&qsgmii_csr>;
1319
1320 clocks = <&gcc GMAC_CORE1_CLK>;
1321 clock-names = "stmmaceth";
1322
1323 resets = <&gcc GMAC_CORE1_RESET>,
1324 <&gcc GMAC_AHB_RESET>;
1325 reset-names = "stmmaceth", "ahb";
1326
1327 status = "disabled";
1328 };
1329
1330 gmac1: ethernet@37200000 {
1331 device_type = "network";
1332 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1333 reg = <0x37200000 0x200000>;
1334 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1335 interrupt-names = "macirq";
1336
1337 snps,axi-config = <&stmmac_axi_setup>;
1338 snps,pbl = <32>;
1339 snps,aal;
1340
1341 qcom,nss-common = <&nss_common>;
1342 qcom,qsgmii-csr = <&qsgmii_csr>;
1343
1344 clocks = <&gcc GMAC_CORE2_CLK>;
1345 clock-names = "stmmaceth";
1346
1347 resets = <&gcc GMAC_CORE2_RESET>,
1348 <&gcc GMAC_AHB_RESET>;
1349 reset-names = "stmmaceth", "ahb";
1350
1351 status = "disabled";
1352 };
1353
1354 gmac2: ethernet@37400000 {
1355 device_type = "network";
1356 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1357 reg = <0x37400000 0x200000>;
1358 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1359 interrupt-names = "macirq";
1360
1361 snps,axi-config = <&stmmac_axi_setup>;
1362 snps,pbl = <32>;
1363 snps,aal;
1364
1365 qcom,nss-common = <&nss_common>;
1366 qcom,qsgmii-csr = <&qsgmii_csr>;
1367
1368 clocks = <&gcc GMAC_CORE3_CLK>;
1369 clock-names = "stmmaceth";
1370
1371 resets = <&gcc GMAC_CORE3_RESET>,
1372 <&gcc GMAC_AHB_RESET>;
1373 reset-names = "stmmaceth", "ahb";
1374
1375 status = "disabled";
1376 };
1377
1378 gmac3: ethernet@37600000 {
1379 device_type = "network";
1380 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1381 reg = <0x37600000 0x200000>;
1382 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1383 interrupt-names = "macirq";
1384
1385 snps,axi-config = <&stmmac_axi_setup>;
1386 snps,pbl = <32>;
1387 snps,aal;
1388
1389 qcom,nss-common = <&nss_common>;
1390 qcom,qsgmii-csr = <&qsgmii_csr>;
1391
1392 clocks = <&gcc GMAC_CORE4_CLK>;
1393 clock-names = "stmmaceth";
1394
1395 resets = <&gcc GMAC_CORE4_RESET>,
1396 <&gcc GMAC_AHB_RESET>;
1397 reset-names = "stmmaceth", "ahb";
1398
1399 status = "disabled";
1400 };
1401 };
1402 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.