1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
15
16 / {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&intc>;
20
21 chosen { };
22
23 clocks {
24 xo_board: xo_board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <19200000>;
28 };
29
30 sleep_clk: sleep_clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 clock-frequency = <32768>;
34 };
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 CPU0: cpu@0 {
42 compatible = "arm,cortex-a7";
43 enable-method = "qcom,msm8226-smp";
44 device_type = "cpu";
45 reg = <0>;
46 next-level-cache = <&L2>;
47 qcom,acc = <&acc0>;
48 qcom,saw = <&saw0>;
49 };
50
51 CPU1: cpu@1 {
52 compatible = "arm,cortex-a7";
53 enable-method = "qcom,msm8226-smp";
54 device_type = "cpu";
55 reg = <1>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc1>;
58 qcom,saw = <&saw1>;
59 };
60
61 CPU2: cpu@2 {
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,msm8226-smp";
64 device_type = "cpu";
65 reg = <2>;
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "arm,cortex-a7";
73 enable-method = "qcom,msm8226-smp";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 };
80
81 L2: l2-cache {
82 compatible = "cache";
83 cache-level = <2>;
84 cache-unified;
85 };
86 };
87
88 firmware {
89 scm {
90 compatible = "qcom,scm-msm8226", "qcom,scm";
91 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
92 clock-names = "core", "bus", "iface";
93 };
94 };
95
96 memory@0 {
97 device_type = "memory";
98 reg = <0x0 0x0>;
99 };
100
101 pmu {
102 compatible = "arm,cortex-a7-pmu";
103 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
104 IRQ_TYPE_LEVEL_HIGH)>;
105 };
106
107 rpm: remoteproc {
108 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
109
110 master-stats {
111 compatible = "qcom,rpm-master-stats";
112 qcom,rpm-msg-ram = <&apss_master_stats>,
113 <&mpss_master_stats>,
114 <&lpss_master_stats>,
115 <&pronto_master_stats>;
116 qcom,master-names = "APSS",
117 "MPSS",
118 "LPSS",
119 "PRONTO";
120 };
121
122 smd-edge {
123 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
124 qcom,ipc = <&apcs 8 0>;
125 qcom,smd-edge = <15>;
126
127 rpm_requests: rpm-requests {
128 compatible = "qcom,rpm-msm8226";
129 qcom,smd-channels = "rpm_requests";
130
131 rpmcc: clock-controller {
132 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
133 #clock-cells = <1>;
134 clocks = <&xo_board>;
135 clock-names = "xo";
136 };
137
138 rpmpd: power-controller {
139 compatible = "qcom,msm8226-rpmpd";
140 #power-domain-cells = <1>;
141 operating-points-v2 = <&rpmpd_opp_table>;
142
143 rpmpd_opp_table: opp-table {
144 compatible = "operating-points-v2";
145
146 rpmpd_opp_ret: opp1 {
147 opp-level = <1>;
148 };
149 rpmpd_opp_svs_krait: opp2 {
150 opp-level = <2>;
151 };
152 rpmpd_opp_svs_soc: opp3 {
153 opp-level = <3>;
154 };
155 rpmpd_opp_nom: opp4 {
156 opp-level = <4>;
157 };
158 rpmpd_opp_turbo: opp5 {
159 opp-level = <5>;
160 };
161 rpmpd_opp_super_turbo: opp6 {
162 opp-level = <6>;
163 };
164 };
165 };
166 };
167 };
168 };
169
170 reserved-memory {
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges;
174
175 smem_region: smem@3000000 {
176 reg = <0x3000000 0x100000>;
177 no-map;
178 };
179
180 adsp_region: adsp@dc00000 {
181 reg = <0x0dc00000 0x1900000>;
182 no-map;
183 };
184 };
185
186 smem {
187 compatible = "qcom,smem";
188
189 memory-region = <&smem_region>;
190 qcom,rpm-msg-ram = <&rpm_msg_ram>;
191
192 hwlocks = <&tcsr_mutex 3>;
193 };
194
195 smp2p-adsp {
196 compatible = "qcom,smp2p";
197 qcom,smem = <443>, <429>;
198
199 interrupt-parent = <&intc>;
200 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
201
202 qcom,ipc = <&apcs 8 10>;
203
204 qcom,local-pid = <0>;
205 qcom,remote-pid = <2>;
206
207 adsp_smp2p_out: master-kernel {
208 qcom,entry-name = "master-kernel";
209 #qcom,smem-state-cells = <1>;
210 };
211
212 adsp_smp2p_in: slave-kernel {
213 qcom,entry-name = "slave-kernel";
214
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 };
218 };
219
220 soc: soc {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges;
225
226 intc: interrupt-controller@f9000000 {
227 compatible = "qcom,msm-qgic2";
228 reg = <0xf9000000 0x1000>,
229 <0xf9002000 0x1000>;
230 interrupt-controller;
231 #interrupt-cells = <3>;
232 };
233
234 apcs: syscon@f9011000 {
235 compatible = "syscon";
236 reg = <0xf9011000 0x1000>;
237 };
238
239 saw_l2: power-manager@f9012000 {
240 compatible = "qcom,msm8226-saw2-v2.1-l2", "qcom,saw2";
241 reg = <0xf9012000 0x1000>;
242 };
243
244 watchdog@f9017000 {
245 compatible = "qcom,apss-wdt-msm8226", "qcom,kpss-wdt";
246 reg = <0xf9017000 0x1000>;
247 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
249 clocks = <&sleep_clk>;
250 };
251
252 timer@f9020000 {
253 compatible = "arm,armv7-timer-mem";
254 reg = <0xf9020000 0x1000>;
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges;
258
259 frame@f9021000 {
260 frame-number = <0>;
261 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0xf9021000 0x1000>,
264 <0xf9022000 0x1000>;
265 };
266
267 frame@f9023000 {
268 frame-number = <1>;
269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
270 reg = <0xf9023000 0x1000>;
271 status = "disabled";
272 };
273
274 frame@f9024000 {
275 frame-number = <2>;
276 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
277 reg = <0xf9024000 0x1000>;
278 status = "disabled";
279 };
280
281 frame@f9025000 {
282 frame-number = <3>;
283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
284 reg = <0xf9025000 0x1000>;
285 status = "disabled";
286 };
287
288 frame@f9026000 {
289 frame-number = <4>;
290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
291 reg = <0xf9026000 0x1000>;
292 status = "disabled";
293 };
294
295 frame@f9027000 {
296 frame-number = <5>;
297 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
298 reg = <0xf9027000 0x1000>;
299 status = "disabled";
300 };
301
302 frame@f9028000 {
303 frame-number = <6>;
304 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
305 reg = <0xf9028000 0x1000>;
306 status = "disabled";
307 };
308 };
309
310 acc0: power-manager@f9088000 {
311 compatible = "qcom,kpss-acc-v2";
312 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
313 };
314
315 saw0: power-manager@f9089000 {
316 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
317 reg = <0xf9089000 0x1000>;
318 };
319
320 acc1: power-manager@f9098000 {
321 compatible = "qcom,kpss-acc-v2";
322 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
323 };
324
325 saw1: power-manager@f9099000 {
326 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
327 reg = <0xf9099000 0x1000>;
328 };
329
330 acc2: power-manager@f90a8000 {
331 compatible = "qcom,kpss-acc-v2";
332 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
333 };
334
335 saw2: power-manager@f90a9000 {
336 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
337 reg = <0xf90a9000 0x1000>;
338 };
339
340 acc3: power-manager@f90b8000 {
341 compatible = "qcom,kpss-acc-v2";
342 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
343 };
344
345 saw3: power-manager@f90b9000 {
346 compatible = "qcom,msm8226-saw2-v2.1-cpu", "qcom,saw2";
347 reg = <0xf90b9000 0x1000>;
348 };
349
350 sdhc_1: mmc@f9824900 {
351 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
352 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
353 reg-names = "hc", "core";
354 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
356 interrupt-names = "hc_irq", "pwr_irq";
357 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
358 <&gcc GCC_SDCC1_APPS_CLK>,
359 <&rpmcc RPM_SMD_XO_CLK_SRC>;
360 clock-names = "iface", "core", "xo";
361 pinctrl-names = "default";
362 pinctrl-0 = <&sdhc1_default_state>;
363 status = "disabled";
364 };
365
366 sdhc_3: mmc@f9864900 {
367 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
368 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
369 reg-names = "hc", "core";
370 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "hc_irq", "pwr_irq";
373 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
374 <&gcc GCC_SDCC3_APPS_CLK>,
375 <&rpmcc RPM_SMD_XO_CLK_SRC>;
376 clock-names = "iface", "core", "xo";
377 pinctrl-names = "default";
378 pinctrl-0 = <&sdhc3_default_state>;
379 status = "disabled";
380 };
381
382 sdhc_2: mmc@f98a4900 {
383 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
384 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
385 reg-names = "hc", "core";
386 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
388 interrupt-names = "hc_irq", "pwr_irq";
389 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
390 <&gcc GCC_SDCC2_APPS_CLK>,
391 <&rpmcc RPM_SMD_XO_CLK_SRC>;
392 clock-names = "iface", "core", "xo";
393 pinctrl-names = "default";
394 pinctrl-0 = <&sdhc2_default_state>;
395 status = "disabled";
396 };
397
398 blsp1_uart1: serial@f991d000 {
399 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
400 reg = <0xf991d000 0x1000>;
401 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
403 clock-names = "core", "iface";
404 status = "disabled";
405 };
406
407 blsp1_uart2: serial@f991e000 {
408 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
409 reg = <0xf991e000 0x1000>;
410 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
412 <&gcc GCC_BLSP1_AHB_CLK>;
413 clock-names = "core",
414 "iface";
415 status = "disabled";
416 };
417
418 blsp1_uart3: serial@f991f000 {
419 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
420 reg = <0xf991f000 0x1000>;
421 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
423 clock-names = "core", "iface";
424 status = "disabled";
425 };
426
427 blsp1_uart4: serial@f9920000 {
428 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
429 reg = <0xf9920000 0x1000>;
430 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
432 clock-names = "core", "iface";
433 status = "disabled";
434 };
435
436 blsp1_i2c1: i2c@f9923000 {
437 compatible = "qcom,i2c-qup-v2.1.1";
438 reg = <0xf9923000 0x1000>;
439 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
441 clock-names = "core", "iface";
442 pinctrl-names = "default";
443 pinctrl-0 = <&blsp1_i2c1_pins>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 blsp1_i2c2: i2c@f9924000 {
450 compatible = "qcom,i2c-qup-v2.1.1";
451 reg = <0xf9924000 0x1000>;
452 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
454 clock-names = "core", "iface";
455 pinctrl-names = "default";
456 pinctrl-0 = <&blsp1_i2c2_pins>;
457 #address-cells = <1>;
458 #size-cells = <0>;
459 status = "disabled";
460 };
461
462 blsp1_i2c3: i2c@f9925000 {
463 compatible = "qcom,i2c-qup-v2.1.1";
464 reg = <0xf9925000 0x1000>;
465 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
467 clock-names = "core", "iface";
468 pinctrl-names = "default";
469 pinctrl-0 = <&blsp1_i2c3_pins>;
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
474
475 blsp1_i2c4: i2c@f9926000 {
476 compatible = "qcom,i2c-qup-v2.1.1";
477 reg = <0xf9926000 0x1000>;
478 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
480 clock-names = "core", "iface";
481 pinctrl-names = "default";
482 pinctrl-0 = <&blsp1_i2c4_pins>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
487
488 blsp1_i2c5: i2c@f9927000 {
489 compatible = "qcom,i2c-qup-v2.1.1";
490 reg = <0xf9927000 0x1000>;
491 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
493 clock-names = "core", "iface";
494 pinctrl-names = "default";
495 pinctrl-0 = <&blsp1_i2c5_pins>;
496 #address-cells = <1>;
497 #size-cells = <0>;
498 status = "disabled";
499 };
500
501 blsp1_i2c6: i2c@f9928000 {
502 compatible = "qcom,i2c-qup-v2.1.1";
503 reg = <0xf9928000 0x1000>;
504 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
506 <&gcc GCC_BLSP1_AHB_CLK>;
507 clock-names = "core",
508 "iface";
509 pinctrl-0 = <&blsp1_i2c6_pins>;
510 pinctrl-names = "default";
511 #address-cells = <1>;
512 #size-cells = <0>;
513 status = "disabled";
514 };
515
516 usb: usb@f9a55000 {
517 compatible = "qcom,ci-hdrc";
518 reg = <0xf9a55000 0x200>,
519 <0xf9a55200 0x200>;
520 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
522 <&gcc GCC_USB_HS_SYSTEM_CLK>;
523 clock-names = "iface", "core";
524 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
525 assigned-clock-rates = <75000000>;
526 resets = <&gcc GCC_USB_HS_BCR>;
527 reset-names = "core";
528 phy_type = "ulpi";
529 dr_mode = "otg";
530 hnp-disable;
531 srp-disable;
532 adp-disable;
533 ahb-burst-config = <0>;
534 phy-names = "usb-phy";
535 phys = <&usb_hs_phy>;
536 status = "disabled";
537 #reset-cells = <1>;
538
539 ulpi {
540 usb_hs_phy: phy {
541 compatible = "qcom,usb-hs-phy-msm8226",
542 "qcom,usb-hs-phy";
543 #phy-cells = <0>;
544 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
545 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
546 clock-names = "ref", "sleep";
547 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
548 reset-names = "phy", "por";
549 qcom,init-seq = /bits/ 8 <0x0 0x44
550 0x1 0x68 0x2 0x24 0x3 0x13>;
551 };
552 };
553 };
554
555 rng@f9bff000 {
556 compatible = "qcom,prng";
557 reg = <0xf9bff000 0x200>;
558 clocks = <&gcc GCC_PRNG_AHB_CLK>;
559 clock-names = "core";
560 };
561
562 sram@fc190000 {
563 compatible = "qcom,msm8226-rpm-stats";
564 reg = <0xfc190000 0x10000>;
565 };
566
567 gcc: clock-controller@fc400000 {
568 compatible = "qcom,gcc-msm8226";
569 reg = <0xfc400000 0x4000>;
570 #clock-cells = <1>;
571 #reset-cells = <1>;
572 #power-domain-cells = <1>;
573
574 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
575 <&sleep_clk>;
576 clock-names = "xo",
577 "sleep_clk";
578 };
579
580 rpm_msg_ram: sram@fc428000 {
581 compatible = "qcom,rpm-msg-ram";
582 reg = <0xfc428000 0x4000>;
583
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges = <0 0xfc428000 0x4000>;
587
588 apss_master_stats: sram@150 {
589 reg = <0x150 0x14>;
590 };
591
592 mpss_master_stats: sram@b50 {
593 reg = <0xb50 0x14>;
594 };
595
596 lpss_master_stats: sram@1550 {
597 reg = <0x1550 0x14>;
598 };
599
600 pronto_master_stats: sram@1f50 {
601 reg = <0x1f50 0x14>;
602 };
603 };
604
605 tsens: thermal-sensor@fc4a9000 {
606 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
607 reg = <0xfc4a9000 0x1000>, /* TM */
608 <0xfc4a8000 0x1000>; /* SROT */
609 nvmem-cells = <&tsens_mode>,
610 <&tsens_base1>, <&tsens_base2>,
611 <&tsens_s0_p1>, <&tsens_s0_p2>,
612 <&tsens_s1_p1>, <&tsens_s1_p2>,
613 <&tsens_s2_p1>, <&tsens_s2_p2>,
614 <&tsens_s3_p1>, <&tsens_s3_p2>,
615 <&tsens_s4_p1>, <&tsens_s4_p2>,
616 <&tsens_s5_p1>, <&tsens_s5_p2>,
617 <&tsens_s6_p1>, <&tsens_s6_p2>;
618 nvmem-cell-names = "mode",
619 "base1", "base2",
620 "s0_p1", "s0_p2",
621 "s1_p1", "s1_p2",
622 "s2_p1", "s2_p2",
623 "s3_p1", "s3_p2",
624 "s4_p1", "s4_p2",
625 "s5_p1", "s5_p2",
626 "s6_p1", "s6_p2";
627 #qcom,sensors = <6>;
628 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
629 interrupt-names = "uplow";
630 #thermal-sensor-cells = <1>;
631 };
632
633 restart@fc4ab000 {
634 compatible = "qcom,pshold";
635 reg = <0xfc4ab000 0x4>;
636 };
637
638 qfprom: efuse@fc4bc000 {
639 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
640 reg = <0xfc4bc000 0x1000>;
641 #address-cells = <1>;
642 #size-cells = <1>;
643
644 tsens_base1: base1@1c1 {
645 reg = <0x1c1 0x2>;
646 bits = <5 8>;
647 };
648
649 tsens_s0_p1: s0-p1@1c2 {
650 reg = <0x1c2 0x2>;
651 bits = <5 6>;
652 };
653
654 tsens_s1_p1: s1-p1@1c4 {
655 reg = <0x1c4 0x1>;
656 bits = <0 6>;
657 };
658
659 tsens_s2_p1: s2-p1@1c4 {
660 reg = <0x1c4 0x2>;
661 bits = <6 6>;
662 };
663
664 tsens_s3_p1: s3-p1@1c5 {
665 reg = <0x1c5 0x2>;
666 bits = <4 6>;
667 };
668
669 tsens_s4_p1: s4-p1@1c6 {
670 reg = <0x1c6 0x1>;
671 bits = <2 6>;
672 };
673
674 tsens_s5_p1: s5-p1@1c7 {
675 reg = <0x1c7 0x1>;
676 bits = <0 6>;
677 };
678
679 tsens_s6_p1: s6-p1@1ca {
680 reg = <0x1ca 0x2>;
681 bits = <4 6>;
682 };
683
684 tsens_base2: base2@1cc {
685 reg = <0x1cc 0x1>;
686 bits = <0 8>;
687 };
688
689 tsens_s0_p2: s0-p2@1cd {
690 reg = <0x1cd 0x1>;
691 bits = <0 6>;
692 };
693
694 tsens_s1_p2: s1-p2@1cd {
695 reg = <0x1cd 0x2>;
696 bits = <6 6>;
697 };
698
699 tsens_s2_p2: s2-p2@1ce {
700 reg = <0x1ce 0x2>;
701 bits = <4 6>;
702 };
703
704 tsens_s3_p2: s3-p2@1cf {
705 reg = <0x1cf 0x1>;
706 bits = <2 6>;
707 };
708
709 tsens_s4_p2: s4-p2@446 {
710 reg = <0x446 0x2>;
711 bits = <4 6>;
712 };
713
714 tsens_s5_p2: s5-p2@447 {
715 reg = <0x447 0x1>;
716 bits = <2 6>;
717 };
718
719 tsens_s6_p2: s6-p2@44e {
720 reg = <0x44e 0x1>;
721 bits = <1 6>;
722 };
723
724 tsens_mode: mode@44f {
725 reg = <0x44f 0x1>;
726 bits = <5 3>;
727 };
728 };
729
730 spmi_bus: spmi@fc4cf000 {
731 compatible = "qcom,spmi-pmic-arb";
732 reg-names = "core", "intr", "cnfg";
733 reg = <0xfc4cf000 0x1000>,
734 <0xfc4cb000 0x1000>,
735 <0xfc4ca000 0x1000>;
736 interrupt-names = "periph_irq";
737 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
738 qcom,ee = <0>;
739 qcom,channel = <0>;
740 #address-cells = <2>;
741 #size-cells = <0>;
742 interrupt-controller;
743 #interrupt-cells = <4>;
744 };
745
746 tcsr_mutex: hwlock@fd484000 {
747 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
748 reg = <0xfd484000 0x1000>;
749 #hwlock-cells = <1>;
750 };
751
752 tlmm: pinctrl@fd510000 {
753 compatible = "qcom,msm8226-pinctrl";
754 reg = <0xfd510000 0x4000>;
755 gpio-controller;
756 #gpio-cells = <2>;
757 gpio-ranges = <&tlmm 0 0 117>;
758 interrupt-controller;
759 #interrupt-cells = <2>;
760 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
761
762 blsp1_i2c1_pins: blsp1-i2c1-state {
763 pins = "gpio2", "gpio3";
764 function = "blsp_i2c1";
765 drive-strength = <2>;
766 bias-disable;
767 };
768
769 blsp1_i2c2_pins: blsp1-i2c2-state {
770 pins = "gpio6", "gpio7";
771 function = "blsp_i2c2";
772 drive-strength = <2>;
773 bias-disable;
774 };
775
776 blsp1_i2c3_pins: blsp1-i2c3-state {
777 pins = "gpio10", "gpio11";
778 function = "blsp_i2c3";
779 drive-strength = <2>;
780 bias-disable;
781 };
782
783 blsp1_i2c4_pins: blsp1-i2c4-state {
784 pins = "gpio14", "gpio15";
785 function = "blsp_i2c4";
786 drive-strength = <2>;
787 bias-disable;
788 };
789
790 blsp1_i2c5_pins: blsp1-i2c5-state {
791 pins = "gpio18", "gpio19";
792 function = "blsp_i2c5";
793 drive-strength = <2>;
794 bias-disable;
795 };
796
797 blsp1_i2c6_pins: blsp1-i2c6-state {
798 pins = "gpio22", "gpio23";
799 function = "blsp_i2c6";
800 drive-strength = <2>;
801 bias-disable;
802 };
803
804 cci_default: cci-default-state {
805 pins = "gpio29", "gpio30";
806 function = "cci_i2c0";
807
808 drive-strength = <2>;
809 bias-disable;
810 };
811
812 cci_sleep: cci-sleep-state {
813 pins = "gpio29", "gpio30";
814 function = "gpio";
815
816 drive-strength = <2>;
817 bias-disable;
818 };
819
820 sdhc1_default_state: sdhc1-default-state {
821 clk-pins {
822 pins = "sdc1_clk";
823 drive-strength = <10>;
824 bias-disable;
825 };
826
827 cmd-data-pins {
828 pins = "sdc1_cmd", "sdc1_data";
829 drive-strength = <10>;
830 bias-pull-up;
831 };
832 };
833
834 sdhc2_default_state: sdhc2-default-state {
835 clk-pins {
836 pins = "sdc2_clk";
837 drive-strength = <10>;
838 bias-disable;
839 };
840
841 cmd-data-pins {
842 pins = "sdc2_cmd", "sdc2_data";
843 drive-strength = <10>;
844 bias-pull-up;
845 };
846 };
847
848 sdhc3_default_state: sdhc3-default-state {
849 clk-pins {
850 pins = "gpio44";
851 function = "sdc3";
852 drive-strength = <8>;
853 bias-disable;
854 };
855
856 cmd-pins {
857 pins = "gpio43";
858 function = "sdc3";
859 drive-strength = <8>;
860 bias-pull-up;
861 };
862
863 data-pins {
864 pins = "gpio39", "gpio40", "gpio41", "gpio42";
865 function = "sdc3";
866 drive-strength = <8>;
867 bias-pull-up;
868 };
869 };
870 };
871
872 mmcc: clock-controller@fd8c0000 {
873 compatible = "qcom,mmcc-msm8226";
874 reg = <0xfd8c0000 0x6000>;
875 #clock-cells = <1>;
876 #reset-cells = <1>;
877 #power-domain-cells = <1>;
878
879 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
880 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
881 <&gcc GPLL0_VOTE>,
882 <&gcc GPLL1_VOTE>,
883 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
884 <&mdss_dsi0_phy 1>,
885 <&mdss_dsi0_phy 0>;
886 clock-names = "xo",
887 "mmss_gpll0_vote",
888 "gpll0_vote",
889 "gpll1_vote",
890 "gfx3d_clk_src",
891 "dsi0pll",
892 "dsi0pllbyte";
893 };
894
895 mdss: display-subsystem@fd900000 {
896 compatible = "qcom,mdss";
897 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
898 reg-names = "mdss_phys", "vbif_phys";
899
900 power-domains = <&mmcc MDSS_GDSC>;
901
902 clocks = <&mmcc MDSS_AHB_CLK>,
903 <&mmcc MDSS_AXI_CLK>,
904 <&mmcc MDSS_VSYNC_CLK>;
905 clock-names = "iface",
906 "bus",
907 "vsync";
908
909 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
910
911 interrupt-controller;
912 #interrupt-cells = <1>;
913
914 #address-cells = <1>;
915 #size-cells = <1>;
916 ranges;
917
918 status = "disabled";
919
920 mdss_mdp: display-controller@fd900000 {
921 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
922 reg = <0xfd900100 0x22000>;
923 reg-names = "mdp_phys";
924
925 interrupt-parent = <&mdss>;
926 interrupts = <0>;
927
928 clocks = <&mmcc MDSS_AHB_CLK>,
929 <&mmcc MDSS_AXI_CLK>,
930 <&mmcc MDSS_MDP_CLK>,
931 <&mmcc MDSS_VSYNC_CLK>;
932 clock-names = "iface",
933 "bus",
934 "core",
935 "vsync";
936
937 ports {
938 #address-cells = <1>;
939 #size-cells = <0>;
940
941 port@0 {
942 reg = <0>;
943 mdss_mdp_intf1_out: endpoint {
944 remote-endpoint = <&mdss_dsi0_in>;
945 };
946 };
947 };
948 };
949
950 mdss_dsi0: dsi@fd922800 {
951 compatible = "qcom,msm8226-dsi-ctrl",
952 "qcom,mdss-dsi-ctrl";
953 reg = <0xfd922800 0x1f8>;
954 reg-names = "dsi_ctrl";
955
956 interrupt-parent = <&mdss>;
957 interrupts = <4>;
958
959 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
960 <&mmcc PCLK0_CLK_SRC>;
961 assigned-clock-parents = <&mdss_dsi0_phy 0>,
962 <&mdss_dsi0_phy 1>;
963
964 clocks = <&mmcc MDSS_MDP_CLK>,
965 <&mmcc MDSS_AHB_CLK>,
966 <&mmcc MDSS_AXI_CLK>,
967 <&mmcc MDSS_BYTE0_CLK>,
968 <&mmcc MDSS_PCLK0_CLK>,
969 <&mmcc MDSS_ESC0_CLK>,
970 <&mmcc MMSS_MISC_AHB_CLK>;
971 clock-names = "mdp_core",
972 "iface",
973 "bus",
974 "byte",
975 "pixel",
976 "core",
977 "core_mmss";
978
979 phys = <&mdss_dsi0_phy>;
980
981 #address-cells = <1>;
982 #size-cells = <0>;
983
984 ports {
985 #address-cells = <1>;
986 #size-cells = <0>;
987
988 port@0 {
989 reg = <0>;
990 mdss_dsi0_in: endpoint {
991 remote-endpoint = <&mdss_mdp_intf1_out>;
992 };
993 };
994
995 port@1 {
996 reg = <1>;
997 mdss_dsi0_out: endpoint {
998 };
999 };
1000 };
1001 };
1002
1003 mdss_dsi0_phy: phy@fd922a00 {
1004 compatible = "qcom,dsi-phy-28nm-8226";
1005 reg = <0xfd922a00 0xd4>,
1006 <0xfd922b00 0x280>,
1007 <0xfd922d80 0x30>;
1008 reg-names = "dsi_pll",
1009 "dsi_phy",
1010 "dsi_phy_regulator";
1011
1012 #clock-cells = <1>;
1013 #phy-cells = <0>;
1014
1015 clocks = <&mmcc MDSS_AHB_CLK>,
1016 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1017 clock-names = "iface",
1018 "ref";
1019 };
1020 };
1021
1022 cci: cci@fda0c000 {
1023 compatible = "qcom,msm8226-cci";
1024 reg = <0xfda0c000 0x1000>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1028 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1029 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
1030 <&mmcc CAMSS_CCI_CCI_CLK>;
1031 clock-names = "camss_top_ahb",
1032 "cci_ahb",
1033 "cci";
1034
1035 pinctrl-names = "default", "sleep";
1036 pinctrl-0 = <&cci_default>;
1037 pinctrl-1 = <&cci_sleep>;
1038
1039 status = "disabled";
1040
1041 cci_i2c0: i2c-bus@0 {
1042 reg = <0>;
1043 clock-frequency = <400000>;
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 };
1047 };
1048
1049 gpu: gpu@fdb00000 {
1050 compatible = "qcom,adreno-305.18", "qcom,adreno";
1051 reg = <0xfdb00000 0x10000>;
1052 reg-names = "kgsl_3d0_reg_memory";
1053
1054 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1055 interrupt-names = "kgsl_3d0_irq";
1056
1057 clocks = <&mmcc OXILI_GFX3D_CLK>,
1058 <&mmcc OXILICX_AHB_CLK>,
1059 <&mmcc OXILICX_AXI_CLK>;
1060 clock-names = "core", "iface", "mem_iface";
1061
1062 sram = <&gmu_sram>;
1063 power-domains = <&mmcc OXILICX_GDSC>;
1064 operating-points-v2 = <&gpu_opp_table>;
1065
1066 status = "disabled";
1067
1068 gpu_opp_table: opp-table {
1069 compatible = "operating-points-v2";
1070
1071 opp-450000000 {
1072 opp-hz = /bits/ 64 <450000000>;
1073 };
1074
1075 opp-320000000 {
1076 opp-hz = /bits/ 64 <320000000>;
1077 };
1078
1079 opp-200000000 {
1080 opp-hz = /bits/ 64 <200000000>;
1081 };
1082
1083 opp-19000000 {
1084 opp-hz = /bits/ 64 <19000000>;
1085 };
1086 };
1087 };
1088
1089 sram@fdd00000 {
1090 compatible = "qcom,msm8226-ocmem";
1091 reg = <0xfdd00000 0x2000>,
1092 <0xfec00000 0x20000>;
1093 reg-names = "ctrl", "mem";
1094 ranges = <0 0xfec00000 0x20000>;
1095 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>;
1096 clock-names = "core";
1097
1098 #address-cells = <1>;
1099 #size-cells = <1>;
1100
1101 gmu_sram: gmu-sram@0 {
1102 reg = <0x0 0x20000>;
1103 };
1104 };
1105
1106 adsp: remoteproc@fe200000 {
1107 compatible = "qcom,msm8226-adsp-pil";
1108 reg = <0xfe200000 0x100>;
1109
1110 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
1111 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1112 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1113 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1114 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1115 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1116
1117 power-domains = <&rpmpd MSM8226_VDDCX>;
1118 power-domain-names = "cx";
1119
1120 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1121 clock-names = "xo";
1122
1123 memory-region = <&adsp_region>;
1124
1125 qcom,smem-states = <&adsp_smp2p_out 0>;
1126 qcom,smem-state-names = "stop";
1127
1128 status = "disabled";
1129
1130 smd-edge {
1131 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1132
1133 qcom,ipc = <&apcs 8 8>;
1134 qcom,smd-edge = <1>;
1135
1136 label = "lpass";
1137 };
1138 };
1139
1140 sram@fe805000 {
1141 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
1142 reg = <0xfe805000 0x1000>;
1143
1144 reboot-mode {
1145 compatible = "syscon-reboot-mode";
1146 offset = <0x65c>;
1147
1148 mode-bootloader = <0x77665500>;
1149 mode-normal = <0x77665501>;
1150 mode-recovery = <0x77665502>;
1151 };
1152 };
1153 };
1154
1155 thermal-zones {
1156 cpu0-thermal {
1157 polling-delay-passive = <250>;
1158 polling-delay = <1000>;
1159
1160 thermal-sensors = <&tsens 5>;
1161
1162 trips {
1163 cpu_alert0: trip0 {
1164 temperature = <75000>;
1165 hysteresis = <2000>;
1166 type = "passive";
1167 };
1168
1169 cpu_crit0: trip1 {
1170 temperature = <110000>;
1171 hysteresis = <2000>;
1172 type = "critical";
1173 };
1174 };
1175 };
1176
1177 cpu1-thermal {
1178 polling-delay-passive = <250>;
1179 polling-delay = <1000>;
1180
1181 thermal-sensors = <&tsens 2>;
1182
1183 trips {
1184 cpu_alert1: trip0 {
1185 temperature = <75000>;
1186 hysteresis = <2000>;
1187 type = "passive";
1188 };
1189
1190 cpu_crit1: trip1 {
1191 temperature = <110000>;
1192 hysteresis = <2000>;
1193 type = "critical";
1194 };
1195 };
1196 };
1197 };
1198
1199 timer {
1200 compatible = "arm,armv7-timer";
1201 interrupts = <GIC_PPI 2
1202 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1203 <GIC_PPI 3
1204 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1205 <GIC_PPI 4
1206 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
1207 <GIC_PPI 1
1208 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
1209 };
1210 };
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