1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
3
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
11
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 interrupt-parent = <&intc>;
16
17 chosen { };
18
19 clocks {
20 xo_board: xo_board {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <19200000>;
24 };
25
26 sleep_clk: sleep_clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <32768>;
30 };
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
37
38 CPU0: cpu@0 {
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v2";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CPU_SPC>;
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v2";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v2";
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CPU_SPC>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v2";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CPU_SPC>;
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 cache-unified;
86 qcom,saw = <&saw_l2>;
87 };
88
89 idle-states {
90 CPU_SPC: cpu-spc {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <150>;
94 exit-latency-us = <200>;
95 min-residency-us = <2000>;
96 };
97 };
98 };
99
100 firmware {
101 scm {
102 compatible = "qcom,scm-msm8974", "qcom,scm";
103 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
104 clock-names = "core", "bus", "iface";
105 };
106 };
107
108 memory@0 {
109 device_type = "memory";
110 reg = <0x0 0x0>;
111 };
112
113 pmu {
114 compatible = "qcom,krait-pmu";
115 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
116 };
117
118 rpm: remoteproc {
119 compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc";
120
121 master-stats {
122 compatible = "qcom,rpm-master-stats";
123 qcom,rpm-msg-ram = <&apss_master_stats>,
124 <&mpss_master_stats>,
125 <&lpss_master_stats>,
126 <&pronto_master_stats>;
127 qcom,master-names = "APSS",
128 "MPSS",
129 "LPSS",
130 "PRONTO";
131 };
132
133 smd-edge {
134 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
135 mboxes = <&apcs 0>;
136 qcom,smd-edge = <15>;
137
138 rpm_requests: rpm-requests {
139 compatible = "qcom,rpm-msm8974";
140 qcom,smd-channels = "rpm_requests";
141
142 rpmcc: clock-controller {
143 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
144 #clock-cells = <1>;
145 clocks = <&xo_board>;
146 clock-names = "xo";
147 };
148 };
149 };
150 };
151
152 reserved-memory {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 ranges;
156
157 mpss_region: mpss@8000000 {
158 reg = <0x08000000 0x5100000>;
159 no-map;
160 };
161
162 mba_region: mba@d100000 {
163 reg = <0x0d100000 0x100000>;
164 no-map;
165 };
166
167 wcnss_region: wcnss@d200000 {
168 reg = <0x0d200000 0xa00000>;
169 no-map;
170 };
171
172 adsp_region: adsp@dc00000 {
173 reg = <0x0dc00000 0x1900000>;
174 no-map;
175 };
176
177 venus_region: memory@f500000 {
178 reg = <0x0f500000 0x500000>;
179 no-map;
180 };
181
182 smem_region: smem@fa00000 {
183 reg = <0xfa00000 0x200000>;
184 no-map;
185 };
186
187 tz_region: memory@fc00000 {
188 reg = <0x0fc00000 0x160000>;
189 no-map;
190 };
191
192 rfsa_mem: memory@fd60000 {
193 reg = <0x0fd60000 0x20000>;
194 no-map;
195 };
196
197 rmtfs@fd80000 {
198 compatible = "qcom,rmtfs-mem";
199 reg = <0x0fd80000 0x180000>;
200 no-map;
201
202 qcom,client-id = <1>;
203 };
204 };
205
206 smem {
207 compatible = "qcom,smem";
208
209 memory-region = <&smem_region>;
210 qcom,rpm-msg-ram = <&rpm_msg_ram>;
211
212 hwlocks = <&tcsr_mutex 3>;
213 };
214
215 smp2p-adsp {
216 compatible = "qcom,smp2p";
217 qcom,smem = <443>, <429>;
218
219 interrupt-parent = <&intc>;
220 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
221
222 mboxes = <&apcs 10>;
223
224 qcom,local-pid = <0>;
225 qcom,remote-pid = <2>;
226
227 adsp_smp2p_out: master-kernel {
228 qcom,entry-name = "master-kernel";
229 #qcom,smem-state-cells = <1>;
230 };
231
232 adsp_smp2p_in: slave-kernel {
233 qcom,entry-name = "slave-kernel";
234
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 };
238 };
239
240 smp2p-modem {
241 compatible = "qcom,smp2p";
242 qcom,smem = <435>, <428>;
243
244 interrupt-parent = <&intc>;
245 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
246
247 mboxes = <&apcs 14>;
248
249 qcom,local-pid = <0>;
250 qcom,remote-pid = <1>;
251
252 modem_smp2p_out: master-kernel {
253 qcom,entry-name = "master-kernel";
254 #qcom,smem-state-cells = <1>;
255 };
256
257 modem_smp2p_in: slave-kernel {
258 qcom,entry-name = "slave-kernel";
259
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
263 };
264
265 smp2p-wcnss {
266 compatible = "qcom,smp2p";
267 qcom,smem = <451>, <431>;
268
269 interrupt-parent = <&intc>;
270 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
271
272 mboxes = <&apcs 18>;
273
274 qcom,local-pid = <0>;
275 qcom,remote-pid = <4>;
276
277 wcnss_smp2p_out: master-kernel {
278 qcom,entry-name = "master-kernel";
279
280 #qcom,smem-state-cells = <1>;
281 };
282
283 wcnss_smp2p_in: slave-kernel {
284 qcom,entry-name = "slave-kernel";
285
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 };
289 };
290
291 smsm {
292 compatible = "qcom,smsm";
293
294 #address-cells = <1>;
295 #size-cells = <0>;
296
297 mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>;
298
299 apps_smsm: apps@0 {
300 reg = <0>;
301
302 #qcom,smem-state-cells = <1>;
303 };
304
305 modem_smsm: modem@1 {
306 reg = <1>;
307 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
308
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 adsp_smsm: adsp@2 {
314 reg = <2>;
315 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
316
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 wcnss_smsm: wcnss@7 {
322 reg = <7>;
323 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
324
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328 };
329
330 soc: soc {
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334 compatible = "simple-bus";
335
336 intc: interrupt-controller@f9000000 {
337 compatible = "qcom,msm-qgic2";
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 reg = <0xf9000000 0x1000>,
341 <0xf9002000 0x1000>;
342 };
343
344 apcs: mailbox@f9011000 {
345 compatible = "qcom,msm8974-apcs-kpss-global",
346 "qcom,msm8994-apcs-kpss-global", "syscon";
347 reg = <0xf9011000 0x1000>;
348 #mbox-cells = <1>;
349 };
350
351 saw_l2: power-manager@f9012000 {
352 compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
353 reg = <0xf9012000 0x1000>;
354 };
355
356 watchdog@f9017000 {
357 compatible = "qcom,apss-wdt-msm8974", "qcom,kpss-wdt";
358 reg = <0xf9017000 0x1000>;
359 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
360 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
361 clocks = <&sleep_clk>;
362 };
363
364 timer@f9020000 {
365 #address-cells = <1>;
366 #size-cells = <1>;
367 ranges;
368 compatible = "arm,armv7-timer-mem";
369 reg = <0xf9020000 0x1000>;
370 clock-frequency = <19200000>;
371
372 frame@f9021000 {
373 frame-number = <0>;
374 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
376 reg = <0xf9021000 0x1000>,
377 <0xf9022000 0x1000>;
378 };
379
380 frame@f9023000 {
381 frame-number = <1>;
382 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
383 reg = <0xf9023000 0x1000>;
384 status = "disabled";
385 };
386
387 frame@f9024000 {
388 frame-number = <2>;
389 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
390 reg = <0xf9024000 0x1000>;
391 status = "disabled";
392 };
393
394 frame@f9025000 {
395 frame-number = <3>;
396 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
397 reg = <0xf9025000 0x1000>;
398 status = "disabled";
399 };
400
401 frame@f9026000 {
402 frame-number = <4>;
403 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
404 reg = <0xf9026000 0x1000>;
405 status = "disabled";
406 };
407
408 frame@f9027000 {
409 frame-number = <5>;
410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
411 reg = <0xf9027000 0x1000>;
412 status = "disabled";
413 };
414
415 frame@f9028000 {
416 frame-number = <6>;
417 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
418 reg = <0xf9028000 0x1000>;
419 status = "disabled";
420 };
421 };
422
423 acc0: power-manager@f9088000 {
424 compatible = "qcom,kpss-acc-v2";
425 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
426 };
427
428 saw0: power-manager@f9089000 {
429 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
430 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
431 };
432
433 acc1: power-manager@f9098000 {
434 compatible = "qcom,kpss-acc-v2";
435 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
436 };
437
438 saw1: power-manager@f9099000 {
439 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
440 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
441 };
442
443 acc2: power-manager@f90a8000 {
444 compatible = "qcom,kpss-acc-v2";
445 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
446 };
447
448 saw2: power-manager@f90a9000 {
449 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
450 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
451 };
452
453 acc3: power-manager@f90b8000 {
454 compatible = "qcom,kpss-acc-v2";
455 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
456 };
457
458 saw3: power-manager@f90b9000 {
459 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
460 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
461 };
462
463 sdhc_1: mmc@f9824900 {
464 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
465 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
466 reg-names = "hc", "core";
467 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "hc_irq", "pwr_irq";
470 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
471 <&gcc GCC_SDCC1_APPS_CLK>,
472 <&xo_board>;
473 clock-names = "iface", "core", "xo";
474 bus-width = <8>;
475 non-removable;
476
477 status = "disabled";
478 };
479
480 sdhc_3: mmc@f9864900 {
481 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
482 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
483 reg-names = "hc", "core";
484 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
486 interrupt-names = "hc_irq", "pwr_irq";
487 clocks = <&gcc GCC_SDCC3_AHB_CLK>,
488 <&gcc GCC_SDCC3_APPS_CLK>,
489 <&xo_board>;
490 clock-names = "iface", "core", "xo";
491 bus-width = <4>;
492
493 #address-cells = <1>;
494 #size-cells = <0>;
495
496 status = "disabled";
497 };
498
499 sdhc_2: mmc@f98a4900 {
500 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
501 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
502 reg-names = "hc", "core";
503 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
505 interrupt-names = "hc_irq", "pwr_irq";
506 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
507 <&gcc GCC_SDCC2_APPS_CLK>,
508 <&xo_board>;
509 clock-names = "iface", "core", "xo";
510 bus-width = <4>;
511
512 #address-cells = <1>;
513 #size-cells = <0>;
514
515 status = "disabled";
516 };
517
518 blsp1_uart1: serial@f991d000 {
519 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
520 reg = <0xf991d000 0x1000>;
521 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
523 clock-names = "core", "iface";
524 status = "disabled";
525 };
526
527 blsp1_uart2: serial@f991e000 {
528 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
529 reg = <0xf991e000 0x1000>;
530 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
532 clock-names = "core", "iface";
533 pinctrl-names = "default";
534 pinctrl-0 = <&blsp1_uart2_default>;
535 status = "disabled";
536 };
537
538 blsp1_i2c1: i2c@f9923000 {
539 status = "disabled";
540 compatible = "qcom,i2c-qup-v2.1.1";
541 reg = <0xf9923000 0x1000>;
542 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
544 clock-names = "core", "iface";
545 pinctrl-names = "default", "sleep";
546 pinctrl-0 = <&blsp1_i2c1_default>;
547 pinctrl-1 = <&blsp1_i2c1_sleep>;
548 #address-cells = <1>;
549 #size-cells = <0>;
550 };
551
552 blsp1_i2c2: i2c@f9924000 {
553 status = "disabled";
554 compatible = "qcom,i2c-qup-v2.1.1";
555 reg = <0xf9924000 0x1000>;
556 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
558 clock-names = "core", "iface";
559 pinctrl-names = "default", "sleep";
560 pinctrl-0 = <&blsp1_i2c2_default>;
561 pinctrl-1 = <&blsp1_i2c2_sleep>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 };
565
566 blsp1_i2c3: i2c@f9925000 {
567 status = "disabled";
568 compatible = "qcom,i2c-qup-v2.1.1";
569 reg = <0xf9925000 0x1000>;
570 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
572 clock-names = "core", "iface";
573 pinctrl-names = "default", "sleep";
574 pinctrl-0 = <&blsp1_i2c3_default>;
575 pinctrl-1 = <&blsp1_i2c3_sleep>;
576 #address-cells = <1>;
577 #size-cells = <0>;
578 };
579
580 blsp1_i2c6: i2c@f9928000 {
581 status = "disabled";
582 compatible = "qcom,i2c-qup-v2.1.1";
583 reg = <0xf9928000 0x1000>;
584 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
586 clock-names = "core", "iface";
587 pinctrl-names = "default", "sleep";
588 pinctrl-0 = <&blsp1_i2c6_default>;
589 pinctrl-1 = <&blsp1_i2c6_sleep>;
590 #address-cells = <1>;
591 #size-cells = <0>;
592 };
593
594 blsp2_dma: dma-controller@f9944000 {
595 compatible = "qcom,bam-v1.4.0";
596 reg = <0xf9944000 0x19000>;
597 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
599 clock-names = "bam_clk";
600 #dma-cells = <1>;
601 qcom,ee = <0>;
602 };
603
604 blsp2_uart1: serial@f995d000 {
605 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
606 reg = <0xf995d000 0x1000>;
607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
609 clock-names = "core", "iface";
610 pinctrl-names = "default", "sleep";
611 pinctrl-0 = <&blsp2_uart1_default>;
612 pinctrl-1 = <&blsp2_uart1_sleep>;
613 status = "disabled";
614 };
615
616 blsp2_uart2: serial@f995e000 {
617 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
618 reg = <0xf995e000 0x1000>;
619 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
621 clock-names = "core", "iface";
622 status = "disabled";
623 };
624
625 blsp2_uart4: serial@f9960000 {
626 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
627 reg = <0xf9960000 0x1000>;
628 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
630 clock-names = "core", "iface";
631 pinctrl-names = "default";
632 pinctrl-0 = <&blsp2_uart4_default>;
633 status = "disabled";
634 };
635
636 blsp2_i2c2: i2c@f9964000 {
637 status = "disabled";
638 compatible = "qcom,i2c-qup-v2.1.1";
639 reg = <0xf9964000 0x1000>;
640 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
642 clock-names = "core", "iface";
643 pinctrl-names = "default", "sleep";
644 pinctrl-0 = <&blsp2_i2c2_default>;
645 pinctrl-1 = <&blsp2_i2c2_sleep>;
646 #address-cells = <1>;
647 #size-cells = <0>;
648 };
649
650 blsp2_i2c5: i2c@f9967000 {
651 status = "disabled";
652 compatible = "qcom,i2c-qup-v2.1.1";
653 reg = <0xf9967000 0x1000>;
654 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
656 clock-names = "core", "iface";
657 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
658 dma-names = "tx", "rx";
659 pinctrl-names = "default", "sleep";
660 pinctrl-0 = <&blsp2_i2c5_default>;
661 pinctrl-1 = <&blsp2_i2c5_sleep>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 };
665
666 blsp2_i2c6: i2c@f9968000 {
667 status = "disabled";
668 compatible = "qcom,i2c-qup-v2.1.1";
669 reg = <0xf9968000 0x1000>;
670 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
672 clock-names = "core", "iface";
673 pinctrl-names = "default", "sleep";
674 pinctrl-0 = <&blsp2_i2c6_default>;
675 pinctrl-1 = <&blsp2_i2c6_sleep>;
676 #address-cells = <1>;
677 #size-cells = <0>;
678 };
679
680 usb: usb@f9a55000 {
681 compatible = "qcom,ci-hdrc";
682 reg = <0xf9a55000 0x200>,
683 <0xf9a55200 0x200>;
684 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
686 <&gcc GCC_USB_HS_SYSTEM_CLK>;
687 clock-names = "iface", "core";
688 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
689 assigned-clock-rates = <75000000>;
690 resets = <&gcc GCC_USB_HS_BCR>;
691 reset-names = "core";
692 phy_type = "ulpi";
693 dr_mode = "otg";
694 ahb-burst-config = <0>;
695 phy-names = "usb-phy";
696 status = "disabled";
697 #reset-cells = <1>;
698
699 ulpi {
700 usb_hs1_phy: phy-0 {
701 compatible = "qcom,usb-hs-phy-msm8974",
702 "qcom,usb-hs-phy";
703 #phy-cells = <0>;
704 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
705 clock-names = "ref", "sleep";
706 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
707 reset-names = "phy", "por";
708 status = "disabled";
709 };
710
711 usb_hs2_phy: phy-1 {
712 compatible = "qcom,usb-hs-phy-msm8974",
713 "qcom,usb-hs-phy";
714 #phy-cells = <0>;
715 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
716 clock-names = "ref", "sleep";
717 resets = <&gcc GCC_USB2B_PHY_BCR>, <&usb 1>;
718 reset-names = "phy", "por";
719 status = "disabled";
720 };
721 };
722 };
723
724 rng@f9bff000 {
725 compatible = "qcom,prng";
726 reg = <0xf9bff000 0x200>;
727 clocks = <&gcc GCC_PRNG_AHB_CLK>;
728 clock-names = "core";
729 };
730
731 pronto: remoteproc@fb204000 {
732 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
733 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
734 reg-names = "ccu", "dxe", "pmu";
735
736 memory-region = <&wcnss_region>;
737
738 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
739 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
740 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
741 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
742 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
743 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
744
745 qcom,smem-states = <&wcnss_smp2p_out 0>;
746 qcom,smem-state-names = "stop";
747
748 status = "disabled";
749
750 iris {
751 compatible = "qcom,wcn3680";
752
753 clocks = <&rpmcc RPM_SMD_CXO_A2>;
754 clock-names = "xo";
755 };
756
757 smd-edge {
758 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
759
760 mboxes = <&apcs 17>;
761 qcom,smd-edge = <6>;
762
763 wcnss {
764 compatible = "qcom,wcnss";
765 qcom,smd-channels = "WCNSS_CTRL";
766 status = "disabled";
767
768 qcom,mmio = <&pronto>;
769
770 bluetooth {
771 compatible = "qcom,wcnss-bt";
772 };
773
774 wifi {
775 compatible = "qcom,wcnss-wlan";
776
777 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
778 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
779 interrupt-names = "tx", "rx";
780
781 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
782 qcom,smem-state-names = "tx-enable",
783 "tx-rings-empty";
784 };
785 };
786 };
787 };
788
789 sram@fc190000 {
790 compatible = "qcom,msm8974-rpm-stats";
791 reg = <0xfc190000 0x10000>;
792 };
793
794 etf@fc307000 {
795 compatible = "arm,coresight-tmc", "arm,primecell";
796 reg = <0xfc307000 0x1000>;
797
798 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
799 clock-names = "apb_pclk", "atclk";
800
801 out-ports {
802 port {
803 etf_out: endpoint {
804 remote-endpoint = <&replicator_in>;
805 };
806 };
807 };
808
809 in-ports {
810 port {
811 etf_in: endpoint {
812 remote-endpoint = <&merger_out>;
813 };
814 };
815 };
816 };
817
818 tpiu@fc318000 {
819 compatible = "arm,coresight-tpiu", "arm,primecell";
820 reg = <0xfc318000 0x1000>;
821
822 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
823 clock-names = "apb_pclk", "atclk";
824
825 in-ports {
826 port {
827 tpiu_in: endpoint {
828 remote-endpoint = <&replicator_out1>;
829 };
830 };
831 };
832 };
833
834 funnel@fc31a000 {
835 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
836 reg = <0xfc31a000 0x1000>;
837
838 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
839 clock-names = "apb_pclk", "atclk";
840
841 in-ports {
842 #address-cells = <1>;
843 #size-cells = <0>;
844
845 /*
846 * Not described input ports:
847 * 0 - not-connected
848 * 1 - connected trought funnel to Multimedia CPU
849 * 2 - connected to Wireless CPU
850 * 3 - not-connected
851 * 4 - not-connected
852 * 6 - not-connected
853 * 7 - connected to STM
854 */
855 port@5 {
856 reg = <5>;
857 funnel1_in5: endpoint {
858 remote-endpoint = <&kpss_out>;
859 };
860 };
861 };
862
863 out-ports {
864 port {
865 funnel1_out: endpoint {
866 remote-endpoint = <&merger_in1>;
867 };
868 };
869 };
870 };
871
872 funnel@fc31b000 {
873 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
874 reg = <0xfc31b000 0x1000>;
875
876 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
877 clock-names = "apb_pclk", "atclk";
878
879 in-ports {
880 #address-cells = <1>;
881 #size-cells = <0>;
882
883 /*
884 * Not described input ports:
885 * 0 - connected trought funnel to Audio, Modem and
886 * Resource and Power Manager CPU's
887 * 2...7 - not-connected
888 */
889 port@1 {
890 reg = <1>;
891 merger_in1: endpoint {
892 remote-endpoint = <&funnel1_out>;
893 };
894 };
895 };
896
897 out-ports {
898 port {
899 merger_out: endpoint {
900 remote-endpoint = <&etf_in>;
901 };
902 };
903 };
904 };
905
906 replicator@fc31c000 {
907 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
908 reg = <0xfc31c000 0x1000>;
909
910 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
911 clock-names = "apb_pclk", "atclk";
912
913 out-ports {
914 #address-cells = <1>;
915 #size-cells = <0>;
916
917 port@0 {
918 reg = <0>;
919 replicator_out0: endpoint {
920 remote-endpoint = <&etr_in>;
921 };
922 };
923 port@1 {
924 reg = <1>;
925 replicator_out1: endpoint {
926 remote-endpoint = <&tpiu_in>;
927 };
928 };
929 };
930
931 in-ports {
932 port {
933 replicator_in: endpoint {
934 remote-endpoint = <&etf_out>;
935 };
936 };
937 };
938 };
939
940 etr@fc322000 {
941 compatible = "arm,coresight-tmc", "arm,primecell";
942 reg = <0xfc322000 0x1000>;
943
944 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
945 clock-names = "apb_pclk", "atclk";
946
947 in-ports {
948 port {
949 etr_in: endpoint {
950 remote-endpoint = <&replicator_out0>;
951 };
952 };
953 };
954 };
955
956 etm@fc33c000 {
957 compatible = "arm,coresight-etm4x", "arm,primecell";
958 reg = <0xfc33c000 0x1000>;
959
960 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
961 clock-names = "apb_pclk", "atclk";
962
963 cpu = <&CPU0>;
964
965 out-ports {
966 port {
967 etm0_out: endpoint {
968 remote-endpoint = <&kpss_in0>;
969 };
970 };
971 };
972 };
973
974 etm@fc33d000 {
975 compatible = "arm,coresight-etm4x", "arm,primecell";
976 reg = <0xfc33d000 0x1000>;
977
978 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
979 clock-names = "apb_pclk", "atclk";
980
981 cpu = <&CPU1>;
982
983 out-ports {
984 port {
985 etm1_out: endpoint {
986 remote-endpoint = <&kpss_in1>;
987 };
988 };
989 };
990 };
991
992 etm@fc33e000 {
993 compatible = "arm,coresight-etm4x", "arm,primecell";
994 reg = <0xfc33e000 0x1000>;
995
996 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
997 clock-names = "apb_pclk", "atclk";
998
999 cpu = <&CPU2>;
1000
1001 out-ports {
1002 port {
1003 etm2_out: endpoint {
1004 remote-endpoint = <&kpss_in2>;
1005 };
1006 };
1007 };
1008 };
1009
1010 etm@fc33f000 {
1011 compatible = "arm,coresight-etm4x", "arm,primecell";
1012 reg = <0xfc33f000 0x1000>;
1013
1014 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1015 clock-names = "apb_pclk", "atclk";
1016
1017 cpu = <&CPU3>;
1018
1019 out-ports {
1020 port {
1021 etm3_out: endpoint {
1022 remote-endpoint = <&kpss_in3>;
1023 };
1024 };
1025 };
1026 };
1027
1028 /* KPSS funnel, only 4 inputs are used */
1029 funnel@fc345000 {
1030 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1031 reg = <0xfc345000 0x1000>;
1032
1033 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1034 clock-names = "apb_pclk", "atclk";
1035
1036 in-ports {
1037 #address-cells = <1>;
1038 #size-cells = <0>;
1039
1040 port@0 {
1041 reg = <0>;
1042 kpss_in0: endpoint {
1043 remote-endpoint = <&etm0_out>;
1044 };
1045 };
1046 port@1 {
1047 reg = <1>;
1048 kpss_in1: endpoint {
1049 remote-endpoint = <&etm1_out>;
1050 };
1051 };
1052 port@2 {
1053 reg = <2>;
1054 kpss_in2: endpoint {
1055 remote-endpoint = <&etm2_out>;
1056 };
1057 };
1058 port@3 {
1059 reg = <3>;
1060 kpss_in3: endpoint {
1061 remote-endpoint = <&etm3_out>;
1062 };
1063 };
1064 };
1065
1066 out-ports {
1067 port {
1068 kpss_out: endpoint {
1069 remote-endpoint = <&funnel1_in5>;
1070 };
1071 };
1072 };
1073 };
1074
1075 bimc: interconnect@fc380000 {
1076 reg = <0xfc380000 0x6a000>;
1077 compatible = "qcom,msm8974-bimc";
1078 #interconnect-cells = <1>;
1079 clock-names = "bus", "bus_a";
1080 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1081 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1082 };
1083
1084 gcc: clock-controller@fc400000 {
1085 compatible = "qcom,gcc-msm8974";
1086 #clock-cells = <1>;
1087 #reset-cells = <1>;
1088 #power-domain-cells = <1>;
1089 reg = <0xfc400000 0x4000>;
1090
1091 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1092 <&sleep_clk>;
1093 clock-names = "xo",
1094 "sleep_clk";
1095 };
1096
1097 rpm_msg_ram: sram@fc428000 {
1098 compatible = "qcom,rpm-msg-ram";
1099 reg = <0xfc428000 0x4000>;
1100
1101 #address-cells = <1>;
1102 #size-cells = <1>;
1103 ranges = <0 0xfc428000 0x4000>;
1104
1105 apss_master_stats: sram@150 {
1106 reg = <0x150 0x14>;
1107 };
1108
1109 mpss_master_stats: sram@b50 {
1110 reg = <0xb50 0x14>;
1111 };
1112
1113 lpss_master_stats: sram@1550 {
1114 reg = <0x1550 0x14>;
1115 };
1116
1117 pronto_master_stats: sram@1f50 {
1118 reg = <0x1f50 0x14>;
1119 };
1120 };
1121
1122 snoc: interconnect@fc460000 {
1123 reg = <0xfc460000 0x4000>;
1124 compatible = "qcom,msm8974-snoc";
1125 #interconnect-cells = <1>;
1126 clock-names = "bus", "bus_a";
1127 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1128 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1129 };
1130
1131 pnoc: interconnect@fc468000 {
1132 reg = <0xfc468000 0x4000>;
1133 compatible = "qcom,msm8974-pnoc";
1134 #interconnect-cells = <1>;
1135 clock-names = "bus", "bus_a";
1136 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1137 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1138 };
1139
1140 ocmemnoc: interconnect@fc470000 {
1141 reg = <0xfc470000 0x4000>;
1142 compatible = "qcom,msm8974-ocmemnoc";
1143 #interconnect-cells = <1>;
1144 clock-names = "bus", "bus_a";
1145 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1146 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1147 };
1148
1149 mmssnoc: interconnect@fc478000 {
1150 reg = <0xfc478000 0x4000>;
1151 compatible = "qcom,msm8974-mmssnoc";
1152 #interconnect-cells = <1>;
1153 clock-names = "bus", "bus_a";
1154 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1155 <&mmcc MMSS_S0_AXI_CLK>;
1156 };
1157
1158 cnoc: interconnect@fc480000 {
1159 reg = <0xfc480000 0x4000>;
1160 compatible = "qcom,msm8974-cnoc";
1161 #interconnect-cells = <1>;
1162 clock-names = "bus", "bus_a";
1163 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1164 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1165 };
1166
1167 tsens: thermal-sensor@fc4a9000 {
1168 compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1";
1169 reg = <0xfc4a9000 0x1000>, /* TM */
1170 <0xfc4a8000 0x1000>; /* SROT */
1171 nvmem-cells = <&tsens_mode>,
1172 <&tsens_base1>, <&tsens_base2>,
1173 <&tsens_use_backup>,
1174 <&tsens_mode_backup>,
1175 <&tsens_base1_backup>, <&tsens_base2_backup>,
1176 <&tsens_s0_p1>, <&tsens_s0_p2>,
1177 <&tsens_s1_p1>, <&tsens_s1_p2>,
1178 <&tsens_s2_p1>, <&tsens_s2_p2>,
1179 <&tsens_s3_p1>, <&tsens_s3_p2>,
1180 <&tsens_s4_p1>, <&tsens_s4_p2>,
1181 <&tsens_s5_p1>, <&tsens_s5_p2>,
1182 <&tsens_s6_p1>, <&tsens_s6_p2>,
1183 <&tsens_s7_p1>, <&tsens_s7_p2>,
1184 <&tsens_s8_p1>, <&tsens_s8_p2>,
1185 <&tsens_s9_p1>, <&tsens_s9_p2>,
1186 <&tsens_s10_p1>, <&tsens_s10_p2>,
1187 <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>,
1188 <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>,
1189 <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>,
1190 <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>,
1191 <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>,
1192 <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>,
1193 <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>,
1194 <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>,
1195 <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>,
1196 <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>,
1197 <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>;
1198 nvmem-cell-names = "mode",
1199 "base1", "base2",
1200 "use_backup",
1201 "mode_backup",
1202 "base1_backup", "base2_backup",
1203 "s0_p1", "s0_p2",
1204 "s1_p1", "s1_p2",
1205 "s2_p1", "s2_p2",
1206 "s3_p1", "s3_p2",
1207 "s4_p1", "s4_p2",
1208 "s5_p1", "s5_p2",
1209 "s6_p1", "s6_p2",
1210 "s7_p1", "s7_p2",
1211 "s8_p1", "s8_p2",
1212 "s9_p1", "s9_p2",
1213 "s10_p1", "s10_p2",
1214 "s0_p1_backup", "s0_p2_backup",
1215 "s1_p1_backup", "s1_p2_backup",
1216 "s2_p1_backup", "s2_p2_backup",
1217 "s3_p1_backup", "s3_p2_backup",
1218 "s4_p1_backup", "s4_p2_backup",
1219 "s5_p1_backup", "s5_p2_backup",
1220 "s6_p1_backup", "s6_p2_backup",
1221 "s7_p1_backup", "s7_p2_backup",
1222 "s8_p1_backup", "s8_p2_backup",
1223 "s9_p1_backup", "s9_p2_backup",
1224 "s10_p1_backup", "s10_p2_backup";
1225 #qcom,sensors = <11>;
1226 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1227 interrupt-names = "uplow";
1228 #thermal-sensor-cells = <1>;
1229 };
1230
1231 restart@fc4ab000 {
1232 compatible = "qcom,pshold";
1233 reg = <0xfc4ab000 0x4>;
1234 };
1235
1236 qfprom: efuse@fc4bc000 {
1237 compatible = "qcom,msm8974-qfprom", "qcom,qfprom";
1238 reg = <0xfc4bc000 0x2100>;
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241
1242 tsens_base1: base1@d0 {
1243 reg = <0xd0 0x1>;
1244 bits = <0 8>;
1245 };
1246
1247 tsens_s0_p1: s0-p1@d1 {
1248 reg = <0xd1 0x1>;
1249 bits = <0 6>;
1250 };
1251
1252 tsens_s1_p1: s1-p1@d2 {
1253 reg = <0xd1 0x2>;
1254 bits = <6 6>;
1255 };
1256
1257 tsens_s2_p1: s2-p1@d2 {
1258 reg = <0xd2 0x2>;
1259 bits = <4 6>;
1260 };
1261
1262 tsens_s3_p1: s3-p1@d3 {
1263 reg = <0xd3 0x1>;
1264 bits = <2 6>;
1265 };
1266
1267 tsens_s4_p1: s4-p1@d4 {
1268 reg = <0xd4 0x1>;
1269 bits = <0 6>;
1270 };
1271
1272 tsens_s5_p1: s5-p1@d4 {
1273 reg = <0xd4 0x2>;
1274 bits = <6 6>;
1275 };
1276
1277 tsens_s6_p1: s6-p1@d5 {
1278 reg = <0xd5 0x2>;
1279 bits = <4 6>;
1280 };
1281
1282 tsens_s7_p1: s7-p1@d6 {
1283 reg = <0xd6 0x1>;
1284 bits = <2 6>;
1285 };
1286
1287 tsens_s8_p1: s8-p1@d7 {
1288 reg = <0xd7 0x1>;
1289 bits = <0 6>;
1290 };
1291
1292 tsens_mode: mode@d7 {
1293 reg = <0xd7 0x1>;
1294 bits = <6 2>;
1295 };
1296
1297 tsens_s9_p1: s9-p1@d8 {
1298 reg = <0xd8 0x1>;
1299 bits = <0 6>;
1300 };
1301
1302 tsens_s10_p1: s10_p1@d8 {
1303 reg = <0xd8 0x2>;
1304 bits = <6 6>;
1305 };
1306
1307 tsens_base2: base2@d9 {
1308 reg = <0xd9 0x2>;
1309 bits = <4 8>;
1310 };
1311
1312 tsens_s0_p2: s0-p2@da {
1313 reg = <0xda 0x2>;
1314 bits = <4 6>;
1315 };
1316
1317 tsens_s1_p2: s1-p2@db {
1318 reg = <0xdb 0x1>;
1319 bits = <2 6>;
1320 };
1321
1322 tsens_s2_p2: s2-p2@dc {
1323 reg = <0xdc 0x1>;
1324 bits = <0 6>;
1325 };
1326
1327 tsens_s3_p2: s3-p2@dc {
1328 reg = <0xdc 0x2>;
1329 bits = <6 6>;
1330 };
1331
1332 tsens_s4_p2: s4-p2@dd {
1333 reg = <0xdd 0x2>;
1334 bits = <4 6>;
1335 };
1336
1337 tsens_s5_p2: s5-p2@de {
1338 reg = <0xde 0x2>;
1339 bits = <2 6>;
1340 };
1341
1342 tsens_s6_p2: s6-p2@df {
1343 reg = <0xdf 0x1>;
1344 bits = <0 6>;
1345 };
1346
1347 tsens_s7_p2: s7-p2@e0 {
1348 reg = <0xe0 0x1>;
1349 bits = <0 6>;
1350 };
1351
1352 tsens_s8_p2: s8-p2@e0 {
1353 reg = <0xe0 0x2>;
1354 bits = <6 6>;
1355 };
1356
1357 tsens_s9_p2: s9-p2@e1 {
1358 reg = <0xe1 0x2>;
1359 bits = <4 6>;
1360 };
1361
1362 tsens_s10_p2: s10_p2@e2 {
1363 reg = <0xe2 0x2>;
1364 bits = <2 6>;
1365 };
1366
1367 tsens_s5_p2_backup: s5-p2_backup@e3 {
1368 reg = <0xe3 0x2>;
1369 bits = <0 6>;
1370 };
1371
1372 tsens_mode_backup: mode_backup@e3 {
1373 reg = <0xe3 0x1>;
1374 bits = <6 2>;
1375 };
1376
1377 tsens_s6_p2_backup: s6-p2_backup@e4 {
1378 reg = <0xe4 0x1>;
1379 bits = <0 6>;
1380 };
1381
1382 tsens_s7_p2_backup: s7-p2_backup@e4 {
1383 reg = <0xe4 0x2>;
1384 bits = <6 6>;
1385 };
1386
1387 tsens_s8_p2_backup: s8-p2_backup@e5 {
1388 reg = <0xe5 0x2>;
1389 bits = <4 6>;
1390 };
1391
1392 tsens_s9_p2_backup: s9-p2_backup@e6 {
1393 reg = <0xe6 0x2>;
1394 bits = <2 6>;
1395 };
1396
1397 tsens_s10_p2_backup: s10_p2_backup@e7 {
1398 reg = <0xe7 0x1>;
1399 bits = <0 6>;
1400 };
1401
1402 tsens_base1_backup: base1_backup@440 {
1403 reg = <0x440 0x1>;
1404 bits = <0 8>;
1405 };
1406
1407 tsens_s0_p1_backup: s0-p1_backup@441 {
1408 reg = <0x441 0x1>;
1409 bits = <0 6>;
1410 };
1411
1412 tsens_s1_p1_backup: s1-p1_backup@442 {
1413 reg = <0x441 0x2>;
1414 bits = <6 6>;
1415 };
1416
1417 tsens_s2_p1_backup: s2-p1_backup@442 {
1418 reg = <0x442 0x2>;
1419 bits = <4 6>;
1420 };
1421
1422 tsens_s3_p1_backup: s3-p1_backup@443 {
1423 reg = <0x443 0x1>;
1424 bits = <2 6>;
1425 };
1426
1427 tsens_s4_p1_backup: s4-p1_backup@444 {
1428 reg = <0x444 0x1>;
1429 bits = <0 6>;
1430 };
1431
1432 tsens_s5_p1_backup: s5-p1_backup@444 {
1433 reg = <0x444 0x2>;
1434 bits = <6 6>;
1435 };
1436
1437 tsens_s6_p1_backup: s6-p1_backup@445 {
1438 reg = <0x445 0x2>;
1439 bits = <4 6>;
1440 };
1441
1442 tsens_s7_p1_backup: s7-p1_backup@446 {
1443 reg = <0x446 0x1>;
1444 bits = <2 6>;
1445 };
1446
1447 tsens_use_backup: use_backup@447 {
1448 reg = <0x447 0x1>;
1449 bits = <5 3>;
1450 };
1451
1452 tsens_s8_p1_backup: s8-p1_backup@448 {
1453 reg = <0x448 0x1>;
1454 bits = <0 6>;
1455 };
1456
1457 tsens_s9_p1_backup: s9-p1_backup@448 {
1458 reg = <0x448 0x2>;
1459 bits = <6 6>;
1460 };
1461
1462 tsens_s10_p1_backup: s10_p1_backup@449 {
1463 reg = <0x449 0x2>;
1464 bits = <4 6>;
1465 };
1466
1467 tsens_base2_backup: base2_backup@44a {
1468 reg = <0x44a 0x2>;
1469 bits = <2 8>;
1470 };
1471
1472 tsens_s0_p2_backup: s0-p2_backup@44b {
1473 reg = <0x44b 0x3>;
1474 bits = <2 6>;
1475 };
1476
1477 tsens_s1_p2_backup: s1-p2_backup@44c {
1478 reg = <0x44c 0x1>;
1479 bits = <0 6>;
1480 };
1481
1482 tsens_s2_p2_backup: s2-p2_backup@44c {
1483 reg = <0x44c 0x2>;
1484 bits = <6 6>;
1485 };
1486
1487 tsens_s3_p2_backup: s3-p2_backup@44d {
1488 reg = <0x44d 0x2>;
1489 bits = <4 6>;
1490 };
1491
1492 tsens_s4_p2_backup: s4-p2_backup@44e {
1493 reg = <0x44e 0x1>;
1494 bits = <2 6>;
1495 };
1496 };
1497
1498 spmi_bus: spmi@fc4cf000 {
1499 compatible = "qcom,spmi-pmic-arb";
1500 reg-names = "core", "intr", "cnfg";
1501 reg = <0xfc4cf000 0x1000>,
1502 <0xfc4cb000 0x1000>,
1503 <0xfc4ca000 0x1000>;
1504 interrupt-names = "periph_irq";
1505 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1506 qcom,ee = <0>;
1507 qcom,channel = <0>;
1508 #address-cells = <2>;
1509 #size-cells = <0>;
1510 interrupt-controller;
1511 #interrupt-cells = <4>;
1512 };
1513
1514 bam_dmux_dma: dma-controller@fc834000 {
1515 compatible = "qcom,bam-v1.4.0";
1516 reg = <0xfc834000 0x7000>;
1517 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1518 #dma-cells = <1>;
1519 qcom,ee = <0>;
1520
1521 num-channels = <6>;
1522 qcom,num-ees = <1>;
1523 qcom,powered-remotely;
1524 };
1525
1526 remoteproc_mss: remoteproc@fc880000 {
1527 compatible = "qcom,msm8974-mss-pil";
1528 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1529 reg-names = "qdsp6", "rmb";
1530
1531 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1532 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1533 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1534 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1535 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1536 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1537
1538 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1539 <&gcc GCC_MSS_CFG_AHB_CLK>,
1540 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1541 <&xo_board>;
1542 clock-names = "iface", "bus", "mem", "xo";
1543
1544 resets = <&gcc GCC_MSS_RESTART>;
1545 reset-names = "mss_restart";
1546
1547 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1548
1549 qcom,smem-states = <&modem_smp2p_out 0>;
1550 qcom,smem-state-names = "stop";
1551
1552 status = "disabled";
1553
1554 mba {
1555 memory-region = <&mba_region>;
1556 };
1557
1558 mpss {
1559 memory-region = <&mpss_region>;
1560 };
1561
1562 bam_dmux: bam-dmux {
1563 compatible = "qcom,bam-dmux";
1564
1565 interrupt-parent = <&modem_smsm>;
1566 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1567 interrupt-names = "pc", "pc-ack";
1568
1569 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1570 qcom,smem-state-names = "pc", "pc-ack";
1571
1572 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1573 dma-names = "tx", "rx";
1574 };
1575
1576 smd-edge {
1577 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1578
1579 mboxes = <&apcs 12>;
1580 qcom,smd-edge = <0>;
1581
1582 label = "modem";
1583 };
1584 };
1585
1586 tcsr_mutex: hwlock@fd484000 {
1587 compatible = "qcom,msm8974-tcsr-mutex", "qcom,tcsr-mutex", "syscon";
1588 reg = <0xfd484000 0x2000>;
1589 #hwlock-cells = <1>;
1590 };
1591
1592 tcsr: syscon@fd4a0000 {
1593 compatible = "qcom,tcsr-msm8974", "syscon";
1594 reg = <0xfd4a0000 0x10000>;
1595 };
1596
1597 tlmm: pinctrl@fd510000 {
1598 compatible = "qcom,msm8974-pinctrl";
1599 reg = <0xfd510000 0x4000>;
1600 gpio-controller;
1601 gpio-ranges = <&tlmm 0 0 146>;
1602 #gpio-cells = <2>;
1603 interrupt-controller;
1604 #interrupt-cells = <2>;
1605 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1606
1607 sdc1_off: sdc1-off-state {
1608 clk-pins {
1609 pins = "sdc1_clk";
1610 bias-disable;
1611 drive-strength = <2>;
1612 };
1613
1614 cmd-pins {
1615 pins = "sdc1_cmd";
1616 bias-pull-up;
1617 drive-strength = <2>;
1618 };
1619
1620 data-pins {
1621 pins = "sdc1_data";
1622 bias-pull-up;
1623 drive-strength = <2>;
1624 };
1625 };
1626
1627 sdc2_off: sdc2-off-state {
1628 clk-pins {
1629 pins = "sdc2_clk";
1630 bias-disable;
1631 drive-strength = <2>;
1632 };
1633
1634 cmd-pins {
1635 pins = "sdc2_cmd";
1636 bias-pull-up;
1637 drive-strength = <2>;
1638 };
1639
1640 data-pins {
1641 pins = "sdc2_data";
1642 bias-pull-up;
1643 drive-strength = <2>;
1644 };
1645 };
1646
1647 blsp1_uart2_default: blsp1-uart2-default-state {
1648 rx-pins {
1649 pins = "gpio5";
1650 function = "blsp_uart2";
1651 drive-strength = <2>;
1652 bias-pull-up;
1653 };
1654
1655 tx-pins {
1656 pins = "gpio4";
1657 function = "blsp_uart2";
1658 drive-strength = <4>;
1659 bias-disable;
1660 };
1661 };
1662
1663 blsp2_uart1_default: blsp2-uart1-default-state {
1664 tx-rts-pins {
1665 pins = "gpio41", "gpio44";
1666 function = "blsp_uart7";
1667 drive-strength = <2>;
1668 bias-disable;
1669 };
1670
1671 rx-cts-pins {
1672 pins = "gpio42", "gpio43";
1673 function = "blsp_uart7";
1674 drive-strength = <2>;
1675 bias-pull-up;
1676 };
1677 };
1678
1679 blsp2_uart1_sleep: blsp2-uart1-sleep-state {
1680 pins = "gpio41", "gpio42", "gpio43", "gpio44";
1681 function = "gpio";
1682 drive-strength = <2>;
1683 bias-pull-down;
1684 };
1685
1686 blsp2_uart4_default: blsp2-uart4-default-state {
1687 tx-rts-pins {
1688 pins = "gpio53", "gpio56";
1689 function = "blsp_uart10";
1690 drive-strength = <2>;
1691 bias-disable;
1692 };
1693
1694 rx-cts-pins {
1695 pins = "gpio54", "gpio55";
1696 function = "blsp_uart10";
1697 drive-strength = <2>;
1698 bias-pull-up;
1699 };
1700 };
1701
1702 blsp1_i2c1_default: blsp1-i2c1-default-state {
1703 pins = "gpio2", "gpio3";
1704 function = "blsp_i2c1";
1705 drive-strength = <2>;
1706 bias-disable;
1707 };
1708
1709 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state {
1710 pins = "gpio2", "gpio3";
1711 function = "blsp_i2c1";
1712 drive-strength = <2>;
1713 bias-pull-up;
1714 };
1715
1716 blsp1_i2c2_default: blsp1-i2c2-default-state {
1717 pins = "gpio6", "gpio7";
1718 function = "blsp_i2c2";
1719 drive-strength = <2>;
1720 bias-disable;
1721 };
1722
1723 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
1724 pins = "gpio6", "gpio7";
1725 function = "blsp_i2c2";
1726 drive-strength = <2>;
1727 bias-pull-up;
1728 };
1729
1730 blsp1_i2c3_default: blsp1-i2c3-default-state {
1731 pins = "gpio10", "gpio11";
1732 function = "blsp_i2c3";
1733 drive-strength = <2>;
1734 bias-disable;
1735 };
1736
1737 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1738 pins = "gpio10", "gpio11";
1739 function = "blsp_i2c3";
1740 drive-strength = <2>;
1741 bias-pull-up;
1742 };
1743
1744 /* BLSP1_I2C4 info is missing */
1745
1746 /* BLSP1_I2C5 info is missing */
1747
1748 blsp1_i2c6_default: blsp1-i2c6-default-state {
1749 pins = "gpio29", "gpio30";
1750 function = "blsp_i2c6";
1751 drive-strength = <2>;
1752 bias-disable;
1753 };
1754
1755 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1756 pins = "gpio29", "gpio30";
1757 function = "blsp_i2c6";
1758 drive-strength = <2>;
1759 bias-pull-up;
1760 };
1761 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1762
1763 /* BLSP2_I2C1 info is missing */
1764
1765 blsp2_i2c2_default: blsp2-i2c2-default-state {
1766 pins = "gpio47", "gpio48";
1767 function = "blsp_i2c8";
1768 drive-strength = <2>;
1769 bias-disable;
1770 };
1771
1772 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1773 pins = "gpio47", "gpio48";
1774 function = "blsp_i2c8";
1775 drive-strength = <2>;
1776 bias-pull-up;
1777 };
1778
1779 /* BLSP2_I2C3 info is missing */
1780
1781 /* BLSP2_I2C4 info is missing */
1782
1783 blsp2_i2c5_default: blsp2-i2c5-default-state {
1784 pins = "gpio83", "gpio84";
1785 function = "blsp_i2c11";
1786 drive-strength = <2>;
1787 bias-disable;
1788 };
1789
1790 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1791 pins = "gpio83", "gpio84";
1792 function = "blsp_i2c11";
1793 drive-strength = <2>;
1794 bias-pull-up;
1795 };
1796
1797 blsp2_i2c6_default: blsp2-i2c6-default-state {
1798 pins = "gpio87", "gpio88";
1799 function = "blsp_i2c12";
1800 drive-strength = <2>;
1801 bias-disable;
1802 };
1803
1804 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1805 pins = "gpio87", "gpio88";
1806 function = "blsp_i2c12";
1807 drive-strength = <2>;
1808 bias-pull-up;
1809 };
1810
1811 cci_default: cci-default-state {
1812 cci_i2c0_default: cci-i2c0-default-pins {
1813 pins = "gpio19", "gpio20";
1814 function = "cci_i2c0";
1815 drive-strength = <2>;
1816 bias-disable;
1817 };
1818
1819 cci_i2c1_default: cci-i2c1-default-pins {
1820 pins = "gpio21", "gpio22";
1821 function = "cci_i2c1";
1822 drive-strength = <2>;
1823 bias-disable;
1824 };
1825 };
1826
1827 cci_sleep: cci-sleep-state {
1828 cci_i2c0_sleep: cci-i2c0-sleep-pins {
1829 pins = "gpio19", "gpio20";
1830 function = "gpio";
1831 drive-strength = <2>;
1832 bias-disable;
1833 };
1834
1835 cci_i2c1_sleep: cci-i2c1-sleep-pins {
1836 pins = "gpio21", "gpio22";
1837 function = "gpio";
1838 drive-strength = <2>;
1839 bias-disable;
1840 };
1841 };
1842
1843 spi8_default: spi8_default-state {
1844 mosi-pins {
1845 pins = "gpio45";
1846 function = "blsp_spi8";
1847 };
1848 miso-pins {
1849 pins = "gpio46";
1850 function = "blsp_spi8";
1851 };
1852 cs-pins {
1853 pins = "gpio47";
1854 function = "blsp_spi8";
1855 };
1856 clk-pins {
1857 pins = "gpio48";
1858 function = "blsp_spi8";
1859 };
1860 };
1861 };
1862
1863 mmcc: clock-controller@fd8c0000 {
1864 compatible = "qcom,mmcc-msm8974";
1865 #clock-cells = <1>;
1866 #reset-cells = <1>;
1867 #power-domain-cells = <1>;
1868 reg = <0xfd8c0000 0x6000>;
1869 clocks = <&xo_board>,
1870 <&gcc GCC_MMSS_GPLL0_CLK_SRC>,
1871 <&gcc GPLL0_VOTE>,
1872 <&gcc GPLL1_VOTE>,
1873 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1874 <&mdss_dsi0_phy 1>,
1875 <&mdss_dsi0_phy 0>,
1876 <&mdss_dsi1_phy 1>,
1877 <&mdss_dsi1_phy 0>,
1878 <0>,
1879 <0>,
1880 <0>;
1881 clock-names = "xo",
1882 "mmss_gpll0_vote",
1883 "gpll0_vote",
1884 "gpll1_vote",
1885 "gfx3d_clk_src",
1886 "dsi0pll",
1887 "dsi0pllbyte",
1888 "dsi1pll",
1889 "dsi1pllbyte",
1890 "hdmipll",
1891 "edp_link_clk",
1892 "edp_vco_div";
1893 };
1894
1895 mdss: display-subsystem@fd900000 {
1896 compatible = "qcom,mdss";
1897 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1898 reg-names = "mdss_phys", "vbif_phys";
1899
1900 power-domains = <&mmcc MDSS_GDSC>;
1901
1902 clocks = <&mmcc MDSS_AHB_CLK>,
1903 <&mmcc MDSS_AXI_CLK>,
1904 <&mmcc MDSS_VSYNC_CLK>;
1905 clock-names = "iface", "bus", "vsync";
1906
1907 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1908
1909 interrupt-controller;
1910 #interrupt-cells = <1>;
1911
1912 status = "disabled";
1913
1914 #address-cells = <1>;
1915 #size-cells = <1>;
1916 ranges;
1917
1918 mdp: display-controller@fd900000 {
1919 compatible = "qcom,msm8974-mdp5", "qcom,mdp5";
1920 reg = <0xfd900100 0x22000>;
1921 reg-names = "mdp_phys";
1922
1923 interrupt-parent = <&mdss>;
1924 interrupts = <0>;
1925
1926 clocks = <&mmcc MDSS_AHB_CLK>,
1927 <&mmcc MDSS_AXI_CLK>,
1928 <&mmcc MDSS_MDP_CLK>,
1929 <&mmcc MDSS_VSYNC_CLK>;
1930 clock-names = "iface", "bus", "core", "vsync";
1931
1932 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1933 interconnect-names = "mdp0-mem";
1934
1935 ports {
1936 #address-cells = <1>;
1937 #size-cells = <0>;
1938
1939 port@0 {
1940 reg = <0>;
1941 mdp5_intf1_out: endpoint {
1942 remote-endpoint = <&mdss_dsi0_in>;
1943 };
1944 };
1945
1946 port@1 {
1947 reg = <1>;
1948 mdp5_intf2_out: endpoint {
1949 remote-endpoint = <&mdss_dsi1_in>;
1950 };
1951 };
1952 };
1953 };
1954
1955 mdss_dsi0: dsi@fd922800 {
1956 compatible = "qcom,msm8974-dsi-ctrl",
1957 "qcom,mdss-dsi-ctrl";
1958 reg = <0xfd922800 0x1f8>;
1959 reg-names = "dsi_ctrl";
1960
1961 interrupt-parent = <&mdss>;
1962 interrupts = <4>;
1963
1964 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1965 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1966
1967 clocks = <&mmcc MDSS_MDP_CLK>,
1968 <&mmcc MDSS_AHB_CLK>,
1969 <&mmcc MDSS_AXI_CLK>,
1970 <&mmcc MDSS_BYTE0_CLK>,
1971 <&mmcc MDSS_PCLK0_CLK>,
1972 <&mmcc MDSS_ESC0_CLK>,
1973 <&mmcc MMSS_MISC_AHB_CLK>;
1974 clock-names = "mdp_core",
1975 "iface",
1976 "bus",
1977 "byte",
1978 "pixel",
1979 "core",
1980 "core_mmss";
1981
1982 phys = <&mdss_dsi0_phy>;
1983
1984 status = "disabled";
1985
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1988
1989 ports {
1990 #address-cells = <1>;
1991 #size-cells = <0>;
1992
1993 port@0 {
1994 reg = <0>;
1995 mdss_dsi0_in: endpoint {
1996 remote-endpoint = <&mdp5_intf1_out>;
1997 };
1998 };
1999
2000 port@1 {
2001 reg = <1>;
2002 mdss_dsi0_out: endpoint {
2003 };
2004 };
2005 };
2006 };
2007
2008 mdss_dsi0_phy: phy@fd922a00 {
2009 compatible = "qcom,dsi-phy-28nm-hpm";
2010 reg = <0xfd922a00 0xd4>,
2011 <0xfd922b00 0x280>,
2012 <0xfd922d80 0x30>;
2013 reg-names = "dsi_pll",
2014 "dsi_phy",
2015 "dsi_phy_regulator";
2016
2017 #clock-cells = <1>;
2018 #phy-cells = <0>;
2019
2020 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2021 clock-names = "iface", "ref";
2022
2023 status = "disabled";
2024 };
2025
2026 mdss_dsi1: dsi@fd922e00 {
2027 compatible = "qcom,msm8974-dsi-ctrl",
2028 "qcom,mdss-dsi-ctrl";
2029 reg = <0xfd922e00 0x1f8>;
2030 reg-names = "dsi_ctrl";
2031
2032 interrupt-parent = <&mdss>;
2033 interrupts = <4>;
2034
2035 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
2036 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2037
2038 clocks = <&mmcc MDSS_MDP_CLK>,
2039 <&mmcc MDSS_AHB_CLK>,
2040 <&mmcc MDSS_AXI_CLK>,
2041 <&mmcc MDSS_BYTE1_CLK>,
2042 <&mmcc MDSS_PCLK1_CLK>,
2043 <&mmcc MDSS_ESC1_CLK>,
2044 <&mmcc MMSS_MISC_AHB_CLK>;
2045 clock-names = "mdp_core",
2046 "iface",
2047 "bus",
2048 "byte",
2049 "pixel",
2050 "core",
2051 "core_mmss";
2052
2053 phys = <&mdss_dsi1_phy>;
2054
2055 status = "disabled";
2056
2057 #address-cells = <1>;
2058 #size-cells = <0>;
2059
2060 ports {
2061 #address-cells = <1>;
2062 #size-cells = <0>;
2063
2064 port@0 {
2065 reg = <0>;
2066 mdss_dsi1_in: endpoint {
2067 remote-endpoint = <&mdp5_intf2_out>;
2068 };
2069 };
2070
2071 port@1 {
2072 reg = <1>;
2073 mdss_dsi1_out: endpoint {
2074 };
2075 };
2076 };
2077 };
2078
2079 mdss_dsi1_phy: phy@fd923000 {
2080 compatible = "qcom,dsi-phy-28nm-hpm";
2081 reg = <0xfd923000 0xd4>,
2082 <0xfd923100 0x280>,
2083 <0xfd923380 0x30>;
2084 reg-names = "dsi_pll",
2085 "dsi_phy",
2086 "dsi_phy_regulator";
2087
2088 #clock-cells = <1>;
2089 #phy-cells = <0>;
2090
2091 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
2092 clock-names = "iface", "ref";
2093
2094 status = "disabled";
2095 };
2096 };
2097
2098 cci: cci@fda0c000 {
2099 compatible = "qcom,msm8974-cci";
2100 #address-cells = <1>;
2101 #size-cells = <0>;
2102 reg = <0xfda0c000 0x1000>;
2103 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
2104 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2105 <&mmcc CAMSS_CCI_CCI_AHB_CLK>,
2106 <&mmcc CAMSS_CCI_CCI_CLK>;
2107 clock-names = "camss_top_ahb",
2108 "cci_ahb",
2109 "cci";
2110
2111 pinctrl-names = "default", "sleep";
2112 pinctrl-0 = <&cci_default>;
2113 pinctrl-1 = <&cci_sleep>;
2114
2115 status = "disabled";
2116
2117 cci_i2c0: i2c-bus@0 {
2118 reg = <0>;
2119 clock-frequency = <100000>;
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2122 };
2123
2124 cci_i2c1: i2c-bus@1 {
2125 reg = <1>;
2126 clock-frequency = <100000>;
2127 #address-cells = <1>;
2128 #size-cells = <0>;
2129 };
2130 };
2131
2132 gpu: gpu@fdb00000 {
2133 compatible = "qcom,adreno-330.1", "qcom,adreno";
2134 reg = <0xfdb00000 0x10000>;
2135 reg-names = "kgsl_3d0_reg_memory";
2136
2137 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2138 interrupt-names = "kgsl_3d0_irq";
2139
2140 clocks = <&mmcc OXILI_GFX3D_CLK>,
2141 <&mmcc OXILICX_AHB_CLK>,
2142 <&mmcc OXILICX_AXI_CLK>;
2143 clock-names = "core", "iface", "mem_iface";
2144
2145 sram = <&gmu_sram>;
2146 power-domains = <&mmcc OXILICX_GDSC>;
2147 operating-points-v2 = <&gpu_opp_table>;
2148
2149 interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
2150 <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
2151 interconnect-names = "gfx-mem", "ocmem";
2152
2153 // iommus = <&gpu_iommu 0>;
2154
2155 status = "disabled";
2156
2157 gpu_opp_table: opp-table {
2158 compatible = "operating-points-v2";
2159
2160 opp-320000000 {
2161 opp-hz = /bits/ 64 <320000000>;
2162 };
2163
2164 opp-200000000 {
2165 opp-hz = /bits/ 64 <200000000>;
2166 };
2167
2168 opp-27000000 {
2169 opp-hz = /bits/ 64 <27000000>;
2170 };
2171 };
2172 };
2173
2174 sram@fdd00000 {
2175 compatible = "qcom,msm8974-ocmem";
2176 reg = <0xfdd00000 0x2000>,
2177 <0xfec00000 0x180000>;
2178 reg-names = "ctrl", "mem";
2179 ranges = <0 0xfec00000 0x180000>;
2180 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
2181 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
2182 clock-names = "core", "iface";
2183
2184 #address-cells = <1>;
2185 #size-cells = <1>;
2186
2187 gmu_sram: gmu-sram@0 {
2188 reg = <0x0 0x100000>;
2189 };
2190 };
2191
2192 remoteproc_adsp: remoteproc@fe200000 {
2193 compatible = "qcom,msm8974-adsp-pil";
2194 reg = <0xfe200000 0x100>;
2195
2196 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
2197 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2198 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2199 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2200 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2201 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2202
2203 clocks = <&xo_board>;
2204 clock-names = "xo";
2205
2206 memory-region = <&adsp_region>;
2207
2208 qcom,smem-states = <&adsp_smp2p_out 0>;
2209 qcom,smem-state-names = "stop";
2210
2211 status = "disabled";
2212
2213 smd-edge {
2214 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2215
2216 mboxes = <&apcs 8>;
2217 qcom,smd-edge = <1>;
2218 label = "lpass";
2219 };
2220 };
2221
2222 imem: sram@fe805000 {
2223 compatible = "qcom,msm8974-imem", "syscon", "simple-mfd";
2224 reg = <0xfe805000 0x1000>;
2225
2226 reboot-mode {
2227 compatible = "syscon-reboot-mode";
2228 offset = <0x65c>;
2229 };
2230 };
2231 };
2232
2233 thermal-zones {
2234 cpu0-thermal {
2235 polling-delay-passive = <250>;
2236 polling-delay = <1000>;
2237
2238 thermal-sensors = <&tsens 5>;
2239
2240 trips {
2241 cpu_alert0: trip0 {
2242 temperature = <75000>;
2243 hysteresis = <2000>;
2244 type = "passive";
2245 };
2246 cpu_crit0: trip1 {
2247 temperature = <110000>;
2248 hysteresis = <2000>;
2249 type = "critical";
2250 };
2251 };
2252 };
2253
2254 cpu1-thermal {
2255 polling-delay-passive = <250>;
2256 polling-delay = <1000>;
2257
2258 thermal-sensors = <&tsens 6>;
2259
2260 trips {
2261 cpu_alert1: trip0 {
2262 temperature = <75000>;
2263 hysteresis = <2000>;
2264 type = "passive";
2265 };
2266 cpu_crit1: trip1 {
2267 temperature = <110000>;
2268 hysteresis = <2000>;
2269 type = "critical";
2270 };
2271 };
2272 };
2273
2274 cpu2-thermal {
2275 polling-delay-passive = <250>;
2276 polling-delay = <1000>;
2277
2278 thermal-sensors = <&tsens 7>;
2279
2280 trips {
2281 cpu_alert2: trip0 {
2282 temperature = <75000>;
2283 hysteresis = <2000>;
2284 type = "passive";
2285 };
2286 cpu_crit2: trip1 {
2287 temperature = <110000>;
2288 hysteresis = <2000>;
2289 type = "critical";
2290 };
2291 };
2292 };
2293
2294 cpu3-thermal {
2295 polling-delay-passive = <250>;
2296 polling-delay = <1000>;
2297
2298 thermal-sensors = <&tsens 8>;
2299
2300 trips {
2301 cpu_alert3: trip0 {
2302 temperature = <75000>;
2303 hysteresis = <2000>;
2304 type = "passive";
2305 };
2306 cpu_crit3: trip1 {
2307 temperature = <110000>;
2308 hysteresis = <2000>;
2309 type = "critical";
2310 };
2311 };
2312 };
2313
2314 q6-dsp-thermal {
2315 polling-delay-passive = <250>;
2316 polling-delay = <1000>;
2317
2318 thermal-sensors = <&tsens 1>;
2319
2320 trips {
2321 q6_dsp_alert0: trip-point0 {
2322 temperature = <90000>;
2323 hysteresis = <2000>;
2324 type = "hot";
2325 };
2326 };
2327 };
2328
2329 modemtx-thermal {
2330 polling-delay-passive = <250>;
2331 polling-delay = <1000>;
2332
2333 thermal-sensors = <&tsens 2>;
2334
2335 trips {
2336 modemtx_alert0: trip-point0 {
2337 temperature = <90000>;
2338 hysteresis = <2000>;
2339 type = "hot";
2340 };
2341 };
2342 };
2343
2344 video-thermal {
2345 polling-delay-passive = <250>;
2346 polling-delay = <1000>;
2347
2348 thermal-sensors = <&tsens 3>;
2349
2350 trips {
2351 video_alert0: trip-point0 {
2352 temperature = <95000>;
2353 hysteresis = <2000>;
2354 type = "hot";
2355 };
2356 };
2357 };
2358
2359 wlan-thermal {
2360 polling-delay-passive = <250>;
2361 polling-delay = <1000>;
2362
2363 thermal-sensors = <&tsens 4>;
2364
2365 trips {
2366 wlan_alert0: trip-point0 {
2367 temperature = <105000>;
2368 hysteresis = <2000>;
2369 type = "hot";
2370 };
2371 };
2372 };
2373
2374 gpu-top-thermal {
2375 polling-delay-passive = <250>;
2376 polling-delay = <1000>;
2377
2378 thermal-sensors = <&tsens 9>;
2379
2380 trips {
2381 gpu1_alert0: trip-point0 {
2382 temperature = <90000>;
2383 hysteresis = <2000>;
2384 type = "hot";
2385 };
2386 };
2387 };
2388
2389 gpu-bottom-thermal {
2390 polling-delay-passive = <250>;
2391 polling-delay = <1000>;
2392
2393 thermal-sensors = <&tsens 10>;
2394
2395 trips {
2396 gpu2_alert0: trip-point0 {
2397 temperature = <90000>;
2398 hysteresis = <2000>;
2399 type = "hot";
2400 };
2401 };
2402 };
2403 };
2404
2405 timer {
2406 compatible = "arm,armv7-timer";
2407 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2408 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2409 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2410 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2411 clock-frequency = <19200000>;
2412 };
2413 };
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