1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * SDX65 SoC device tree source
4 *
5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
6 *
7 */
8
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
16
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
21 interrupt-parent = <&intc>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0>;
26 };
27
28 clocks {
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 clock-frequency = <76800000>;
32 clock-output-names = "xo_board";
33 #clock-cells = <0>;
34 };
35
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
40 #clock-cells = <0>;
41 };
42
43 nand_clk_dummy: nand-clk-dummy {
44 compatible = "fixed-clock";
45 clock-frequency = <32764>;
46 #clock-cells = <0>;
47 };
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a7";
57 reg = <0x0>;
58 enable-method = "psci";
59 clocks = <&apcs>;
60 power-domains = <&rpmhpd SDX65_CX_AO>;
61 power-domain-names = "rpmhpd";
62 operating-points-v2 = <&cpu_opp_table>;
63 };
64 };
65
66 firmware {
67 scm {
68 compatible = "qcom,scm-sdx65", "qcom,scm";
69 };
70 };
71
72 mc_virt: interconnect-mc-virt {
73 compatible = "qcom,sdx65-mc-virt";
74 #interconnect-cells = <1>;
75 qcom,bcm-voters = <&apps_bcm_voter>;
76 };
77
78 cpu_opp_table: opp-table-cpu {
79 compatible = "operating-points-v2";
80 opp-shared;
81
82 opp-345600000 {
83 opp-hz = /bits/ 64 <345600000>;
84 required-opps = <&rpmhpd_opp_low_svs>;
85 };
86
87 opp-576000000 {
88 opp-hz = /bits/ 64 <576000000>;
89 required-opps = <&rpmhpd_opp_svs>;
90 };
91
92 opp-1094400000 {
93 opp-hz = /bits/ 64 <1094400000>;
94 required-opps = <&rpmhpd_opp_nom>;
95 };
96
97 opp-1497600000 {
98 opp-hz = /bits/ 64 <1497600000>;
99 required-opps = <&rpmhpd_opp_turbo>;
100 };
101 };
102
103 psci {
104 compatible = "arm,psci-1.0";
105 method = "smc";
106 };
107
108 reserved_memory: reserved-memory {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 ranges;
112
113 tz_heap_mem: memory@8fcad000 {
114 no-map;
115 reg = <0x8fcad000 0x40000>;
116 };
117
118 secdata_mem: memory@8fcfd000 {
119 no-map;
120 reg = <0x8fcfd000 0x1000>;
121 };
122
123 hyp_mem: memory@8fd00000 {
124 no-map;
125 reg = <0x8fd00000 0x80000>;
126 };
127
128 access_control_mem: memory@8fd80000 {
129 no-map;
130 reg = <0x8fd80000 0x80000>;
131 };
132
133 aop_mem: memory@8fe00000 {
134 no-map;
135 reg = <0x8fe00000 0x20000>;
136 };
137
138 smem_mem: memory@8fe20000 {
139 compatible = "qcom,smem";
140 reg = <0x8fe20000 0xc0000>;
141 hwlocks = <&tcsr_mutex 3>;
142 no-map;
143 };
144
145 cmd_db: reserved-memory@8fee0000 {
146 compatible = "qcom,cmd-db";
147 reg = <0x8fee0000 0x20000>;
148 no-map;
149 };
150
151 tz_mem: memory@8ff00000 {
152 no-map;
153 reg = <0x8ff00000 0x100000>;
154 };
155
156 tz_apps_mem: memory@90000000 {
157 no-map;
158 reg = <0x90000000 0x500000>;
159 };
160
161 llcc_tcm_mem: memory@15800000 {
162 no-map;
163 reg = <0x15800000 0x800000>;
164 };
165 };
166
167 smp2p-mpss {
168 compatible = "qcom,smp2p";
169 qcom,smem = <435>, <428>;
170 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
171 mboxes = <&apcs 14>;
172 qcom,local-pid = <0>;
173 qcom,remote-pid = <1>;
174
175 modem_smp2p_out: master-kernel {
176 qcom,entry-name = "master-kernel";
177 #qcom,smem-state-cells = <1>;
178 };
179
180 modem_smp2p_in: slave-kernel {
181 qcom,entry-name = "slave-kernel";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 };
185
186 ipa_smp2p_out: ipa-ap-to-modem {
187 qcom,entry-name = "ipa";
188 #qcom,smem-state-cells = <1>;
189 };
190
191 ipa_smp2p_in: ipa-modem-to-ap {
192 qcom,entry-name = "ipa";
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196 };
197
198 soc: soc {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 ranges;
202 compatible = "simple-bus";
203
204 gcc: clock-controller@100000 {
205 compatible = "qcom,gcc-sdx65";
206 reg = <0x00100000 0x001f7400>;
207 clocks = <&rpmhcc RPMH_CXO_CLK>,
208 <&rpmhcc RPMH_CXO_CLK_A>,
209 <&sleep_clk>,
210 <&pcie_phy>,
211 <0>;
212 clock-names = "bi_tcxo",
213 "bi_tcxo_ao",
214 "sleep_clk",
215 "pcie_pipe_clk",
216 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
217 #power-domain-cells = <1>;
218 #clock-cells = <1>;
219 #reset-cells = <1>;
220 };
221
222 blsp1_uart3: serial@831000 {
223 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
224 reg = <0x00831000 0x200>;
225 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
227 clock-names = "core", "iface";
228 status = "disabled";
229 };
230
231 usb_hsphy: phy@ff4000 {
232 compatible = "qcom,sdx65-usb-hs-phy",
233 "qcom,usb-snps-hs-7nm-phy";
234 reg = <0xff4000 0x120>;
235 #phy-cells = <0>;
236 clocks = <&rpmhcc RPMH_CXO_CLK>;
237 clock-names = "ref";
238 resets = <&gcc GCC_QUSB2PHY_BCR>;
239 status = "disabled";
240 };
241
242 usb_qmpphy: phy@ff6000 {
243 compatible = "qcom,sdx65-qmp-usb3-uni-phy";
244 reg = <0x00ff6000 0x2000>;
245
246 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
247 <&gcc GCC_USB3_PRIM_CLKREF_EN>,
248 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
249 <&gcc GCC_USB3_PHY_PIPE_CLK>;
250 clock-names = "aux",
251 "ref",
252 "cfg_ahb",
253 "pipe";
254 clock-output-names = "usb3_uni_phy_pipe_clk_src";
255 #clock-cells = <0>;
256 #phy-cells = <0>;
257
258 resets = <&gcc GCC_USB3_PHY_BCR>,
259 <&gcc GCC_USB3PHY_PHY_BCR>;
260 reset-names = "phy",
261 "phy_phy";
262
263 status = "disabled";
264
265 };
266
267 system_noc: interconnect@1620000 {
268 compatible = "qcom,sdx65-system-noc";
269 reg = <0x01620000 0x31200>;
270 #interconnect-cells = <1>;
271 qcom,bcm-voters = <&apps_bcm_voter>;
272 };
273
274 qpic_bam: dma-controller@1b04000 {
275 compatible = "qcom,bam-v1.7.0";
276 reg = <0x01b04000 0x1c000>;
277 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&rpmhcc RPMH_QPIC_CLK>;
279 clock-names = "bam_clk";
280 #dma-cells = <1>;
281 qcom,ee = <0>;
282 qcom,controlled-remotely;
283 status = "disabled";
284 };
285
286 qpic_nand: nand-controller@1b30000 {
287 compatible = "qcom,sdx55-nand";
288 reg = <0x01b30000 0x10000>;
289 #address-cells = <1>;
290 #size-cells = <0>;
291 clocks = <&rpmhcc RPMH_QPIC_CLK>,
292 <&nand_clk_dummy>;
293 clock-names = "core", "aon";
294
295 dmas = <&qpic_bam 0>,
296 <&qpic_bam 1>,
297 <&qpic_bam 2>;
298 dma-names = "tx", "rx", "cmd";
299 status = "disabled";
300 };
301
302 pcie_ep: pcie-ep@1c00000 {
303 compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
304 reg = <0x01c00000 0x3000>,
305 <0x40000000 0xf1d>,
306 <0x40000f20 0xa8>,
307 <0x40001000 0x1000>,
308 <0x40200000 0x100000>,
309 <0x01c03000 0x3000>;
310 reg-names = "parf",
311 "dbi",
312 "elbi",
313 "atu",
314 "addr_space",
315 "mmio";
316
317 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
318
319 clocks = <&gcc GCC_PCIE_AUX_CLK>,
320 <&gcc GCC_PCIE_CFG_AHB_CLK>,
321 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
322 <&gcc GCC_PCIE_SLV_AXI_CLK>,
323 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
324 <&gcc GCC_PCIE_SLEEP_CLK>,
325 <&gcc GCC_PCIE_0_CLKREF_EN>;
326 clock-names = "aux",
327 "cfg",
328 "bus_master",
329 "bus_slave",
330 "slave_q2a",
331 "sleep",
332 "ref";
333
334 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-names = "global", "doorbell";
337
338 resets = <&gcc GCC_PCIE_BCR>;
339 reset-names = "core";
340
341 power-domains = <&gcc PCIE_GDSC>;
342
343 phys = <&pcie_phy>;
344 phy-names = "pciephy";
345
346 max-link-speed = <3>;
347 num-lanes = <2>;
348
349 status = "disabled";
350 };
351
352 pcie_phy: phy@1c06000 {
353 compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
354 reg = <0x01c06000 0x2000>;
355
356 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
357 <&gcc GCC_PCIE_CFG_AHB_CLK>,
358 <&gcc GCC_PCIE_0_CLKREF_EN>,
359 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
360 <&gcc GCC_PCIE_PIPE_CLK>;
361 clock-names = "aux",
362 "cfg_ahb",
363 "ref",
364 "rchng",
365 "pipe";
366
367 resets = <&gcc GCC_PCIE_PHY_BCR>;
368 reset-names = "phy";
369
370 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
371 assigned-clock-rates = <100000000>;
372
373 power-domains = <&gcc PCIE_GDSC>;
374
375 #clock-cells = <0>;
376 clock-output-names = "pcie_pipe_clk";
377
378 #phy-cells = <0>;
379
380 status = "disabled";
381 };
382
383 tcsr_mutex: hwlock@1f40000 {
384 compatible = "qcom,tcsr-mutex";
385 reg = <0x01f40000 0x40000>;
386 #hwlock-cells = <1>;
387 };
388
389 tcsr: syscon@1fcb000 {
390 compatible = "qcom,sdx65-tcsr", "syscon";
391 reg = <0x01fc0000 0x1000>;
392 };
393
394 ipa: ipa@3f40000 {
395 compatible = "qcom,sdx65-ipa";
396
397 reg = <0x03f40000 0x10000>,
398 <0x03f50000 0x5000>,
399 <0x03e04000 0xfc000>;
400 reg-names = "ipa-reg",
401 "ipa-shared",
402 "gsi";
403
404 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
405 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
406 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
407 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
408 interrupt-names = "ipa",
409 "gsi",
410 "ipa-clock-query",
411 "ipa-setup-ready";
412
413 iommus = <&apps_smmu 0x5e0 0x0>,
414 <&apps_smmu 0x5e2 0x0>;
415
416 clocks = <&rpmhcc RPMH_IPA_CLK>;
417 clock-names = "core";
418
419 interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
420 <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
421 interconnect-names = "memory",
422 "config";
423
424 qcom,smem-states = <&ipa_smp2p_out 0>,
425 <&ipa_smp2p_out 1>;
426 qcom,smem-state-names = "ipa-clock-enabled-valid",
427 "ipa-clock-enabled";
428
429 status = "disabled";
430 };
431
432 remoteproc_mpss: remoteproc@4080000 {
433 compatible = "qcom,sdx55-mpss-pas";
434 reg = <0x04080000 0x4040>;
435
436 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
437 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
438 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
439 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
440 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
441 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
442 interrupt-names = "wdog", "fatal", "ready", "handover",
443 "stop-ack", "shutdown-ack";
444
445 clocks = <&rpmhcc RPMH_CXO_CLK>;
446 clock-names = "xo";
447
448 power-domains = <&rpmhpd SDX65_CX>,
449 <&rpmhpd SDX65_MSS>;
450 power-domain-names = "cx", "mss";
451
452 qcom,smem-states = <&modem_smp2p_out 0>;
453 qcom,smem-state-names = "stop";
454
455 status = "disabled";
456
457 glink-edge {
458 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
459 label = "mpss";
460 qcom,remote-pid = <1>;
461 mboxes = <&apcs 15>;
462 };
463 };
464
465 sdhc_1: mmc@8804000 {
466 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
467 reg = <0x08804000 0x1000>;
468 reg-names = "hc";
469 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-names = "hc_irq", "pwr_irq";
472 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
473 <&gcc GCC_SDCC1_APPS_CLK>;
474 clock-names = "iface", "core";
475 status = "disabled";
476 };
477
478 mem_noc: interconnect@9680000 {
479 compatible = "qcom,sdx65-mem-noc";
480 reg = <0x09680000 0x27200>;
481 #interconnect-cells = <1>;
482 qcom,bcm-voters = <&apps_bcm_voter>;
483 };
484
485 usb: usb@a6f8800 {
486 compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
487 reg = <0x0a6f8800 0x400>;
488 #address-cells = <1>;
489 #size-cells = <1>;
490 ranges;
491
492 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
493 <&gcc GCC_USB30_MASTER_CLK>,
494 <&gcc GCC_USB30_MSTR_AXI_CLK>,
495 <&gcc GCC_USB30_SLEEP_CLK>,
496 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
497 clock-names = "cfg_noc", "core", "iface", "sleep",
498 "mock_utmi";
499
500 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
501 <&gcc GCC_USB30_MASTER_CLK>;
502 assigned-clock-rates = <19200000>, <200000000>;
503
504 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
505 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
506 <&pdc 19 IRQ_TYPE_EDGE_BOTH>,
507 <&pdc 18 IRQ_TYPE_EDGE_BOTH>,
508 <&pdc 76 IRQ_TYPE_LEVEL_HIGH>;
509 interrupt-names = "pwr_event",
510 "hs_phy_irq",
511 "dp_hs_phy_irq",
512 "dm_hs_phy_irq",
513 "ss_phy_irq";
514
515 power-domains = <&gcc USB30_GDSC>;
516
517 resets = <&gcc GCC_USB30_BCR>;
518
519 status = "disabled";
520
521 usb_dwc3: usb@a600000 {
522 compatible = "snps,dwc3";
523 reg = <0x0a600000 0xcd00>;
524 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
525 iommus = <&apps_smmu 0x1a0 0x0>;
526 snps,dis_u2_susphy_quirk;
527 snps,dis_enblslpm_quirk;
528 phys = <&usb_hsphy>, <&usb_qmpphy>;
529 phy-names = "usb2-phy", "usb3-phy";
530 };
531 };
532
533 restart@c264000 {
534 compatible = "qcom,pshold";
535 reg = <0x0c264000 0x1000>;
536 };
537
538 spmi_bus: spmi@c440000 {
539 compatible = "qcom,spmi-pmic-arb";
540 reg = <0xc440000 0xd00>,
541 <0xc600000 0x2000000>,
542 <0xe600000 0x100000>,
543 <0xe700000 0xa0000>,
544 <0xc40a000 0x26000>;
545 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
546 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "periph_irq";
548 interrupt-controller;
549 #interrupt-cells = <4>;
550 #address-cells = <2>;
551 #size-cells = <0>;
552 qcom,channel = <0>;
553 qcom,ee = <0>;
554 };
555
556 tlmm: pinctrl@f100000 {
557 compatible = "qcom,sdx65-tlmm";
558 reg = <0xf100000 0x300000>;
559 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
560 gpio-controller;
561 #gpio-cells = <2>;
562 gpio-ranges = <&tlmm 0 0 109>;
563 interrupt-controller;
564 interrupt-parent = <&intc>;
565 #interrupt-cells = <2>;
566 };
567
568 pdc: interrupt-controller@b210000 {
569 compatible = "qcom,sdx65-pdc", "qcom,pdc";
570 reg = <0xb210000 0x10000>;
571 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
572 #interrupt-cells = <2>;
573 interrupt-parent = <&intc>;
574 interrupt-controller;
575 };
576
577 sram@1468f000 {
578 compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
579 reg = <0x1468f000 0x1000>;
580 ranges = <0x0 0x1468f000 0x1000>;
581 #address-cells = <1>;
582 #size-cells = <1>;
583
584 pil-reloc@94c {
585 compatible = "qcom,pil-reloc-info";
586 reg = <0x94c 0xc8>;
587 };
588 };
589
590 apps_smmu: iommu@15000000 {
591 compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
592 reg = <0x15000000 0x40000>;
593 #iommu-cells = <2>;
594 #global-interrupts = <1>;
595 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
628 };
629
630 intc: interrupt-controller@17800000 {
631 compatible = "qcom,msm-qgic2";
632 interrupt-controller;
633 interrupt-parent = <&intc>;
634 #interrupt-cells = <3>;
635 reg = <0x17800000 0x1000>,
636 <0x17802000 0x1000>;
637 };
638
639 a7pll: clock@17808000 {
640 compatible = "qcom,sdx55-a7pll";
641 reg = <0x17808000 0x1000>;
642 clocks = <&rpmhcc RPMH_CXO_CLK>;
643 clock-names = "bi_tcxo";
644 #clock-cells = <0>;
645 };
646
647 apcs: mailbox@17810000 {
648 compatible = "qcom,sdx55-apcs-gcc", "syscon";
649 reg = <0x17810000 0x2000>;
650 #mbox-cells = <1>;
651 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
652 clock-names = "ref", "pll", "aux";
653 #clock-cells = <0>;
654 };
655
656 watchdog@17817000 {
657 compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
658 reg = <0x17817000 0x1000>;
659 clocks = <&sleep_clk>;
660 };
661
662 timer@17820000 {
663 #address-cells = <1>;
664 #size-cells = <1>;
665 ranges;
666 compatible = "arm,armv7-timer-mem";
667 reg = <0x17820000 0x1000>;
668 clock-frequency = <19200000>;
669
670 frame@17821000 {
671 frame-number = <0>;
672 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
674 reg = <0x17821000 0x1000>,
675 <0x17822000 0x1000>;
676 };
677
678 frame@17823000 {
679 frame-number = <1>;
680 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
681 reg = <0x17823000 0x1000>;
682 status = "disabled";
683 };
684
685 frame@17824000 {
686 frame-number = <2>;
687 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
688 reg = <0x17824000 0x1000>;
689 status = "disabled";
690 };
691
692 frame@17825000 {
693 frame-number = <3>;
694 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
695 reg = <0x17825000 0x1000>;
696 status = "disabled";
697 };
698
699 frame@17826000 {
700 frame-number = <4>;
701 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
702 reg = <0x17826000 0x1000>;
703 status = "disabled";
704 };
705
706 frame@17827000 {
707 frame-number = <5>;
708 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
709 reg = <0x17827000 0x1000>;
710 status = "disabled";
711 };
712
713 frame@17828000 {
714 frame-number = <6>;
715 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
716 reg = <0x17828000 0x1000>;
717 status = "disabled";
718 };
719
720 frame@17829000 {
721 frame-number = <7>;
722 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
723 reg = <0x17829000 0x1000>;
724 status = "disabled";
725 };
726 };
727
728 apps_rsc: rsc@17830000 {
729 label = "apps_rsc";
730 compatible = "qcom,rpmh-rsc";
731 reg = <0x17830000 0x10000>,
732 <0x17840000 0x10000>;
733 reg-names = "drv-0", "drv-1";
734 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
736 qcom,tcs-offset = <0xd00>;
737 qcom,drv-id = <1>;
738 qcom,tcs-config = <ACTIVE_TCS 2>,
739 <SLEEP_TCS 2>,
740 <WAKE_TCS 2>,
741 <CONTROL_TCS 1>;
742
743 rpmhcc: clock-controller {
744 compatible = "qcom,sdx65-rpmh-clk";
745 #clock-cells = <1>;
746 clock-names = "xo";
747 clocks = <&xo_board>;
748 };
749
750 rpmhpd: power-controller {
751 compatible = "qcom,sdx65-rpmhpd";
752 #power-domain-cells = <1>;
753 operating-points-v2 = <&rpmhpd_opp_table>;
754
755 rpmhpd_opp_table: opp-table {
756 compatible = "operating-points-v2";
757
758 rpmhpd_opp_ret: opp1 {
759 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
760 };
761
762 rpmhpd_opp_min_svs: opp2 {
763 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
764 };
765
766 rpmhpd_opp_low_svs: opp3 {
767 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
768 };
769
770 rpmhpd_opp_svs: opp4 {
771 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
772 };
773
774 rpmhpd_opp_svs_l1: opp5 {
775 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
776 };
777
778 rpmhpd_opp_nom: opp6 {
779 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
780 };
781
782 rpmhpd_opp_nom_l1: opp7 {
783 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
784 };
785
786 rpmhpd_opp_nom_l2: opp8 {
787 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
788 };
789
790 rpmhpd_opp_turbo: opp9 {
791 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
792 };
793
794 rpmhpd_opp_turbo_l1: opp10 {
795 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
796 };
797 };
798 };
799
800 apps_bcm_voter: bcm-voter {
801 compatible = "qcom,bcm-voter";
802 };
803
804 };
805 };
806
807 timer {
808 compatible = "arm,armv7-timer";
809 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
810 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
811 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
812 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
813 clock-frequency = <19200000>;
814 };
815 };
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