1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device Tree Source for the R-Car V2H (R8A77920) SoC
4 *
5 * Copyright (C) 2016 Cogent Embedded Inc.
6 */
7
8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a7792-sysc.h>
12
13 / {
14 compatible = "renesas,r8a7792";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 i2c3 = &i2c3;
23 i2c4 = &i2c4;
24 i2c5 = &i2c5;
25 i2c6 = &iic3;
26 spi0 = &qspi;
27 spi1 = &msiof0;
28 spi2 = &msiof1;
29 vin0 = &vin0;
30 vin1 = &vin1;
31 vin2 = &vin2;
32 vin3 = &vin3;
33 vin4 = &vin4;
34 vin5 = &vin5;
35 };
36
37 /* External CAN clock */
38 can_clk: can {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridden by the board. */
42 clock-frequency = <0>;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu0: cpu@0 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a15";
52 reg = <0>;
53 clock-frequency = <1000000000>;
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
55 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
56 enable-method = "renesas,apmu";
57 next-level-cache = <&L2_CA15>;
58 };
59
60 cpu1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <1>;
64 clock-frequency = <1000000000>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
66 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
67 enable-method = "renesas,apmu";
68 next-level-cache = <&L2_CA15>;
69 };
70
71 L2_CA15: cache-controller-0 {
72 compatible = "cache";
73 cache-unified;
74 cache-level = <2>;
75 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
76 };
77 };
78
79 /* External root clock */
80 extal_clk: extal {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 /* This value must be overridden by the board. */
84 clock-frequency = <0>;
85 };
86
87 lbsc: lbsc {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges = <0 0 0 0x1c000000>;
92 };
93
94 pmu {
95 compatible = "arm,cortex-a15-pmu";
96 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
97 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
98 interrupt-affinity = <&cpu0>, <&cpu1>;
99 };
100
101 /* External SCIF clock */
102 scif_clk: scif {
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 /* This value must be overridden by the board. */
106 clock-frequency = <0>;
107 };
108
109 soc {
110 compatible = "simple-bus";
111 interrupt-parent = <&gic>;
112
113 #address-cells = <2>;
114 #size-cells = <2>;
115 ranges;
116
117 rwdt: watchdog@e6020000 {
118 compatible = "renesas,r8a7792-wdt",
119 "renesas,rcar-gen2-wdt";
120 reg = <0 0xe6020000 0 0x0c>;
121 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
122 clocks = <&cpg CPG_MOD 402>;
123 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
124 resets = <&cpg 402>;
125 status = "disabled";
126 };
127
128 gpio0: gpio@e6050000 {
129 compatible = "renesas,gpio-r8a7792",
130 "renesas,rcar-gen2-gpio";
131 reg = <0 0xe6050000 0 0x50>;
132 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
133 #gpio-cells = <2>;
134 gpio-controller;
135 gpio-ranges = <&pfc 0 0 29>;
136 #interrupt-cells = <2>;
137 interrupt-controller;
138 clocks = <&cpg CPG_MOD 912>;
139 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
140 resets = <&cpg 912>;
141 };
142
143 gpio1: gpio@e6051000 {
144 compatible = "renesas,gpio-r8a7792",
145 "renesas,rcar-gen2-gpio";
146 reg = <0 0xe6051000 0 0x50>;
147 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-ranges = <&pfc 0 32 23>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
153 clocks = <&cpg CPG_MOD 911>;
154 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
155 resets = <&cpg 911>;
156 };
157
158 gpio2: gpio@e6052000 {
159 compatible = "renesas,gpio-r8a7792",
160 "renesas,rcar-gen2-gpio";
161 reg = <0 0xe6052000 0 0x50>;
162 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
163 #gpio-cells = <2>;
164 gpio-controller;
165 gpio-ranges = <&pfc 0 64 32>;
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 clocks = <&cpg CPG_MOD 910>;
169 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
170 resets = <&cpg 910>;
171 };
172
173 gpio3: gpio@e6053000 {
174 compatible = "renesas,gpio-r8a7792",
175 "renesas,rcar-gen2-gpio";
176 reg = <0 0xe6053000 0 0x50>;
177 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
178 #gpio-cells = <2>;
179 gpio-controller;
180 gpio-ranges = <&pfc 0 96 28>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&cpg CPG_MOD 909>;
184 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
185 resets = <&cpg 909>;
186 };
187
188 gpio4: gpio@e6054000 {
189 compatible = "renesas,gpio-r8a7792",
190 "renesas,rcar-gen2-gpio";
191 reg = <0 0xe6054000 0 0x50>;
192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
193 #gpio-cells = <2>;
194 gpio-controller;
195 gpio-ranges = <&pfc 0 128 17>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
198 clocks = <&cpg CPG_MOD 908>;
199 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
200 resets = <&cpg 908>;
201 };
202
203 gpio5: gpio@e6055000 {
204 compatible = "renesas,gpio-r8a7792",
205 "renesas,rcar-gen2-gpio";
206 reg = <0 0xe6055000 0 0x50>;
207 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
208 #gpio-cells = <2>;
209 gpio-controller;
210 gpio-ranges = <&pfc 0 160 17>;
211 #interrupt-cells = <2>;
212 interrupt-controller;
213 clocks = <&cpg CPG_MOD 907>;
214 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
215 resets = <&cpg 907>;
216 };
217
218 gpio6: gpio@e6055100 {
219 compatible = "renesas,gpio-r8a7792",
220 "renesas,rcar-gen2-gpio";
221 reg = <0 0xe6055100 0 0x50>;
222 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223 #gpio-cells = <2>;
224 gpio-controller;
225 gpio-ranges = <&pfc 0 192 17>;
226 #interrupt-cells = <2>;
227 interrupt-controller;
228 clocks = <&cpg CPG_MOD 905>;
229 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
230 resets = <&cpg 905>;
231 };
232
233 gpio7: gpio@e6055200 {
234 compatible = "renesas,gpio-r8a7792",
235 "renesas,rcar-gen2-gpio";
236 reg = <0 0xe6055200 0 0x50>;
237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
238 #gpio-cells = <2>;
239 gpio-controller;
240 gpio-ranges = <&pfc 0 224 17>;
241 #interrupt-cells = <2>;
242 interrupt-controller;
243 clocks = <&cpg CPG_MOD 904>;
244 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
245 resets = <&cpg 904>;
246 };
247
248 gpio8: gpio@e6055300 {
249 compatible = "renesas,gpio-r8a7792",
250 "renesas,rcar-gen2-gpio";
251 reg = <0 0xe6055300 0 0x50>;
252 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
253 #gpio-cells = <2>;
254 gpio-controller;
255 gpio-ranges = <&pfc 0 256 17>;
256 #interrupt-cells = <2>;
257 interrupt-controller;
258 clocks = <&cpg CPG_MOD 921>;
259 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
260 resets = <&cpg 921>;
261 };
262
263 gpio9: gpio@e6055400 {
264 compatible = "renesas,gpio-r8a7792",
265 "renesas,rcar-gen2-gpio";
266 reg = <0 0xe6055400 0 0x50>;
267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
268 #gpio-cells = <2>;
269 gpio-controller;
270 gpio-ranges = <&pfc 0 288 17>;
271 #interrupt-cells = <2>;
272 interrupt-controller;
273 clocks = <&cpg CPG_MOD 919>;
274 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
275 resets = <&cpg 919>;
276 };
277
278 gpio10: gpio@e6055500 {
279 compatible = "renesas,gpio-r8a7792",
280 "renesas,rcar-gen2-gpio";
281 reg = <0 0xe6055500 0 0x50>;
282 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
283 #gpio-cells = <2>;
284 gpio-controller;
285 gpio-ranges = <&pfc 0 320 32>;
286 #interrupt-cells = <2>;
287 interrupt-controller;
288 clocks = <&cpg CPG_MOD 914>;
289 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
290 resets = <&cpg 914>;
291 };
292
293 gpio11: gpio@e6055600 {
294 compatible = "renesas,gpio-r8a7792",
295 "renesas,rcar-gen2-gpio";
296 reg = <0 0xe6055600 0 0x50>;
297 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
298 #gpio-cells = <2>;
299 gpio-controller;
300 gpio-ranges = <&pfc 0 352 30>;
301 #interrupt-cells = <2>;
302 interrupt-controller;
303 clocks = <&cpg CPG_MOD 913>;
304 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
305 resets = <&cpg 913>;
306 };
307
308 pfc: pinctrl@e6060000 {
309 compatible = "renesas,pfc-r8a7792";
310 reg = <0 0xe6060000 0 0x144>;
311 };
312
313 cpg: clock-controller@e6150000 {
314 compatible = "renesas,r8a7792-cpg-mssr";
315 reg = <0 0xe6150000 0 0x1000>;
316 clocks = <&extal_clk>;
317 clock-names = "extal";
318 #clock-cells = <2>;
319 #power-domain-cells = <0>;
320 #reset-cells = <1>;
321 };
322
323 apmu@e6152000 {
324 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
325 reg = <0 0xe6152000 0 0x188>;
326 cpus = <&cpu0>, <&cpu1>;
327 };
328
329 rst: reset-controller@e6160000 {
330 compatible = "renesas,r8a7792-rst";
331 reg = <0 0xe6160000 0 0x0100>;
332 };
333
334 sysc: system-controller@e6180000 {
335 compatible = "renesas,r8a7792-sysc";
336 reg = <0 0xe6180000 0 0x0200>;
337 #power-domain-cells = <1>;
338 };
339
340 irqc: interrupt-controller@e61c0000 {
341 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
342 #interrupt-cells = <2>;
343 interrupt-controller;
344 reg = <0 0xe61c0000 0 0x200>;
345 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&cpg CPG_MOD 407>;
350 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
351 resets = <&cpg 407>;
352 };
353
354 tmu0: timer@e61e0000 {
355 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
356 reg = <0 0xe61e0000 0 0x30>;
357 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-names = "tuni0", "tuni1", "tuni2";
361 clocks = <&cpg CPG_MOD 125>;
362 clock-names = "fck";
363 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
364 resets = <&cpg 125>;
365 status = "disabled";
366 };
367
368 tmu1: timer@fff60000 {
369 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
370 reg = <0 0xfff60000 0 0x30>;
371 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
376 clocks = <&cpg CPG_MOD 111>;
377 clock-names = "fck";
378 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
379 resets = <&cpg 111>;
380 status = "disabled";
381 };
382
383 tmu2: timer@fff70000 {
384 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
385 reg = <0 0xfff70000 0 0x30>;
386 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
391 clocks = <&cpg CPG_MOD 122>;
392 clock-names = "fck";
393 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
394 resets = <&cpg 122>;
395 status = "disabled";
396 };
397
398 tmu3: timer@fff80000 {
399 compatible = "renesas,tmu-r8a7792", "renesas,tmu";
400 reg = <0 0xfff80000 0 0x30>;
401 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
405 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
406 clocks = <&cpg CPG_MOD 121>;
407 clock-names = "fck";
408 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
409 resets = <&cpg 121>;
410 status = "disabled";
411 };
412
413 icram0: sram@e63a0000 {
414 compatible = "mmio-sram";
415 reg = <0 0xe63a0000 0 0x12000>;
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges = <0 0 0xe63a0000 0x12000>;
419 };
420
421 icram1: sram@e63c0000 {
422 compatible = "mmio-sram";
423 reg = <0 0xe63c0000 0 0x1000>;
424 #address-cells = <1>;
425 #size-cells = <1>;
426 ranges = <0 0 0xe63c0000 0x1000>;
427
428 smp-sram@0 {
429 compatible = "renesas,smp-sram";
430 reg = <0 0x100>;
431 };
432 };
433
434 /* I2C doesn't need pinmux */
435 i2c0: i2c@e6508000 {
436 compatible = "renesas,i2c-r8a7792",
437 "renesas,rcar-gen2-i2c";
438 reg = <0 0xe6508000 0 0x40>;
439 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cpg CPG_MOD 931>;
441 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
442 resets = <&cpg 931>;
443 i2c-scl-internal-delay-ns = <6>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 status = "disabled";
447 };
448
449 i2c1: i2c@e6518000 {
450 compatible = "renesas,i2c-r8a7792",
451 "renesas,rcar-gen2-i2c";
452 reg = <0 0xe6518000 0 0x40>;
453 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cpg CPG_MOD 930>;
455 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
456 resets = <&cpg 930>;
457 i2c-scl-internal-delay-ns = <6>;
458 #address-cells = <1>;
459 #size-cells = <0>;
460 status = "disabled";
461 };
462
463 i2c2: i2c@e6530000 {
464 compatible = "renesas,i2c-r8a7792",
465 "renesas,rcar-gen2-i2c";
466 reg = <0 0xe6530000 0 0x40>;
467 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cpg CPG_MOD 929>;
469 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
470 resets = <&cpg 929>;
471 i2c-scl-internal-delay-ns = <6>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 status = "disabled";
475 };
476
477 i2c3: i2c@e6540000 {
478 compatible = "renesas,i2c-r8a7792",
479 "renesas,rcar-gen2-i2c";
480 reg = <0 0xe6540000 0 0x40>;
481 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cpg CPG_MOD 928>;
483 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
484 resets = <&cpg 928>;
485 i2c-scl-internal-delay-ns = <6>;
486 #address-cells = <1>;
487 #size-cells = <0>;
488 status = "disabled";
489 };
490
491 i2c4: i2c@e6520000 {
492 compatible = "renesas,i2c-r8a7792",
493 "renesas,rcar-gen2-i2c";
494 reg = <0 0xe6520000 0 0x40>;
495 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cpg CPG_MOD 927>;
497 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
498 resets = <&cpg 927>;
499 i2c-scl-internal-delay-ns = <6>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 status = "disabled";
503 };
504
505 i2c5: i2c@e6528000 {
506 compatible = "renesas,i2c-r8a7792",
507 "renesas,rcar-gen2-i2c";
508 reg = <0 0xe6528000 0 0x40>;
509 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&cpg CPG_MOD 925>;
511 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
512 resets = <&cpg 925>;
513 i2c-scl-internal-delay-ns = <110>;
514 #address-cells = <1>;
515 #size-cells = <0>;
516 status = "disabled";
517 };
518
519 iic3: i2c@e60b0000 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "renesas,iic-r8a7792",
523 "renesas,rcar-gen2-iic",
524 "renesas,rmobile-iic";
525 reg = <0 0xe60b0000 0 0x425>;
526 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cpg CPG_MOD 926>;
528 dmas = <&dmac0 0x77>, <&dmac0 0x78>,
529 <&dmac1 0x77>, <&dmac1 0x78>;
530 dma-names = "tx", "rx", "tx", "rx";
531 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
532 resets = <&cpg 926>;
533 status = "disabled";
534 };
535
536 dmac0: dma-controller@e6700000 {
537 compatible = "renesas,dmac-r8a7792",
538 "renesas,rcar-dmac";
539 reg = <0 0xe6700000 0 0x20000>;
540 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
556 interrupt-names = "error",
557 "ch0", "ch1", "ch2", "ch3",
558 "ch4", "ch5", "ch6", "ch7",
559 "ch8", "ch9", "ch10", "ch11",
560 "ch12", "ch13", "ch14";
561 clocks = <&cpg CPG_MOD 219>;
562 clock-names = "fck";
563 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
564 resets = <&cpg 219>;
565 #dma-cells = <1>;
566 dma-channels = <15>;
567 };
568
569 dmac1: dma-controller@e6720000 {
570 compatible = "renesas,dmac-r8a7792",
571 "renesas,rcar-dmac";
572 reg = <0 0xe6720000 0 0x20000>;
573 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "error",
590 "ch0", "ch1", "ch2", "ch3",
591 "ch4", "ch5", "ch6", "ch7",
592 "ch8", "ch9", "ch10", "ch11",
593 "ch12", "ch13", "ch14";
594 clocks = <&cpg CPG_MOD 218>;
595 clock-names = "fck";
596 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
597 resets = <&cpg 218>;
598 #dma-cells = <1>;
599 dma-channels = <15>;
600 };
601
602 avb: ethernet@e6800000 {
603 compatible = "renesas,etheravb-r8a7792",
604 "renesas,etheravb-rcar-gen2";
605 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
606 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cpg CPG_MOD 812>;
608 clock-names = "fck";
609 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
610 resets = <&cpg 812>;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 status = "disabled";
614 };
615
616 qspi: spi@e6b10000 {
617 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
618 reg = <0 0xe6b10000 0 0x2c>;
619 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cpg CPG_MOD 917>;
621 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
622 <&dmac1 0x17>, <&dmac1 0x18>;
623 dma-names = "tx", "rx", "tx", "rx";
624 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
625 resets = <&cpg 917>;
626 num-cs = <1>;
627 #address-cells = <1>;
628 #size-cells = <0>;
629 status = "disabled";
630 };
631
632 scif0: serial@e6e60000 {
633 compatible = "renesas,scif-r8a7792",
634 "renesas,rcar-gen2-scif", "renesas,scif";
635 reg = <0 0xe6e60000 0 64>;
636 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 721>,
638 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
639 clock-names = "fck", "brg_int", "scif_clk";
640 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
641 <&dmac1 0x29>, <&dmac1 0x2a>;
642 dma-names = "tx", "rx", "tx", "rx";
643 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
644 resets = <&cpg 721>;
645 status = "disabled";
646 };
647
648 scif1: serial@e6e68000 {
649 compatible = "renesas,scif-r8a7792",
650 "renesas,rcar-gen2-scif", "renesas,scif";
651 reg = <0 0xe6e68000 0 64>;
652 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cpg CPG_MOD 720>,
654 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
655 clock-names = "fck", "brg_int", "scif_clk";
656 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
657 <&dmac1 0x2d>, <&dmac1 0x2e>;
658 dma-names = "tx", "rx", "tx", "rx";
659 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
660 resets = <&cpg 720>;
661 status = "disabled";
662 };
663
664 scif2: serial@e6e58000 {
665 compatible = "renesas,scif-r8a7792",
666 "renesas,rcar-gen2-scif", "renesas,scif";
667 reg = <0 0xe6e58000 0 64>;
668 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
669 clocks = <&cpg CPG_MOD 719>,
670 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
671 clock-names = "fck", "brg_int", "scif_clk";
672 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
673 <&dmac1 0x2b>, <&dmac1 0x2c>;
674 dma-names = "tx", "rx", "tx", "rx";
675 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
676 resets = <&cpg 719>;
677 status = "disabled";
678 };
679
680 scif3: serial@e6ea8000 {
681 compatible = "renesas,scif-r8a7792",
682 "renesas,rcar-gen2-scif", "renesas,scif";
683 reg = <0 0xe6ea8000 0 64>;
684 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&cpg CPG_MOD 718>,
686 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
687 clock-names = "fck", "brg_int", "scif_clk";
688 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
689 <&dmac1 0x2f>, <&dmac1 0x30>;
690 dma-names = "tx", "rx", "tx", "rx";
691 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
692 resets = <&cpg 718>;
693 status = "disabled";
694 };
695
696 hscif0: serial@e62c0000 {
697 compatible = "renesas,hscif-r8a7792",
698 "renesas,rcar-gen2-hscif", "renesas,hscif";
699 reg = <0 0xe62c0000 0 96>;
700 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cpg CPG_MOD 717>,
702 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
703 clock-names = "fck", "brg_int", "scif_clk";
704 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
705 <&dmac1 0x39>, <&dmac1 0x3a>;
706 dma-names = "tx", "rx", "tx", "rx";
707 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
708 resets = <&cpg 717>;
709 status = "disabled";
710 };
711
712 hscif1: serial@e62c8000 {
713 compatible = "renesas,hscif-r8a7792",
714 "renesas,rcar-gen2-hscif", "renesas,hscif";
715 reg = <0 0xe62c8000 0 96>;
716 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cpg CPG_MOD 716>,
718 <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
719 clock-names = "fck", "brg_int", "scif_clk";
720 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
721 <&dmac1 0x4d>, <&dmac1 0x4e>;
722 dma-names = "tx", "rx", "tx", "rx";
723 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
724 resets = <&cpg 716>;
725 status = "disabled";
726 };
727
728 msiof0: spi@e6e20000 {
729 compatible = "renesas,msiof-r8a7792",
730 "renesas,rcar-gen2-msiof";
731 reg = <0 0xe6e20000 0 0x0064>;
732 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&cpg CPG_MOD 000>;
734 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
735 <&dmac1 0x51>, <&dmac1 0x52>;
736 dma-names = "tx", "rx", "tx", "rx";
737 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
738 resets = <&cpg 000>;
739 #address-cells = <1>;
740 #size-cells = <0>;
741 status = "disabled";
742 };
743
744 msiof1: spi@e6e10000 {
745 compatible = "renesas,msiof-r8a7792",
746 "renesas,rcar-gen2-msiof";
747 reg = <0 0xe6e10000 0 0x0064>;
748 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cpg CPG_MOD 208>;
750 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
751 <&dmac1 0x55>, <&dmac1 0x56>;
752 dma-names = "tx", "rx", "tx", "rx";
753 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
754 resets = <&cpg 208>;
755 #address-cells = <1>;
756 #size-cells = <0>;
757 status = "disabled";
758 };
759
760 can0: can@e6e80000 {
761 compatible = "renesas,can-r8a7792",
762 "renesas,rcar-gen2-can";
763 reg = <0 0xe6e80000 0 0x1000>;
764 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&cpg CPG_MOD 916>,
766 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
767 clock-names = "clkp1", "clkp2", "can_clk";
768 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
769 resets = <&cpg 916>;
770 status = "disabled";
771 };
772
773 can1: can@e6e88000 {
774 compatible = "renesas,can-r8a7792",
775 "renesas,rcar-gen2-can";
776 reg = <0 0xe6e88000 0 0x1000>;
777 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cpg CPG_MOD 915>,
779 <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
780 clock-names = "clkp1", "clkp2", "can_clk";
781 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
782 resets = <&cpg 915>;
783 status = "disabled";
784 };
785
786 vin0: video@e6ef0000 {
787 compatible = "renesas,vin-r8a7792",
788 "renesas,rcar-gen2-vin";
789 reg = <0 0xe6ef0000 0 0x1000>;
790 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 811>;
792 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
793 resets = <&cpg 811>;
794 status = "disabled";
795 };
796
797 vin1: video@e6ef1000 {
798 compatible = "renesas,vin-r8a7792",
799 "renesas,rcar-gen2-vin";
800 reg = <0 0xe6ef1000 0 0x1000>;
801 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cpg CPG_MOD 810>;
803 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
804 resets = <&cpg 810>;
805 status = "disabled";
806 };
807
808 vin2: video@e6ef2000 {
809 compatible = "renesas,vin-r8a7792",
810 "renesas,rcar-gen2-vin";
811 reg = <0 0xe6ef2000 0 0x1000>;
812 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cpg CPG_MOD 809>;
814 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
815 resets = <&cpg 809>;
816 status = "disabled";
817 };
818
819 vin3: video@e6ef3000 {
820 compatible = "renesas,vin-r8a7792",
821 "renesas,rcar-gen2-vin";
822 reg = <0 0xe6ef3000 0 0x1000>;
823 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cpg CPG_MOD 808>;
825 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
826 resets = <&cpg 808>;
827 status = "disabled";
828 };
829
830 vin4: video@e6ef4000 {
831 compatible = "renesas,vin-r8a7792",
832 "renesas,rcar-gen2-vin";
833 reg = <0 0xe6ef4000 0 0x1000>;
834 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&cpg CPG_MOD 805>;
836 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
837 resets = <&cpg 805>;
838 status = "disabled";
839 };
840
841 vin5: video@e6ef5000 {
842 compatible = "renesas,vin-r8a7792",
843 "renesas,rcar-gen2-vin";
844 reg = <0 0xe6ef5000 0 0x1000>;
845 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&cpg CPG_MOD 804>;
847 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
848 resets = <&cpg 804>;
849 status = "disabled";
850 };
851
852 sdhi0: mmc@ee100000 {
853 compatible = "renesas,sdhi-r8a7792",
854 "renesas,rcar-gen2-sdhi";
855 reg = <0 0xee100000 0 0x328>;
856 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
857 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
858 <&dmac1 0xcd>, <&dmac1 0xce>;
859 dma-names = "tx", "rx", "tx", "rx";
860 clocks = <&cpg CPG_MOD 314>;
861 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
862 resets = <&cpg 314>;
863 status = "disabled";
864 };
865
866 gic: interrupt-controller@f1001000 {
867 compatible = "arm,gic-400";
868 #interrupt-cells = <3>;
869 interrupt-controller;
870 reg = <0 0xf1001000 0 0x1000>,
871 <0 0xf1002000 0 0x2000>,
872 <0 0xf1004000 0 0x2000>,
873 <0 0xf1006000 0 0x2000>;
874 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
875 IRQ_TYPE_LEVEL_HIGH)>;
876 clocks = <&cpg CPG_MOD 408>;
877 clock-names = "clk";
878 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
879 resets = <&cpg 408>;
880 };
881
882 vsp@fe928000 {
883 compatible = "renesas,vsp1";
884 reg = <0 0xfe928000 0 0x8000>;
885 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cpg CPG_MOD 131>;
887 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
888 resets = <&cpg 131>;
889 };
890
891 vsp@fe930000 {
892 compatible = "renesas,vsp1";
893 reg = <0 0xfe930000 0 0x8000>;
894 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&cpg CPG_MOD 128>;
896 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
897 resets = <&cpg 128>;
898 };
899
900 vsp@fe938000 {
901 compatible = "renesas,vsp1";
902 reg = <0 0xfe938000 0 0x8000>;
903 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&cpg CPG_MOD 127>;
905 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
906 resets = <&cpg 127>;
907 };
908
909 jpu: jpeg-codec@fe980000 {
910 compatible = "renesas,jpu-r8a7792",
911 "renesas,rcar-gen2-jpu";
912 reg = <0 0xfe980000 0 0x10300>;
913 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&cpg CPG_MOD 106>;
915 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
916 resets = <&cpg 106>;
917 };
918
919 du: display@feb00000 {
920 compatible = "renesas,du-r8a7792";
921 reg = <0 0xfeb00000 0 0x40000>;
922 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
925 clock-names = "du.0", "du.1";
926 resets = <&cpg 724>;
927 reset-names = "du.0";
928 status = "disabled";
929
930 ports {
931 #address-cells = <1>;
932 #size-cells = <0>;
933
934 port@0 {
935 reg = <0>;
936 du_out_rgb0: endpoint {
937 };
938 };
939 port@1 {
940 reg = <1>;
941 du_out_rgb1: endpoint {
942 };
943 };
944 };
945 };
946
947 prr: chipid@ff000044 {
948 compatible = "renesas,prr";
949 reg = <0 0xff000044 0 4>;
950 };
951
952 cmt0: timer@ffca0000 {
953 compatible = "renesas,r8a7792-cmt0",
954 "renesas,rcar-gen2-cmt0";
955 reg = <0 0xffca0000 0 0x1004>;
956 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&cpg CPG_MOD 124>;
959 clock-names = "fck";
960 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
961 resets = <&cpg 124>;
962
963 status = "disabled";
964 };
965
966 cmt1: timer@e6130000 {
967 compatible = "renesas,r8a7792-cmt1",
968 "renesas,rcar-gen2-cmt1";
969 reg = <0 0xe6130000 0 0x1004>;
970 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cpg CPG_MOD 329>;
979 clock-names = "fck";
980 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
981 resets = <&cpg 329>;
982
983 status = "disabled";
984 };
985 };
986
987 timer {
988 compatible = "arm,armv7-timer";
989 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
990 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
991 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
992 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
993 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
994 };
995 };
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