1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
11 #include "rk3xxx.dtsi"
12
13 / {
14 compatible = "rockchip,rk3066a";
15
16 aliases {
17 gpio4 = &gpio4;
18 gpio6 = &gpio6;
19 };
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
30 reg = <0x0>;
31 operating-points =
32 /* kHz uV */
33 <1416000 1300000>,
34 <1200000 1175000>,
35 <1008000 1125000>,
36 <816000 1125000>,
37 <600000 1100000>,
38 <504000 1100000>,
39 <312000 1075000>;
40 clock-latency = <40000>;
41 clocks = <&cru ARMCLK>;
42 };
43 cpu1: cpu@1 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a9";
46 next-level-cache = <&L2>;
47 reg = <0x1>;
48 };
49 };
50
51 display-subsystem {
52 compatible = "rockchip,display-subsystem";
53 ports = <&vop0_out>, <&vop1_out>;
54 };
55
56 hdmi_sound: hdmi-sound {
57 compatible = "simple-audio-card";
58 simple-audio-card,name = "HDMI";
59 simple-audio-card,format = "i2s";
60 simple-audio-card,mclk-fs = <256>;
61 status = "disabled";
62
63 simple-audio-card,codec {
64 sound-dai = <&hdmi>;
65 };
66
67 simple-audio-card,cpu {
68 sound-dai = <&i2s0>;
69 };
70 };
71
72 sram: sram@10080000 {
73 compatible = "mmio-sram";
74 reg = <0x10080000 0x10000>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77 ranges = <0 0x10080000 0x10000>;
78
79 smp-sram@0 {
80 compatible = "rockchip,rk3066-smp-sram";
81 reg = <0x0 0x50>;
82 };
83 };
84
85 vop0: vop@1010c000 {
86 compatible = "rockchip,rk3066-vop";
87 reg = <0x1010c000 0x19c>;
88 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&cru ACLK_LCDC0>,
90 <&cru DCLK_LCDC0>,
91 <&cru HCLK_LCDC0>;
92 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
93 power-domains = <&power RK3066_PD_VIO>;
94 resets = <&cru SRST_LCDC0_AXI>,
95 <&cru SRST_LCDC0_AHB>,
96 <&cru SRST_LCDC0_DCLK>;
97 reset-names = "axi", "ahb", "dclk";
98 status = "disabled";
99
100 vop0_out: port {
101 #address-cells = <1>;
102 #size-cells = <0>;
103
104 vop0_out_hdmi: endpoint@0 {
105 reg = <0>;
106 remote-endpoint = <&hdmi_in_vop0>;
107 };
108 };
109 };
110
111 vop1: vop@1010e000 {
112 compatible = "rockchip,rk3066-vop";
113 reg = <0x1010e000 0x19c>;
114 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
115 clocks = <&cru ACLK_LCDC1>,
116 <&cru DCLK_LCDC1>,
117 <&cru HCLK_LCDC1>;
118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
119 power-domains = <&power RK3066_PD_VIO>;
120 resets = <&cru SRST_LCDC1_AXI>,
121 <&cru SRST_LCDC1_AHB>,
122 <&cru SRST_LCDC1_DCLK>;
123 reset-names = "axi", "ahb", "dclk";
124 status = "disabled";
125
126 vop1_out: port {
127 #address-cells = <1>;
128 #size-cells = <0>;
129
130 vop1_out_hdmi: endpoint@0 {
131 reg = <0>;
132 remote-endpoint = <&hdmi_in_vop1>;
133 };
134 };
135 };
136
137 hdmi: hdmi@10116000 {
138 compatible = "rockchip,rk3066-hdmi";
139 reg = <0x10116000 0x2000>;
140 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cru HCLK_HDMI>;
142 clock-names = "hclk";
143 pinctrl-names = "default";
144 pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
145 power-domains = <&power RK3066_PD_VIO>;
146 rockchip,grf = <&grf>;
147 #sound-dai-cells = <0>;
148 status = "disabled";
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 hdmi_in: port@0 {
155 reg = <0>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 hdmi_in_vop0: endpoint@0 {
160 reg = <0>;
161 remote-endpoint = <&vop0_out_hdmi>;
162 };
163
164 hdmi_in_vop1: endpoint@1 {
165 reg = <1>;
166 remote-endpoint = <&vop1_out_hdmi>;
167 };
168 };
169
170 hdmi_out: port@1 {
171 reg = <1>;
172 };
173 };
174 };
175
176 i2s0: i2s@10118000 {
177 compatible = "rockchip,rk3066-i2s";
178 reg = <0x10118000 0x2000>;
179 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&i2s0_bus>;
182 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
183 clock-names = "i2s_clk", "i2s_hclk";
184 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
185 dma-names = "tx", "rx";
186 rockchip,playback-channels = <8>;
187 rockchip,capture-channels = <2>;
188 #sound-dai-cells = <0>;
189 status = "disabled";
190 };
191
192 i2s1: i2s@1011a000 {
193 compatible = "rockchip,rk3066-i2s";
194 reg = <0x1011a000 0x2000>;
195 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&i2s1_bus>;
198 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
199 clock-names = "i2s_clk", "i2s_hclk";
200 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
201 dma-names = "tx", "rx";
202 rockchip,playback-channels = <2>;
203 rockchip,capture-channels = <2>;
204 #sound-dai-cells = <0>;
205 status = "disabled";
206 };
207
208 i2s2: i2s@1011c000 {
209 compatible = "rockchip,rk3066-i2s";
210 reg = <0x1011c000 0x2000>;
211 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&i2s2_bus>;
214 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
215 clock-names = "i2s_clk", "i2s_hclk";
216 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
217 dma-names = "tx", "rx";
218 rockchip,playback-channels = <2>;
219 rockchip,capture-channels = <2>;
220 #sound-dai-cells = <0>;
221 status = "disabled";
222 };
223
224 cru: clock-controller@20000000 {
225 compatible = "rockchip,rk3066a-cru";
226 reg = <0x20000000 0x1000>;
227 clocks = <&xin24m>;
228 clock-names = "xin24m";
229 rockchip,grf = <&grf>;
230 #clock-cells = <1>;
231 #reset-cells = <1>;
232 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
233 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
234 <&cru PCLK_CPU>, <&cru ACLK_PERI>,
235 <&cru HCLK_PERI>, <&cru PCLK_PERI>;
236 assigned-clock-rates = <400000000>, <594000000>,
237 <300000000>, <150000000>,
238 <75000000>, <300000000>,
239 <150000000>, <75000000>;
240 };
241
242 timer2: timer@2000e000 {
243 compatible = "snps,dw-apb-timer";
244 reg = <0x2000e000 0x100>;
245 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
247 clock-names = "timer", "pclk";
248 };
249
250 efuse: efuse@20010000 {
251 compatible = "rockchip,rk3066a-efuse";
252 reg = <0x20010000 0x4000>;
253 #address-cells = <1>;
254 #size-cells = <1>;
255 clocks = <&cru PCLK_EFUSE>;
256 clock-names = "pclk_efuse";
257
258 cpu_leakage: cpu_leakage@17 {
259 reg = <0x17 0x1>;
260 };
261 };
262
263 timer0: timer@20038000 {
264 compatible = "snps,dw-apb-timer";
265 reg = <0x20038000 0x100>;
266 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
268 clock-names = "timer", "pclk";
269 };
270
271 timer1: timer@2003a000 {
272 compatible = "snps,dw-apb-timer";
273 reg = <0x2003a000 0x100>;
274 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
276 clock-names = "timer", "pclk";
277 };
278
279 tsadc: tsadc@20060000 {
280 compatible = "rockchip,rk3066-tsadc";
281 reg = <0x20060000 0x100>;
282 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
283 clock-names = "saradc", "apb_pclk";
284 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
285 #io-channel-cells = <1>;
286 resets = <&cru SRST_TSADC>;
287 reset-names = "saradc-apb";
288 status = "disabled";
289 };
290
291 pinctrl: pinctrl {
292 compatible = "rockchip,rk3066a-pinctrl";
293 rockchip,grf = <&grf>;
294 #address-cells = <1>;
295 #size-cells = <1>;
296 ranges;
297
298 gpio0: gpio@20034000 {
299 compatible = "rockchip,gpio-bank";
300 reg = <0x20034000 0x100>;
301 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&cru PCLK_GPIO0>;
303
304 gpio-controller;
305 #gpio-cells = <2>;
306
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 };
310
311 gpio1: gpio@2003c000 {
312 compatible = "rockchip,gpio-bank";
313 reg = <0x2003c000 0x100>;
314 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cru PCLK_GPIO1>;
316
317 gpio-controller;
318 #gpio-cells = <2>;
319
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 gpio2: gpio@2003e000 {
325 compatible = "rockchip,gpio-bank";
326 reg = <0x2003e000 0x100>;
327 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&cru PCLK_GPIO2>;
329
330 gpio-controller;
331 #gpio-cells = <2>;
332
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 };
336
337 gpio3: gpio@20080000 {
338 compatible = "rockchip,gpio-bank";
339 reg = <0x20080000 0x100>;
340 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&cru PCLK_GPIO3>;
342
343 gpio-controller;
344 #gpio-cells = <2>;
345
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 };
349
350 gpio4: gpio@20084000 {
351 compatible = "rockchip,gpio-bank";
352 reg = <0x20084000 0x100>;
353 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cru PCLK_GPIO4>;
355
356 gpio-controller;
357 #gpio-cells = <2>;
358
359 interrupt-controller;
360 #interrupt-cells = <2>;
361 };
362
363 gpio6: gpio@2000a000 {
364 compatible = "rockchip,gpio-bank";
365 reg = <0x2000a000 0x100>;
366 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru PCLK_GPIO6>;
368
369 gpio-controller;
370 #gpio-cells = <2>;
371
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 pcfg_pull_default: pcfg-pull-default {
377 bias-pull-pin-default;
378 };
379
380 pcfg_pull_none: pcfg-pull-none {
381 bias-disable;
382 };
383
384 emac {
385 emac_xfer: emac-xfer {
386 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_none>, /* mac_clk */
387 <1 RK_PC1 2 &pcfg_pull_none>, /* tx_en */
388 <1 RK_PC2 2 &pcfg_pull_none>, /* txd1 */
389 <1 RK_PC3 2 &pcfg_pull_none>, /* txd0 */
390 <1 RK_PC4 2 &pcfg_pull_none>, /* rx_err */
391 <1 RK_PC5 2 &pcfg_pull_none>, /* crs_dvalid */
392 <1 RK_PC6 2 &pcfg_pull_none>, /* rxd1 */
393 <1 RK_PC7 2 &pcfg_pull_none>; /* rxd0 */
394 };
395
396 emac_mdio: emac-mdio {
397 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, /* mac_md */
398 <1 RK_PD1 2 &pcfg_pull_none>; /* mac_mdclk */
399 };
400 };
401
402 emmc {
403 emmc_clk: emmc-clk {
404 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_default>;
405 };
406
407 emmc_cmd: emmc-cmd {
408 rockchip,pins = <4 RK_PB1 2 &pcfg_pull_default>;
409 };
410
411 emmc_rst: emmc-rst {
412 rockchip,pins = <4 RK_PB2 2 &pcfg_pull_default>;
413 };
414
415 /*
416 * The data pins are shared between nandc and emmc and
417 * not accessible through pinctrl. Also they should've
418 * been already set correctly by firmware, as
419 * flash/emmc is the boot-device.
420 */
421 };
422
423 hdmi {
424 hdmi_hpd: hdmi-hpd {
425 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
426 };
427
428 hdmii2c_xfer: hdmii2c-xfer {
429 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
430 <0 RK_PA2 1 &pcfg_pull_none>;
431 };
432 };
433
434 i2c0 {
435 i2c0_xfer: i2c0-xfer {
436 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_none>,
437 <2 RK_PD5 1 &pcfg_pull_none>;
438 };
439 };
440
441 i2c1 {
442 i2c1_xfer: i2c1-xfer {
443 rockchip,pins = <2 RK_PD6 1 &pcfg_pull_none>,
444 <2 RK_PD7 1 &pcfg_pull_none>;
445 };
446 };
447
448 i2c2 {
449 i2c2_xfer: i2c2-xfer {
450 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>,
451 <3 RK_PA1 1 &pcfg_pull_none>;
452 };
453 };
454
455 i2c3 {
456 i2c3_xfer: i2c3-xfer {
457 rockchip,pins = <3 RK_PA2 2 &pcfg_pull_none>,
458 <3 RK_PA3 2 &pcfg_pull_none>;
459 };
460 };
461
462 i2c4 {
463 i2c4_xfer: i2c4-xfer {
464 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,
465 <3 RK_PA5 1 &pcfg_pull_none>;
466 };
467 };
468
469 pwm0 {
470 pwm0_out: pwm0-out {
471 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
472 };
473 };
474
475 pwm1 {
476 pwm1_out: pwm1-out {
477 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
478 };
479 };
480
481 pwm2 {
482 pwm2_out: pwm2-out {
483 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
484 };
485 };
486
487 pwm3 {
488 pwm3_out: pwm3-out {
489 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
490 };
491 };
492
493 spi0 {
494 spi0_clk: spi0-clk {
495 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_default>;
496 };
497 spi0_cs0: spi0-cs0 {
498 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_default>;
499 };
500 spi0_tx: spi0-tx {
501 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_default>;
502 };
503 spi0_rx: spi0-rx {
504 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_default>;
505 };
506 spi0_cs1: spi0-cs1 {
507 rockchip,pins = <4 RK_PB7 1 &pcfg_pull_default>;
508 };
509 };
510
511 spi1 {
512 spi1_clk: spi1-clk {
513 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_default>;
514 };
515 spi1_cs0: spi1-cs0 {
516 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_default>;
517 };
518 spi1_rx: spi1-rx {
519 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_default>;
520 };
521 spi1_tx: spi1-tx {
522 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_default>;
523 };
524 spi1_cs1: spi1-cs1 {
525 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_default>;
526 };
527 };
528
529 uart0 {
530 uart0_xfer: uart0-xfer {
531 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
532 <1 RK_PA1 1 &pcfg_pull_default>;
533 };
534
535 uart0_cts: uart0-cts {
536 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
537 };
538
539 uart0_rts: uart0-rts {
540 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
541 };
542 };
543
544 uart1 {
545 uart1_xfer: uart1-xfer {
546 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>,
547 <1 RK_PA5 1 &pcfg_pull_default>;
548 };
549
550 uart1_cts: uart1-cts {
551 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_default>;
552 };
553
554 uart1_rts: uart1-rts {
555 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
556 };
557 };
558
559 uart2 {
560 uart2_xfer: uart2-xfer {
561 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
562 <1 RK_PB1 1 &pcfg_pull_default>;
563 };
564 /* no rts / cts for uart2 */
565 };
566
567 uart3 {
568 uart3_xfer: uart3-xfer {
569 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>,
570 <3 RK_PD4 1 &pcfg_pull_default>;
571 };
572
573 uart3_cts: uart3-cts {
574 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_default>;
575 };
576
577 uart3_rts: uart3-rts {
578 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_default>;
579 };
580 };
581
582 sd0 {
583 sd0_clk: sd0-clk {
584 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_default>;
585 };
586
587 sd0_cmd: sd0-cmd {
588 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_default>;
589 };
590
591 sd0_cd: sd0-cd {
592 rockchip,pins = <3 RK_PB6 1 &pcfg_pull_default>;
593 };
594
595 sd0_wp: sd0-wp {
596 rockchip,pins = <3 RK_PB7 1 &pcfg_pull_default>;
597 };
598
599 sd0_bus1: sd0-bus-width1 {
600 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>;
601 };
602
603 sd0_bus4: sd0-bus-width4 {
604 rockchip,pins = <3 RK_PB2 1 &pcfg_pull_default>,
605 <3 RK_PB3 1 &pcfg_pull_default>,
606 <3 RK_PB4 1 &pcfg_pull_default>,
607 <3 RK_PB5 1 &pcfg_pull_default>;
608 };
609 };
610
611 sd1 {
612 sd1_clk: sd1-clk {
613 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_default>;
614 };
615
616 sd1_cmd: sd1-cmd {
617 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_default>;
618 };
619
620 sd1_cd: sd1-cd {
621 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_default>;
622 };
623
624 sd1_wp: sd1-wp {
625 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_default>;
626 };
627
628 sd1_bus1: sd1-bus-width1 {
629 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>;
630 };
631
632 sd1_bus4: sd1-bus-width4 {
633 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_default>,
634 <3 RK_PC2 1 &pcfg_pull_default>,
635 <3 RK_PC3 1 &pcfg_pull_default>,
636 <3 RK_PC4 1 &pcfg_pull_default>;
637 };
638 };
639
640 i2s0 {
641 i2s0_bus: i2s0-bus {
642 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_default>,
643 <0 RK_PB0 1 &pcfg_pull_default>,
644 <0 RK_PB1 1 &pcfg_pull_default>,
645 <0 RK_PB2 1 &pcfg_pull_default>,
646 <0 RK_PB3 1 &pcfg_pull_default>,
647 <0 RK_PB4 1 &pcfg_pull_default>,
648 <0 RK_PB5 1 &pcfg_pull_default>,
649 <0 RK_PB6 1 &pcfg_pull_default>,
650 <0 RK_PB7 1 &pcfg_pull_default>;
651 };
652 };
653
654 i2s1 {
655 i2s1_bus: i2s1-bus {
656 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
657 <0 RK_PC1 1 &pcfg_pull_default>,
658 <0 RK_PC2 1 &pcfg_pull_default>,
659 <0 RK_PC3 1 &pcfg_pull_default>,
660 <0 RK_PC4 1 &pcfg_pull_default>,
661 <0 RK_PC5 1 &pcfg_pull_default>;
662 };
663 };
664
665 i2s2 {
666 i2s2_bus: i2s2-bus {
667 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_default>,
668 <0 RK_PD1 1 &pcfg_pull_default>,
669 <0 RK_PD2 1 &pcfg_pull_default>,
670 <0 RK_PD3 1 &pcfg_pull_default>,
671 <0 RK_PD4 1 &pcfg_pull_default>,
672 <0 RK_PD5 1 &pcfg_pull_default>;
673 };
674 };
675 };
676 };
677
678 &gpu {
679 compatible = "rockchip,rk3066-mali", "arm,mali-400";
680 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
690 interrupt-names = "gp",
691 "gpmmu",
692 "pp0",
693 "ppmmu0",
694 "pp1",
695 "ppmmu1",
696 "pp2",
697 "ppmmu2",
698 "pp3",
699 "ppmmu3";
700 power-domains = <&power RK3066_PD_GPU>;
701 };
702
703 &grf {
704 compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
705
706 usbphy: usbphy {
707 compatible = "rockchip,rk3066a-usb-phy";
708 #address-cells = <1>;
709 #size-cells = <0>;
710 status = "disabled";
711
712 usbphy0: usb-phy@17c {
713 reg = <0x17c>;
714 clocks = <&cru SCLK_OTGPHY0>;
715 clock-names = "phyclk";
716 #clock-cells = <0>;
717 #phy-cells = <0>;
718 };
719
720 usbphy1: usb-phy@188 {
721 reg = <0x188>;
722 clocks = <&cru SCLK_OTGPHY1>;
723 clock-names = "phyclk";
724 #clock-cells = <0>;
725 #phy-cells = <0>;
726 };
727 };
728 };
729
730 &i2c0 {
731 pinctrl-names = "default";
732 pinctrl-0 = <&i2c0_xfer>;
733 };
734
735 &i2c1 {
736 pinctrl-names = "default";
737 pinctrl-0 = <&i2c1_xfer>;
738 };
739
740 &i2c2 {
741 pinctrl-names = "default";
742 pinctrl-0 = <&i2c2_xfer>;
743 };
744
745 &i2c3 {
746 pinctrl-names = "default";
747 pinctrl-0 = <&i2c3_xfer>;
748 };
749
750 &i2c4 {
751 pinctrl-names = "default";
752 pinctrl-0 = <&i2c4_xfer>;
753 };
754
755 &mmc0 {
756 clock-frequency = <50000000>;
757 dmas = <&dmac2 1>;
758 dma-names = "rx-tx";
759 max-frequency = <50000000>;
760 pinctrl-names = "default";
761 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
762 };
763
764 &mmc1 {
765 dmas = <&dmac2 3>;
766 dma-names = "rx-tx";
767 pinctrl-names = "default";
768 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
769 };
770
771 &emmc {
772 dmas = <&dmac2 4>;
773 dma-names = "rx-tx";
774 };
775
776 &pmu {
777 power: power-controller {
778 compatible = "rockchip,rk3066-power-controller";
779 #power-domain-cells = <1>;
780 #address-cells = <1>;
781 #size-cells = <0>;
782
783 power-domain@RK3066_PD_VIO {
784 reg = <RK3066_PD_VIO>;
785 clocks = <&cru ACLK_LCDC0>,
786 <&cru ACLK_LCDC1>,
787 <&cru DCLK_LCDC0>,
788 <&cru DCLK_LCDC1>,
789 <&cru HCLK_LCDC0>,
790 <&cru HCLK_LCDC1>,
791 <&cru SCLK_CIF1>,
792 <&cru ACLK_CIF1>,
793 <&cru HCLK_CIF1>,
794 <&cru SCLK_CIF0>,
795 <&cru ACLK_CIF0>,
796 <&cru HCLK_CIF0>,
797 <&cru HCLK_HDMI>,
798 <&cru ACLK_IPP>,
799 <&cru HCLK_IPP>,
800 <&cru ACLK_RGA>,
801 <&cru HCLK_RGA>;
802 pm_qos = <&qos_lcdc0>,
803 <&qos_lcdc1>,
804 <&qos_cif0>,
805 <&qos_cif1>,
806 <&qos_ipp>,
807 <&qos_rga>;
808 #power-domain-cells = <0>;
809 };
810
811 power-domain@RK3066_PD_VIDEO {
812 reg = <RK3066_PD_VIDEO>;
813 clocks = <&cru ACLK_VDPU>,
814 <&cru ACLK_VEPU>,
815 <&cru HCLK_VDPU>,
816 <&cru HCLK_VEPU>;
817 pm_qos = <&qos_vpu>;
818 #power-domain-cells = <0>;
819 };
820
821 power-domain@RK3066_PD_GPU {
822 reg = <RK3066_PD_GPU>;
823 clocks = <&cru ACLK_GPU>;
824 pm_qos = <&qos_gpu>;
825 #power-domain-cells = <0>;
826 };
827 };
828 };
829
830 &pwm0 {
831 pinctrl-names = "default";
832 pinctrl-0 = <&pwm0_out>;
833 };
834
835 &pwm1 {
836 pinctrl-names = "default";
837 pinctrl-0 = <&pwm1_out>;
838 };
839
840 &pwm2 {
841 pinctrl-names = "default";
842 pinctrl-0 = <&pwm2_out>;
843 };
844
845 &pwm3 {
846 pinctrl-names = "default";
847 pinctrl-0 = <&pwm3_out>;
848 };
849
850 &spi0 {
851 pinctrl-names = "default";
852 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
853 };
854
855 &spi1 {
856 pinctrl-names = "default";
857 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
858 };
859
860 &uart0 {
861 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
862 dmas = <&dmac1_s 0>, <&dmac1_s 1>;
863 dma-names = "tx", "rx";
864 pinctrl-names = "default";
865 pinctrl-0 = <&uart0_xfer>;
866 };
867
868 &uart1 {
869 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
870 dmas = <&dmac1_s 2>, <&dmac1_s 3>;
871 dma-names = "tx", "rx";
872 pinctrl-names = "default";
873 pinctrl-0 = <&uart1_xfer>;
874 };
875
876 &uart2 {
877 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
878 dmas = <&dmac2 6>, <&dmac2 7>;
879 dma-names = "tx", "rx";
880 pinctrl-names = "default";
881 pinctrl-0 = <&uart2_xfer>;
882 };
883
884 &uart3 {
885 compatible = "rockchip,rk3066-uart", "snps,dw-apb-uart";
886 dmas = <&dmac2 8>, <&dmac2 9>;
887 dma-names = "tx", "rx";
888 pinctrl-names = "default";
889 pinctrl-0 = <&uart3_xfer>;
890 };
891
892 &vpu {
893 power-domains = <&power RK3066_PD_VIDEO>;
894 };
895
896 &wdt {
897 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
898 };
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