1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
12
13 / {
14 compatible = "rockchip,rk3128";
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 gpio3 = &gpio3;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 };
32
33 arm-pmu {
34 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
39 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45 enable-method = "rockchip,rk3036-smp";
46
47 cpu0: cpu@f00 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a7";
50 reg = <0xf00>;
51 clock-latency = <40000>;
52 clocks = <&cru ARMCLK>;
53 resets = <&cru SRST_CORE0>;
54 operating-points-v2 = <&cpu_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 };
57
58 cpu1: cpu@f01 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a7";
61 reg = <0xf01>;
62 resets = <&cru SRST_CORE1>;
63 operating-points-v2 = <&cpu_opp_table>;
64 };
65
66 cpu2: cpu@f02 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a7";
69 reg = <0xf02>;
70 resets = <&cru SRST_CORE2>;
71 operating-points-v2 = <&cpu_opp_table>;
72 };
73
74 cpu3: cpu@f03 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <0xf03>;
78 resets = <&cru SRST_CORE3>;
79 operating-points-v2 = <&cpu_opp_table>;
80 };
81 };
82
83 cpu_opp_table: opp-table-0 {
84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp-216000000 {
88 opp-hz = /bits/ 64 <216000000>;
89 opp-microvolt = <950000 950000 1325000>;
90 };
91 opp-408000000 {
92 opp-hz = /bits/ 64 <408000000>;
93 opp-microvolt = <950000 950000 1325000>;
94 };
95 opp-600000000 {
96 opp-hz = /bits/ 64 <600000000>;
97 opp-microvolt = <950000 950000 1325000>;
98 };
99 opp-696000000 {
100 opp-hz = /bits/ 64 <696000000>;
101 opp-microvolt = <975000 975000 1325000>;
102 };
103 opp-816000000 {
104 opp-hz = /bits/ 64 <816000000>;
105 opp-microvolt = <1075000 1075000 1325000>;
106 opp-suspend;
107 };
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <1200000 1200000 1325000>;
111 };
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <1325000 1325000 1325000>;
115 };
116 };
117
118 display_subsystem: display-subsystem {
119 compatible = "rockchip,display-subsystem";
120 ports = <&vop_out>;
121 status = "disabled";
122 };
123
124 gpu_opp_table: opp-table-1 {
125 compatible = "operating-points-v2";
126
127 opp-200000000 {
128 opp-hz = /bits/ 64 <200000000>;
129 opp-microvolt = <975000 975000 1250000>;
130 };
131 opp-300000000 {
132 opp-hz = /bits/ 64 <300000000>;
133 opp-microvolt = <1050000 1050000 1250000>;
134 };
135 opp-400000000 {
136 opp-hz = /bits/ 64 <400000000>;
137 opp-microvolt = <1150000 1150000 1250000>;
138 };
139 opp-480000000 {
140 opp-hz = /bits/ 64 <480000000>;
141 opp-microvolt = <1250000 1250000 1250000>;
142 };
143 };
144
145 timer {
146 compatible = "arm,armv7-timer";
147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
151 arm,cpu-registers-not-fw-configured;
152 clock-frequency = <24000000>;
153 };
154
155 xin24m: oscillator {
156 compatible = "fixed-clock";
157 clock-frequency = <24000000>;
158 clock-output-names = "xin24m";
159 #clock-cells = <0>;
160 };
161
162 imem: sram@10080000 {
163 compatible = "mmio-sram";
164 reg = <0x10080000 0x2000>;
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0 0x10080000 0x2000>;
168
169 smp-sram@0 {
170 compatible = "rockchip,rk3066-smp-sram";
171 reg = <0x00 0x10>;
172 };
173 };
174
175 gpu: gpu@10090000 {
176 compatible = "rockchip,rk3128-mali", "arm,mali-400";
177 reg = <0x10090000 0x10000>;
178 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "gp",
185 "gpmmu",
186 "pp0",
187 "ppmmu0",
188 "pp1",
189 "ppmmu1";
190 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
191 clock-names = "bus", "core";
192 operating-points-v2 = <&gpu_opp_table>;
193 resets = <&cru SRST_GPU>;
194 power-domains = <&power RK3128_PD_GPU>;
195 status = "disabled";
196 };
197
198 pmu: syscon@100a0000 {
199 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
200 reg = <0x100a0000 0x1000>;
201
202 power: power-controller {
203 compatible = "rockchip,rk3128-power-controller";
204 #power-domain-cells = <1>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 power-domain@RK3128_PD_VIO {
209 reg = <RK3128_PD_VIO>;
210 clocks = <&cru ACLK_CIF>,
211 <&cru HCLK_CIF>,
212 <&cru DCLK_EBC>,
213 <&cru HCLK_EBC>,
214 <&cru ACLK_IEP>,
215 <&cru HCLK_IEP>,
216 <&cru ACLK_LCDC0>,
217 <&cru HCLK_LCDC0>,
218 <&cru PCLK_MIPI>,
219 <&cru PCLK_MIPIPHY>,
220 <&cru SCLK_MIPI_24M>,
221 <&cru ACLK_RGA>,
222 <&cru HCLK_RGA>,
223 <&cru ACLK_VIO0>,
224 <&cru ACLK_VIO1>,
225 <&cru HCLK_VIO>,
226 <&cru HCLK_VIO_H2P>,
227 <&cru DCLK_VOP>,
228 <&cru SCLK_VOP>;
229 pm_qos = <&qos_ebc>,
230 <&qos_iep>,
231 <&qos_lcdc>,
232 <&qos_rga>,
233 <&qos_vip>;
234 #power-domain-cells = <0>;
235 };
236
237 power-domain@RK3128_PD_VIDEO {
238 reg = <RK3128_PD_VIDEO>;
239 clocks = <&cru ACLK_VDPU>,
240 <&cru HCLK_VDPU>,
241 <&cru ACLK_VEPU>,
242 <&cru HCLK_VEPU>,
243 <&cru SCLK_HEVC_CORE>;
244 pm_qos = <&qos_vpu>;
245 #power-domain-cells = <0>;
246 };
247
248 power-domain@RK3128_PD_GPU {
249 reg = <RK3128_PD_GPU>;
250 clocks = <&cru ACLK_GPU>;
251 pm_qos = <&qos_gpu>;
252 #power-domain-cells = <0>;
253 };
254 };
255 };
256
257 vop: vop@1010e000 {
258 compatible = "rockchip,rk3126-vop";
259 reg = <0x1010e000 0x300>;
260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
262 <&cru HCLK_LCDC0>;
263 clock-names = "aclk_vop", "dclk_vop",
264 "hclk_vop";
265 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
266 <&cru SRST_VOP_D>;
267 reset-names = "axi", "ahb",
268 "dclk";
269 power-domains = <&power RK3128_PD_VIO>;
270 status = "disabled";
271
272 vop_out: port {
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 vop_out_hdmi: endpoint@0 {
277 reg = <0>;
278 remote-endpoint = <&hdmi_in_vop>;
279 };
280
281 vop_out_dsi: endpoint@1 {
282 reg = <1>;
283 remote-endpoint = <&dsi_in_vop>;
284 };
285 };
286 };
287
288 dsi: dsi@10110000 {
289 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
290 reg = <0x10110000 0x4000>;
291 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_MIPI>;
293 clock-names = "pclk";
294 phys = <&dphy>;
295 phy-names = "dphy";
296 power-domains = <&power RK3128_PD_VIO>;
297 resets = <&cru SRST_VIO_MIPI_DSI>;
298 reset-names = "apb";
299 rockchip,grf = <&grf>;
300 status = "disabled";
301
302 ports {
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 dsi_in: port@0 {
307 reg = <0>;
308
309 dsi_in_vop: endpoint {
310 remote-endpoint = <&vop_out_dsi>;
311 };
312 };
313
314 dsi_out: port@1 {
315 reg = <1>;
316 };
317 };
318 };
319
320 qos_gpu: qos@1012d000 {
321 compatible = "rockchip,rk3128-qos", "syscon";
322 reg = <0x1012d000 0x20>;
323 };
324
325 qos_vpu: qos@1012e000 {
326 compatible = "rockchip,rk3128-qos", "syscon";
327 reg = <0x1012e000 0x20>;
328 };
329
330 qos_rga: qos@1012f000 {
331 compatible = "rockchip,rk3128-qos", "syscon";
332 reg = <0x1012f000 0x20>;
333 };
334
335 qos_ebc: qos@1012f080 {
336 compatible = "rockchip,rk3128-qos", "syscon";
337 reg = <0x1012f080 0x20>;
338 };
339
340 qos_iep: qos@1012f100 {
341 compatible = "rockchip,rk3128-qos", "syscon";
342 reg = <0x1012f100 0x20>;
343 };
344
345 qos_lcdc: qos@1012f180 {
346 compatible = "rockchip,rk3128-qos", "syscon";
347 reg = <0x1012f180 0x20>;
348 };
349
350 qos_vip: qos@1012f200 {
351 compatible = "rockchip,rk3128-qos", "syscon";
352 reg = <0x1012f200 0x20>;
353 };
354
355 gic: interrupt-controller@10139000 {
356 compatible = "arm,cortex-a7-gic";
357 reg = <0x10139000 0x1000>,
358 <0x1013a000 0x1000>,
359 <0x1013c000 0x2000>,
360 <0x1013e000 0x2000>;
361 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
362 interrupt-controller;
363 #interrupt-cells = <3>;
364 #address-cells = <0>;
365 };
366
367 usb_otg: usb@10180000 {
368 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
369 reg = <0x10180000 0x40000>;
370 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cru HCLK_OTG>;
372 clock-names = "otg";
373 dr_mode = "otg";
374 g-np-tx-fifo-size = <16>;
375 g-rx-fifo-size = <280>;
376 g-tx-fifo-size = <256 128 128 64 32 16>;
377 phys = <&usb2phy_otg>;
378 phy-names = "usb2-phy";
379 status = "disabled";
380 };
381
382 usb_host_ehci: usb@101c0000 {
383 compatible = "generic-ehci";
384 reg = <0x101c0000 0x20000>;
385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&cru HCLK_HOST2>;
387 phys = <&usb2phy_host>;
388 phy-names = "usb";
389 status = "disabled";
390 };
391
392 usb_host_ohci: usb@101e0000 {
393 compatible = "generic-ohci";
394 reg = <0x101e0000 0x20000>;
395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru HCLK_HOST2>;
397 phys = <&usb2phy_host>;
398 phy-names = "usb";
399 status = "disabled";
400 };
401
402 i2s_8ch: i2s@10200000 {
403 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
404 reg = <0x10200000 0x1000>;
405 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>;
407 clock-names = "i2s_clk", "i2s_hclk";
408 dmas = <&pdma 14>, <&pdma 15>;
409 dma-names = "tx", "rx";
410 #sound-dai-cells = <0>;
411 status = "disabled";
412 };
413
414 spdif: spdif@10204000 {
415 compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif";
416 reg = <0x10204000 0x1000>;
417 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
419 clock-names = "mclk", "hclk";
420 dmas = <&pdma 13>;
421 dma-names = "tx";
422 pinctrl-names = "default";
423 pinctrl-0 = <&spdif_tx>;
424 #sound-dai-cells = <0>;
425 status = "disabled";
426 };
427
428 sfc: spi@1020c000 {
429 compatible = "rockchip,sfc";
430 reg = <0x1020c000 0x8000>;
431 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru SCLK_SFC>, <&cru 479>;
433 clock-names = "clk_sfc", "hclk_sfc";
434 status = "disabled";
435 };
436
437 sdmmc: mmc@10214000 {
438 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
439 reg = <0x10214000 0x4000>;
440 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
442 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
443 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
444 dmas = <&pdma 10>;
445 dma-names = "rx-tx";
446 fifo-depth = <256>;
447 max-frequency = <150000000>;
448 resets = <&cru SRST_SDMMC>;
449 reset-names = "reset";
450 status = "disabled";
451 };
452
453 sdio: mmc@10218000 {
454 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
455 reg = <0x10218000 0x4000>;
456 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
458 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
459 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
460 dmas = <&pdma 11>;
461 dma-names = "rx-tx";
462 fifo-depth = <256>;
463 max-frequency = <150000000>;
464 resets = <&cru SRST_SDIO>;
465 reset-names = "reset";
466 status = "disabled";
467 };
468
469 emmc: mmc@1021c000 {
470 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
471 reg = <0x1021c000 0x4000>;
472 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
474 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
475 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
476 dmas = <&pdma 12>;
477 dma-names = "rx-tx";
478 fifo-depth = <256>;
479 max-frequency = <150000000>;
480 resets = <&cru SRST_EMMC>;
481 reset-names = "reset";
482 status = "disabled";
483 };
484
485 i2s_2ch: i2s@10220000 {
486 compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s";
487 reg = <0x10220000 0x1000>;
488 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>;
490 clock-names = "i2s_clk", "i2s_hclk";
491 dmas = <&pdma 0>, <&pdma 1>;
492 dma-names = "tx", "rx";
493 rockchip,playback-channels = <2>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&i2s_bus>;
496 #sound-dai-cells = <0>;
497 status = "disabled";
498 };
499
500 nfc: nand-controller@10500000 {
501 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
502 reg = <0x10500000 0x4000>;
503 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
505 clock-names = "ahb", "nfc";
506 pinctrl-names = "default";
507 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
508 &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
509 status = "disabled";
510 };
511
512 cru: clock-controller@20000000 {
513 compatible = "rockchip,rk3128-cru";
514 reg = <0x20000000 0x1000>;
515 clocks = <&xin24m>;
516 clock-names = "xin24m";
517 rockchip,grf = <&grf>;
518 #clock-cells = <1>;
519 #reset-cells = <1>;
520 assigned-clocks = <&cru PLL_GPLL>;
521 assigned-clock-rates = <594000000>;
522 };
523
524 grf: syscon@20008000 {
525 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
526 reg = <0x20008000 0x1000>;
527 #address-cells = <1>;
528 #size-cells = <1>;
529
530 usb2phy: usb2phy@17c {
531 compatible = "rockchip,rk3128-usb2phy";
532 reg = <0x017c 0x0c>;
533 clocks = <&cru SCLK_OTGPHY0>;
534 clock-names = "phyclk";
535 clock-output-names = "usb480m_phy";
536 assigned-clocks = <&cru SCLK_USB480M>;
537 assigned-clock-parents = <&usb2phy>;
538 #clock-cells = <0>;
539 status = "disabled";
540
541 usb2phy_host: host-port {
542 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
543 interrupt-names = "linestate";
544 #phy-cells = <0>;
545 status = "disabled";
546 };
547
548 usb2phy_otg: otg-port {
549 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "otg-bvalid", "otg-id",
553 "linestate";
554 #phy-cells = <0>;
555 status = "disabled";
556 };
557 };
558 };
559
560 hdmi: hdmi@20034000 {
561 compatible = "rockchip,rk3128-inno-hdmi";
562 reg = <0x20034000 0x4000>;
563 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
565 clock-names = "pclk", "ref";
566 pinctrl-names = "default";
567 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
568 power-domains = <&power RK3128_PD_VIO>;
569 #sound-dai-cells = <0>;
570 status = "disabled";
571
572 ports {
573 #address-cells = <1>;
574 #size-cells = <0>;
575
576 hdmi_in: port@0 {
577 reg = <0>;
578 hdmi_in_vop: endpoint {
579 remote-endpoint = <&vop_out_hdmi>;
580 };
581 };
582
583 hdmi_out: port@1 {
584 reg = <1>;
585 };
586 };
587 };
588
589 dphy: phy@20038000 {
590 compatible = "rockchip,rk3128-dsi-dphy";
591 reg = <0x20038000 0x4000>;
592 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>;
593 clock-names = "ref", "pclk";
594 #phy-cells = <0>;
595 power-domains = <&power RK3128_PD_VIO>;
596 resets = <&cru SRST_MIPIPHY_P>;
597 reset-names = "apb";
598 status = "disabled";
599 };
600
601 timer0: timer@20044000 {
602 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
603 reg = <0x20044000 0x20>;
604 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
606 clock-names = "pclk", "timer";
607 };
608
609 timer1: timer@20044020 {
610 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
611 reg = <0x20044020 0x20>;
612 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
614 clock-names = "pclk", "timer";
615 };
616
617 timer2: timer@20044040 {
618 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
619 reg = <0x20044040 0x20>;
620 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
622 clock-names = "pclk", "timer";
623 };
624
625 timer3: timer@20044060 {
626 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
627 reg = <0x20044060 0x20>;
628 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
630 clock-names = "pclk", "timer";
631 };
632
633 timer4: timer@20044080 {
634 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
635 reg = <0x20044080 0x20>;
636 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
638 clock-names = "pclk", "timer";
639 };
640
641 timer5: timer@200440a0 {
642 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
643 reg = <0x200440a0 0x20>;
644 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
646 clock-names = "pclk", "timer";
647 };
648
649 watchdog: watchdog@2004c000 {
650 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
651 reg = <0x2004c000 0x100>;
652 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&cru PCLK_WDT>;
654 status = "disabled";
655 };
656
657 pwm0: pwm@20050000 {
658 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
659 reg = <0x20050000 0x10>;
660 clocks = <&cru PCLK_PWM>;
661 pinctrl-names = "default";
662 pinctrl-0 = <&pwm0_pin>;
663 #pwm-cells = <3>;
664 status = "disabled";
665 };
666
667 pwm1: pwm@20050010 {
668 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
669 reg = <0x20050010 0x10>;
670 clocks = <&cru PCLK_PWM>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm1_pin>;
673 #pwm-cells = <3>;
674 status = "disabled";
675 };
676
677 pwm2: pwm@20050020 {
678 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
679 reg = <0x20050020 0x10>;
680 clocks = <&cru PCLK_PWM>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&pwm2_pin>;
683 #pwm-cells = <3>;
684 status = "disabled";
685 };
686
687 pwm3: pwm@20050030 {
688 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
689 reg = <0x20050030 0x10>;
690 clocks = <&cru PCLK_PWM>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pwm3_pin>;
693 #pwm-cells = <3>;
694 status = "disabled";
695 };
696
697 i2c1: i2c@20056000 {
698 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
699 reg = <0x20056000 0x1000>;
700 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
701 clock-names = "i2c";
702 clocks = <&cru PCLK_I2C1>;
703 pinctrl-names = "default";
704 pinctrl-0 = <&i2c1_xfer>;
705 #address-cells = <1>;
706 #size-cells = <0>;
707 status = "disabled";
708 };
709
710 i2c2: i2c@2005a000 {
711 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
712 reg = <0x2005a000 0x1000>;
713 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
714 clock-names = "i2c";
715 clocks = <&cru PCLK_I2C2>;
716 pinctrl-names = "default";
717 pinctrl-0 = <&i2c2_xfer>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 status = "disabled";
721 };
722
723 i2c3: i2c@2005e000 {
724 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
725 reg = <0x2005e000 0x1000>;
726 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
727 clock-names = "i2c";
728 clocks = <&cru PCLK_I2C3>;
729 pinctrl-names = "default";
730 pinctrl-0 = <&i2c3_xfer>;
731 #address-cells = <1>;
732 #size-cells = <0>;
733 status = "disabled";
734 };
735
736 uart0: serial@20060000 {
737 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
738 reg = <0x20060000 0x100>;
739 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
740 clock-frequency = <24000000>;
741 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
742 clock-names = "baudclk", "apb_pclk";
743 dmas = <&pdma 2>, <&pdma 3>;
744 dma-names = "tx", "rx";
745 pinctrl-names = "default";
746 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
747 reg-io-width = <4>;
748 reg-shift = <2>;
749 status = "disabled";
750 };
751
752 uart1: serial@20064000 {
753 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
754 reg = <0x20064000 0x100>;
755 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
756 clock-frequency = <24000000>;
757 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
758 clock-names = "baudclk", "apb_pclk";
759 dmas = <&pdma 4>, <&pdma 5>;
760 dma-names = "tx", "rx";
761 pinctrl-names = "default";
762 pinctrl-0 = <&uart1_xfer>;
763 reg-io-width = <4>;
764 reg-shift = <2>;
765 status = "disabled";
766 };
767
768 uart2: serial@20068000 {
769 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
770 reg = <0x20068000 0x100>;
771 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
772 clock-frequency = <24000000>;
773 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
774 clock-names = "baudclk", "apb_pclk";
775 dmas = <&pdma 6>, <&pdma 7>;
776 dma-names = "tx", "rx";
777 pinctrl-names = "default";
778 pinctrl-0 = <&uart2_xfer>;
779 reg-io-width = <4>;
780 reg-shift = <2>;
781 status = "disabled";
782 };
783
784 saradc: saradc@2006c000 {
785 compatible = "rockchip,saradc";
786 reg = <0x2006c000 0x100>;
787 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
789 clock-names = "saradc", "apb_pclk";
790 resets = <&cru SRST_SARADC>;
791 reset-names = "saradc-apb";
792 #io-channel-cells = <1>;
793 status = "disabled";
794 };
795
796 i2c0: i2c@20072000 {
797 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
798 reg = <0x20072000 0x1000>;
799 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
800 clock-names = "i2c";
801 clocks = <&cru PCLK_I2C0>;
802 pinctrl-names = "default";
803 pinctrl-0 = <&i2c0_xfer>;
804 #address-cells = <1>;
805 #size-cells = <0>;
806 status = "disabled";
807 };
808
809 spi0: spi@20074000 {
810 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
811 reg = <0x20074000 0x1000>;
812 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
814 clock-names = "spiclk", "apb_pclk";
815 dmas = <&pdma 8>, <&pdma 9>;
816 dma-names = "tx", "rx";
817 pinctrl-names = "default";
818 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
819 #address-cells = <1>;
820 #size-cells = <0>;
821 status = "disabled";
822 };
823
824 pdma: dma-controller@20078000 {
825 compatible = "arm,pl330", "arm,primecell";
826 reg = <0x20078000 0x4000>;
827 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
829 arm,pl330-broken-no-flushp;
830 arm,pl330-periph-burst;
831 clocks = <&cru ACLK_DMAC>;
832 clock-names = "apb_pclk";
833 #dma-cells = <1>;
834 };
835
836 gmac: ethernet@2008c000 {
837 compatible = "rockchip,rk3128-gmac";
838 reg = <0x2008c000 0x4000>;
839 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "macirq", "eth_wake_irq";
842 clocks = <&cru SCLK_MAC>,
843 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
844 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
845 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
846 clock-names = "stmmaceth",
847 "mac_clk_rx", "mac_clk_tx",
848 "clk_mac_ref", "clk_mac_refout",
849 "aclk_mac", "pclk_mac";
850 resets = <&cru SRST_GMAC>;
851 reset-names = "stmmaceth";
852 rockchip,grf = <&grf>;
853 rx-fifo-depth = <4096>;
854 tx-fifo-depth = <2048>;
855 status = "disabled";
856
857 mdio: mdio {
858 compatible = "snps,dwmac-mdio";
859 #address-cells = <0x1>;
860 #size-cells = <0x0>;
861 };
862 };
863
864 pinctrl: pinctrl {
865 compatible = "rockchip,rk3128-pinctrl";
866 rockchip,grf = <&grf>;
867 #address-cells = <1>;
868 #size-cells = <1>;
869 ranges;
870
871 gpio0: gpio@2007c000 {
872 compatible = "rockchip,gpio-bank";
873 reg = <0x2007c000 0x100>;
874 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&cru PCLK_GPIO0>;
876 gpio-controller;
877 #gpio-cells = <2>;
878 interrupt-controller;
879 #interrupt-cells = <2>;
880 };
881
882 gpio1: gpio@20080000 {
883 compatible = "rockchip,gpio-bank";
884 reg = <0x20080000 0x100>;
885 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&cru PCLK_GPIO1>;
887 gpio-controller;
888 #gpio-cells = <2>;
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 };
892
893 gpio2: gpio@20084000 {
894 compatible = "rockchip,gpio-bank";
895 reg = <0x20084000 0x100>;
896 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&cru PCLK_GPIO2>;
898 gpio-controller;
899 #gpio-cells = <2>;
900 interrupt-controller;
901 #interrupt-cells = <2>;
902 };
903
904 gpio3: gpio@20088000 {
905 compatible = "rockchip,gpio-bank";
906 reg = <0x20088000 0x100>;
907 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&cru PCLK_GPIO3>;
909 gpio-controller;
910 #gpio-cells = <2>;
911 interrupt-controller;
912 #interrupt-cells = <2>;
913 };
914
915 pcfg_pull_default: pcfg-pull-default {
916 bias-pull-pin-default;
917 };
918
919 pcfg_pull_none: pcfg-pull-none {
920 bias-disable;
921 };
922
923 emmc {
924 emmc_clk: emmc-clk {
925 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
926 };
927
928 emmc_cmd: emmc-cmd {
929 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
930 };
931
932 emmc_cmd1: emmc-cmd1 {
933 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
934 };
935
936 emmc_pwr: emmc-pwr {
937 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
938 };
939
940 emmc_bus1: emmc-bus1 {
941 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
942 };
943
944 emmc_bus4: emmc-bus4 {
945 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
946 <1 RK_PD1 2 &pcfg_pull_default>,
947 <1 RK_PD2 2 &pcfg_pull_default>,
948 <1 RK_PD3 2 &pcfg_pull_default>;
949 };
950
951 emmc_bus8: emmc-bus8 {
952 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
953 <1 RK_PD1 2 &pcfg_pull_default>,
954 <1 RK_PD2 2 &pcfg_pull_default>,
955 <1 RK_PD3 2 &pcfg_pull_default>,
956 <1 RK_PD4 2 &pcfg_pull_default>,
957 <1 RK_PD5 2 &pcfg_pull_default>,
958 <1 RK_PD6 2 &pcfg_pull_default>,
959 <1 RK_PD7 2 &pcfg_pull_default>;
960 };
961 };
962
963 gmac {
964 rgmii_pins: rgmii-pins {
965 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
966 <2 RK_PB1 3 &pcfg_pull_default>,
967 <2 RK_PB3 3 &pcfg_pull_default>,
968 <2 RK_PB4 3 &pcfg_pull_default>,
969 <2 RK_PB5 3 &pcfg_pull_default>,
970 <2 RK_PB6 3 &pcfg_pull_default>,
971 <2 RK_PC0 3 &pcfg_pull_default>,
972 <2 RK_PC1 3 &pcfg_pull_default>,
973 <2 RK_PC2 3 &pcfg_pull_default>,
974 <2 RK_PC3 3 &pcfg_pull_default>,
975 <2 RK_PD1 3 &pcfg_pull_default>,
976 <2 RK_PC4 4 &pcfg_pull_default>,
977 <2 RK_PC5 4 &pcfg_pull_default>,
978 <2 RK_PC6 4 &pcfg_pull_default>,
979 <2 RK_PC7 4 &pcfg_pull_default>;
980 };
981
982 rmii_pins: rmii-pins {
983 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
984 <2 RK_PB4 3 &pcfg_pull_default>,
985 <2 RK_PB5 3 &pcfg_pull_default>,
986 <2 RK_PB6 3 &pcfg_pull_default>,
987 <2 RK_PB7 3 &pcfg_pull_default>,
988 <2 RK_PC0 3 &pcfg_pull_default>,
989 <2 RK_PC1 3 &pcfg_pull_default>,
990 <2 RK_PC2 3 &pcfg_pull_default>,
991 <2 RK_PC3 3 &pcfg_pull_default>,
992 <2 RK_PD1 3 &pcfg_pull_default>;
993 };
994 };
995
996 hdmi {
997 hdmii2c_xfer: hdmii2c-xfer {
998 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
999 <0 RK_PA7 2 &pcfg_pull_none>;
1000 };
1001
1002 hdmi_hpd: hdmi-hpd {
1003 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
1004 };
1005
1006 hdmi_cec: hdmi-cec {
1007 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1008 };
1009 };
1010
1011 i2c0 {
1012 i2c0_xfer: i2c0-xfer {
1013 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1014 <0 RK_PA1 1 &pcfg_pull_none>;
1015 };
1016 };
1017
1018 i2c1 {
1019 i2c1_xfer: i2c1-xfer {
1020 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1021 <0 RK_PA3 1 &pcfg_pull_none>;
1022 };
1023 };
1024
1025 i2c2 {
1026 i2c2_xfer: i2c2-xfer {
1027 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
1028 <2 RK_PC5 3 &pcfg_pull_none>;
1029 };
1030 };
1031
1032 i2c3 {
1033 i2c3_xfer: i2c3-xfer {
1034 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1035 <0 RK_PA7 1 &pcfg_pull_none>;
1036 };
1037 };
1038
1039 i2s {
1040 i2s_bus: i2s-bus {
1041 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1042 <0 RK_PB1 1 &pcfg_pull_none>,
1043 <0 RK_PB3 1 &pcfg_pull_none>,
1044 <0 RK_PB4 1 &pcfg_pull_none>,
1045 <0 RK_PB5 1 &pcfg_pull_none>,
1046 <0 RK_PB6 1 &pcfg_pull_none>;
1047 };
1048
1049 i2s1_bus: i2s1-bus {
1050 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
1051 <1 RK_PA1 1 &pcfg_pull_none>,
1052 <1 RK_PA2 1 &pcfg_pull_none>,
1053 <1 RK_PA3 1 &pcfg_pull_none>,
1054 <1 RK_PA4 1 &pcfg_pull_none>,
1055 <1 RK_PA5 1 &pcfg_pull_none>;
1056 };
1057 };
1058
1059 lcdc {
1060 lcdc_dclk: lcdc-dclk {
1061 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
1062 };
1063
1064 lcdc_den: lcdc-den {
1065 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
1066 };
1067
1068 lcdc_hsync: lcdc-hsync {
1069 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1070 };
1071
1072 lcdc_vsync: lcdc-vsync {
1073 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
1074 };
1075
1076 lcdc_rgb24: lcdc-rgb24 {
1077 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1078 <2 RK_PB5 1 &pcfg_pull_none>,
1079 <2 RK_PB6 1 &pcfg_pull_none>,
1080 <2 RK_PB7 1 &pcfg_pull_none>,
1081 <2 RK_PC0 1 &pcfg_pull_none>,
1082 <2 RK_PC1 1 &pcfg_pull_none>,
1083 <2 RK_PC2 1 &pcfg_pull_none>,
1084 <2 RK_PC3 1 &pcfg_pull_none>,
1085 <2 RK_PC4 1 &pcfg_pull_none>,
1086 <2 RK_PC5 1 &pcfg_pull_none>,
1087 <2 RK_PC6 1 &pcfg_pull_none>,
1088 <2 RK_PC7 1 &pcfg_pull_none>,
1089 <2 RK_PD0 1 &pcfg_pull_none>,
1090 <2 RK_PD1 1 &pcfg_pull_none>;
1091 };
1092 };
1093
1094 nfc {
1095 flash_ale: flash-ale {
1096 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
1097 };
1098
1099 flash_cle: flash-cle {
1100 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
1101 };
1102
1103 flash_wrn: flash-wrn {
1104 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1105 };
1106
1107 flash_rdn: flash-rdn {
1108 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
1109 };
1110
1111 flash_rdy: flash-rdy {
1112 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1113 };
1114
1115 flash_cs0: flash-cs0 {
1116 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1117 };
1118
1119 flash_dqs: flash-dqs {
1120 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
1121 };
1122
1123 flash_bus8: flash-bus8 {
1124 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1125 <1 RK_PD1 1 &pcfg_pull_none>,
1126 <1 RK_PD2 1 &pcfg_pull_none>,
1127 <1 RK_PD3 1 &pcfg_pull_none>,
1128 <1 RK_PD4 1 &pcfg_pull_none>,
1129 <1 RK_PD5 1 &pcfg_pull_none>,
1130 <1 RK_PD6 1 &pcfg_pull_none>,
1131 <1 RK_PD7 1 &pcfg_pull_none>;
1132 };
1133 };
1134
1135 pwm0 {
1136 pwm0_pin: pwm0-pin {
1137 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
1138 };
1139 };
1140
1141 pwm1 {
1142 pwm1_pin: pwm1-pin {
1143 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1144 };
1145 };
1146
1147 pwm2 {
1148 pwm2_pin: pwm2-pin {
1149 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1150 };
1151 };
1152
1153 pwm3 {
1154 pwm3_pin: pwm3-pin {
1155 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
1156 };
1157 };
1158
1159 sdio {
1160 sdio_clk: sdio-clk {
1161 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1162 };
1163
1164 sdio_cmd: sdio-cmd {
1165 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1166 };
1167
1168 sdio_pwren: sdio-pwren {
1169 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1170 };
1171
1172 sdio_bus4: sdio-bus4 {
1173 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1174 <1 RK_PA2 2 &pcfg_pull_default>,
1175 <1 RK_PA4 2 &pcfg_pull_default>,
1176 <1 RK_PA5 2 &pcfg_pull_default>;
1177 };
1178 };
1179
1180 sdmmc {
1181 sdmmc_clk: sdmmc-clk {
1182 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1183 };
1184
1185 sdmmc_cmd: sdmmc-cmd {
1186 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1187 };
1188
1189 sdmmc_det: sdmmc-det {
1190 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1191 };
1192
1193 sdmmc_wp: sdmmc-wp {
1194 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1195 };
1196
1197 sdmmc_pwren: sdmmc-pwren {
1198 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1199 };
1200
1201 sdmmc_bus4: sdmmc-bus4 {
1202 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1203 <1 RK_PC3 1 &pcfg_pull_default>,
1204 <1 RK_PC4 1 &pcfg_pull_default>,
1205 <1 RK_PC5 1 &pcfg_pull_default>;
1206 };
1207 };
1208
1209 sfc {
1210 sfc_bus2: sfc-bus2 {
1211 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1212 <1 RK_PD1 3 &pcfg_pull_default>;
1213 };
1214
1215 sfc_bus4: sfc-bus4 {
1216 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>,
1217 <1 RK_PD1 3 &pcfg_pull_default>,
1218 <1 RK_PD2 3 &pcfg_pull_default>,
1219 <1 RK_PD3 3 &pcfg_pull_default>;
1220 };
1221
1222 sfc_clk: sfc-clk {
1223 rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>;
1224 };
1225
1226 sfc_cs0: sfc-cs0 {
1227 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>;
1228 };
1229
1230 sfc_cs1: sfc-cs1 {
1231 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>;
1232 };
1233 };
1234
1235 spdif {
1236 spdif_tx: spdif-tx {
1237 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1238 };
1239 };
1240
1241 spi0 {
1242 spi0_clk: spi0-clk {
1243 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1244 };
1245
1246 spi0_cs0: spi0-cs0 {
1247 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1248 };
1249
1250 spi0_tx: spi0-tx {
1251 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1252 };
1253
1254 spi0_rx: spi0-rx {
1255 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1256 };
1257
1258 spi0_cs1: spi0-cs1 {
1259 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1260 };
1261
1262 spi1_clk: spi1-clk {
1263 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1264 };
1265
1266 spi1_cs0: spi1-cs0 {
1267 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1268 };
1269
1270 spi1_tx: spi1-tx {
1271 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1272 };
1273
1274 spi1_rx: spi1-rx {
1275 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1276 };
1277
1278 spi1_cs1: spi1-cs1 {
1279 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1280 };
1281
1282 spi2_clk: spi2-clk {
1283 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1284 };
1285
1286 spi2_cs0: spi2-cs0 {
1287 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1288 };
1289
1290 spi2_tx: spi2-tx {
1291 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1292 };
1293
1294 spi2_rx: spi2-rx {
1295 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1296 };
1297 };
1298
1299 uart0 {
1300 uart0_xfer: uart0-xfer {
1301 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1302 <2 RK_PD3 2 &pcfg_pull_none>;
1303 };
1304
1305 uart0_cts: uart0-cts {
1306 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1307 };
1308
1309 uart0_rts: uart0-rts {
1310 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1311 };
1312 };
1313
1314 uart1 {
1315 uart1_xfer: uart1-xfer {
1316 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1317 <1 RK_PB2 2 &pcfg_pull_default>;
1318 };
1319
1320 uart1_cts: uart1-cts {
1321 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1322 };
1323
1324 uart1_rts: uart1-rts {
1325 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1326 };
1327 };
1328
1329 uart2 {
1330 uart2_xfer: uart2-xfer {
1331 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1332 <1 RK_PC3 2 &pcfg_pull_none>;
1333 };
1334
1335 uart2_cts: uart2-cts {
1336 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1337 };
1338
1339 uart2_rts: uart2-rts {
1340 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1341 };
1342 };
1343 };
1344 };
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