1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11
12 / {
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 compatible = "rockchip,rk3288";
17
18 interrupt-parent = <&gic>;
19
20 aliases {
21 ethernet0 = &gmac;
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 gpio4 = &gpio4;
27 gpio5 = &gpio5;
28 gpio6 = &gpio6;
29 gpio7 = &gpio7;
30 gpio8 = &gpio8;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 i2c3 = &i2c3;
35 i2c4 = &i2c4;
36 i2c5 = &i2c5;
37 mshc0 = &emmc;
38 mshc1 = &sdmmc;
39 mshc2 = &sdio0;
40 mshc3 = &sdio1;
41 serial0 = &uart0;
42 serial1 = &uart1;
43 serial2 = &uart2;
44 serial3 = &uart3;
45 serial4 = &uart4;
46 spi0 = &spi0;
47 spi1 = &spi1;
48 spi2 = &spi2;
49 };
50
51 arm-pmu {
52 compatible = "arm,cortex-a12-pmu";
53 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
58 };
59
60 cpus {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 enable-method = "rockchip,rk3066-smp";
64 rockchip,pmu = <&pmu>;
65
66 cpu0: cpu@500 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a12";
69 reg = <0x500>;
70 resets = <&cru SRST_CORE0>;
71 operating-points-v2 = <&cpu_opp_table>;
72 #cooling-cells = <2>; /* min followed by max */
73 clock-latency = <40000>;
74 clocks = <&cru ARMCLK>;
75 dynamic-power-coefficient = <370>;
76 };
77 cpu1: cpu@501 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a12";
80 reg = <0x501>;
81 resets = <&cru SRST_CORE1>;
82 operating-points-v2 = <&cpu_opp_table>;
83 #cooling-cells = <2>; /* min followed by max */
84 clock-latency = <40000>;
85 clocks = <&cru ARMCLK>;
86 dynamic-power-coefficient = <370>;
87 };
88 cpu2: cpu@502 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a12";
91 reg = <0x502>;
92 resets = <&cru SRST_CORE2>;
93 operating-points-v2 = <&cpu_opp_table>;
94 #cooling-cells = <2>; /* min followed by max */
95 clock-latency = <40000>;
96 clocks = <&cru ARMCLK>;
97 dynamic-power-coefficient = <370>;
98 };
99 cpu3: cpu@503 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a12";
102 reg = <0x503>;
103 resets = <&cru SRST_CORE3>;
104 operating-points-v2 = <&cpu_opp_table>;
105 #cooling-cells = <2>; /* min followed by max */
106 clock-latency = <40000>;
107 clocks = <&cru ARMCLK>;
108 dynamic-power-coefficient = <370>;
109 };
110 };
111
112 cpu_opp_table: opp-table-0 {
113 compatible = "operating-points-v2";
114 opp-shared;
115
116 opp-126000000 {
117 opp-hz = /bits/ 64 <126000000>;
118 opp-microvolt = <900000>;
119 };
120 opp-216000000 {
121 opp-hz = /bits/ 64 <216000000>;
122 opp-microvolt = <900000>;
123 };
124 opp-312000000 {
125 opp-hz = /bits/ 64 <312000000>;
126 opp-microvolt = <900000>;
127 };
128 opp-408000000 {
129 opp-hz = /bits/ 64 <408000000>;
130 opp-microvolt = <900000>;
131 };
132 opp-600000000 {
133 opp-hz = /bits/ 64 <600000000>;
134 opp-microvolt = <900000>;
135 };
136 opp-696000000 {
137 opp-hz = /bits/ 64 <696000000>;
138 opp-microvolt = <950000>;
139 };
140 opp-816000000 {
141 opp-hz = /bits/ 64 <816000000>;
142 opp-microvolt = <1000000>;
143 };
144 opp-1008000000 {
145 opp-hz = /bits/ 64 <1008000000>;
146 opp-microvolt = <1050000>;
147 };
148 opp-1200000000 {
149 opp-hz = /bits/ 64 <1200000000>;
150 opp-microvolt = <1100000>;
151 };
152 opp-1416000000 {
153 opp-hz = /bits/ 64 <1416000000>;
154 opp-microvolt = <1200000>;
155 };
156 opp-1512000000 {
157 opp-hz = /bits/ 64 <1512000000>;
158 opp-microvolt = <1300000>;
159 };
160 opp-1608000000 {
161 opp-hz = /bits/ 64 <1608000000>;
162 opp-microvolt = <1350000>;
163 };
164 };
165
166 reserved-memory {
167 #address-cells = <2>;
168 #size-cells = <2>;
169 ranges;
170
171 /*
172 * The rk3288 cannot use the memory area above 0xfe000000
173 * for dma operations for some reason. While there is
174 * probably a better solution available somewhere, we
175 * haven't found it yet and while devices with 2GB of ram
176 * are not affected, this issue prevents 4GB from booting.
177 * So to make these devices at least bootable, block
178 * this area for the time being until the real solution
179 * is found.
180 */
181 dma-unusable@fe000000 {
182 reg = <0x0 0xfe000000 0x0 0x1000000>;
183 };
184 };
185
186 xin24m: oscillator {
187 compatible = "fixed-clock";
188 clock-frequency = <24000000>;
189 clock-output-names = "xin24m";
190 #clock-cells = <0>;
191 };
192
193 timer {
194 compatible = "arm,armv7-timer";
195 arm,cpu-registers-not-fw-configured;
196 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
197 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
199 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
200 clock-frequency = <24000000>;
201 arm,no-tick-in-suspend;
202 };
203
204 timer: timer@ff810000 {
205 compatible = "rockchip,rk3288-timer";
206 reg = <0x0 0xff810000 0x0 0x20>;
207 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&cru PCLK_TIMER>, <&xin24m>;
209 clock-names = "pclk", "timer";
210 };
211
212 display-subsystem {
213 compatible = "rockchip,display-subsystem";
214 ports = <&vopl_out>, <&vopb_out>;
215 };
216
217 sdmmc: mmc@ff0c0000 {
218 compatible = "rockchip,rk3288-dw-mshc";
219 max-frequency = <150000000>;
220 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
221 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
222 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
223 fifo-depth = <0x100>;
224 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
225 reg = <0x0 0xff0c0000 0x0 0x4000>;
226 resets = <&cru SRST_MMC0>;
227 reset-names = "reset";
228 status = "disabled";
229 };
230
231 sdio0: mmc@ff0d0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
235 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0x0 0xff0d0000 0x0 0x4000>;
240 resets = <&cru SRST_SDIO0>;
241 reset-names = "reset";
242 status = "disabled";
243 };
244
245 sdio1: mmc@ff0e0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
249 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x0 0xff0e0000 0x0 0x4000>;
254 resets = <&cru SRST_SDIO1>;
255 reset-names = "reset";
256 status = "disabled";
257 };
258
259 emmc: mmc@ff0f0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
263 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x0 0xff0f0000 0x0 0x4000>;
268 resets = <&cru SRST_EMMC>;
269 reset-names = "reset";
270 status = "disabled";
271 };
272
273 saradc: saradc@ff100000 {
274 compatible = "rockchip,saradc";
275 reg = <0x0 0xff100000 0x0 0x100>;
276 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
277 #io-channel-cells = <1>;
278 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
279 clock-names = "saradc", "apb_pclk";
280 resets = <&cru SRST_SARADC>;
281 reset-names = "saradc-apb";
282 status = "disabled";
283 };
284
285 spi0: spi@ff110000 {
286 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
287 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
288 clock-names = "spiclk", "apb_pclk";
289 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
290 dma-names = "tx", "rx";
291 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
294 reg = <0x0 0xff110000 0x0 0x1000>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 spi1: spi@ff120000 {
301 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
302 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
303 clock-names = "spiclk", "apb_pclk";
304 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
305 dma-names = "tx", "rx";
306 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
309 reg = <0x0 0xff120000 0x0 0x1000>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312 status = "disabled";
313 };
314
315 spi2: spi@ff130000 {
316 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
317 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
318 clock-names = "spiclk", "apb_pclk";
319 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
320 dma-names = "tx", "rx";
321 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
324 reg = <0x0 0xff130000 0x0 0x1000>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 status = "disabled";
328 };
329
330 i2c1: i2c@ff140000 {
331 compatible = "rockchip,rk3288-i2c";
332 reg = <0x0 0xff140000 0x0 0x1000>;
333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clock-names = "i2c";
337 clocks = <&cru PCLK_I2C1>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2c1_xfer>;
340 status = "disabled";
341 };
342
343 i2c3: i2c@ff150000 {
344 compatible = "rockchip,rk3288-i2c";
345 reg = <0x0 0xff150000 0x0 0x1000>;
346 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 clock-names = "i2c";
350 clocks = <&cru PCLK_I2C3>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&i2c3_xfer>;
353 status = "disabled";
354 };
355
356 i2c4: i2c@ff160000 {
357 compatible = "rockchip,rk3288-i2c";
358 reg = <0x0 0xff160000 0x0 0x1000>;
359 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
360 #address-cells = <1>;
361 #size-cells = <0>;
362 clock-names = "i2c";
363 clocks = <&cru PCLK_I2C4>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&i2c4_xfer>;
366 status = "disabled";
367 };
368
369 i2c5: i2c@ff170000 {
370 compatible = "rockchip,rk3288-i2c";
371 reg = <0x0 0xff170000 0x0 0x1000>;
372 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
373 #address-cells = <1>;
374 #size-cells = <0>;
375 clock-names = "i2c";
376 clocks = <&cru PCLK_I2C5>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&i2c5_xfer>;
379 status = "disabled";
380 };
381
382 uart0: serial@ff180000 {
383 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
384 reg = <0x0 0xff180000 0x0 0x100>;
385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
386 reg-shift = <2>;
387 reg-io-width = <4>;
388 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clock-names = "baudclk", "apb_pclk";
390 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
391 dma-names = "tx", "rx";
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart0_xfer>;
394 status = "disabled";
395 };
396
397 uart1: serial@ff190000 {
398 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
399 reg = <0x0 0xff190000 0x0 0x100>;
400 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
404 clock-names = "baudclk", "apb_pclk";
405 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
406 dma-names = "tx", "rx";
407 pinctrl-names = "default";
408 pinctrl-0 = <&uart1_xfer>;
409 status = "disabled";
410 };
411
412 uart2: serial@ff690000 {
413 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
414 reg = <0x0 0xff690000 0x0 0x100>;
415 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
416 reg-shift = <2>;
417 reg-io-width = <4>;
418 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
419 clock-names = "baudclk", "apb_pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
422 status = "disabled";
423 };
424
425 uart3: serial@ff1b0000 {
426 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
427 reg = <0x0 0xff1b0000 0x0 0x100>;
428 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
429 reg-shift = <2>;
430 reg-io-width = <4>;
431 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
432 clock-names = "baudclk", "apb_pclk";
433 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
434 dma-names = "tx", "rx";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart3_xfer>;
437 status = "disabled";
438 };
439
440 uart4: serial@ff1c0000 {
441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
442 reg = <0x0 0xff1c0000 0x0 0x100>;
443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
444 reg-shift = <2>;
445 reg-io-width = <4>;
446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
447 clock-names = "baudclk", "apb_pclk";
448 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
449 dma-names = "tx", "rx";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart4_xfer>;
452 status = "disabled";
453 };
454
455 dmac_peri: dma-controller@ff250000 {
456 compatible = "arm,pl330", "arm,primecell";
457 reg = <0x0 0xff250000 0x0 0x4000>;
458 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
460 #dma-cells = <1>;
461 arm,pl330-broken-no-flushp;
462 arm,pl330-periph-burst;
463 clocks = <&cru ACLK_DMAC2>;
464 clock-names = "apb_pclk";
465 };
466
467 thermal-zones {
468 reserve_thermal: reserve-thermal {
469 polling-delay-passive = <1000>; /* milliseconds */
470 polling-delay = <5000>; /* milliseconds */
471
472 thermal-sensors = <&tsadc 0>;
473 };
474
475 cpu_thermal: cpu-thermal {
476 polling-delay-passive = <100>; /* milliseconds */
477 polling-delay = <5000>; /* milliseconds */
478
479 thermal-sensors = <&tsadc 1>;
480
481 trips {
482 cpu_alert0: cpu_alert0 {
483 temperature = <70000>; /* millicelsius */
484 hysteresis = <2000>; /* millicelsius */
485 type = "passive";
486 };
487 cpu_alert1: cpu_alert1 {
488 temperature = <75000>; /* millicelsius */
489 hysteresis = <2000>; /* millicelsius */
490 type = "passive";
491 };
492 cpu_crit: cpu_crit {
493 temperature = <90000>; /* millicelsius */
494 hysteresis = <2000>; /* millicelsius */
495 type = "critical";
496 };
497 };
498
499 cooling-maps {
500 map0 {
501 trip = <&cpu_alert0>;
502 cooling-device =
503 <&cpu0 THERMAL_NO_LIMIT 6>,
504 <&cpu1 THERMAL_NO_LIMIT 6>,
505 <&cpu2 THERMAL_NO_LIMIT 6>,
506 <&cpu3 THERMAL_NO_LIMIT 6>;
507 };
508 map1 {
509 trip = <&cpu_alert1>;
510 cooling-device =
511 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
512 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
513 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
514 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
515 };
516 };
517 };
518
519 gpu_thermal: gpu-thermal {
520 polling-delay-passive = <100>; /* milliseconds */
521 polling-delay = <5000>; /* milliseconds */
522
523 thermal-sensors = <&tsadc 2>;
524
525 trips {
526 gpu_alert0: gpu_alert0 {
527 temperature = <70000>; /* millicelsius */
528 hysteresis = <2000>; /* millicelsius */
529 type = "passive";
530 };
531 gpu_crit: gpu_crit {
532 temperature = <90000>; /* millicelsius */
533 hysteresis = <2000>; /* millicelsius */
534 type = "critical";
535 };
536 };
537
538 cooling-maps {
539 map0 {
540 trip = <&gpu_alert0>;
541 cooling-device =
542 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
543 };
544 };
545 };
546 };
547
548 tsadc: tsadc@ff280000 {
549 compatible = "rockchip,rk3288-tsadc";
550 reg = <0x0 0xff280000 0x0 0x100>;
551 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
553 clock-names = "tsadc", "apb_pclk";
554 resets = <&cru SRST_TSADC>;
555 reset-names = "tsadc-apb";
556 pinctrl-names = "init", "default", "sleep";
557 pinctrl-0 = <&otp_pin>;
558 pinctrl-1 = <&otp_out>;
559 pinctrl-2 = <&otp_pin>;
560 #thermal-sensor-cells = <1>;
561 rockchip,grf = <&grf>;
562 rockchip,hw-tshut-temp = <95000>;
563 status = "disabled";
564 };
565
566 gmac: ethernet@ff290000 {
567 compatible = "rockchip,rk3288-gmac";
568 reg = <0x0 0xff290000 0x0 0x10000>;
569 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
571 interrupt-names = "macirq", "eth_wake_irq";
572 rockchip,grf = <&grf>;
573 clocks = <&cru SCLK_MAC>,
574 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
575 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
576 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
577 clock-names = "stmmaceth",
578 "mac_clk_rx", "mac_clk_tx",
579 "clk_mac_ref", "clk_mac_refout",
580 "aclk_mac", "pclk_mac";
581 resets = <&cru SRST_MAC>;
582 reset-names = "stmmaceth";
583 status = "disabled";
584 };
585
586 usb_host0_ehci: usb@ff500000 {
587 compatible = "generic-ehci";
588 reg = <0x0 0xff500000 0x0 0x100>;
589 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cru HCLK_USBHOST0>;
591 phys = <&usbphy1>;
592 phy-names = "usb";
593 status = "disabled";
594 };
595
596 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
597 usb_host0_ohci: usb@ff520000 {
598 compatible = "generic-ohci";
599 reg = <0x0 0xff520000 0x0 0x100>;
600 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cru HCLK_USBHOST0>;
602 phys = <&usbphy1>;
603 phy-names = "usb";
604 status = "disabled";
605 };
606
607 usb_host1: usb@ff540000 {
608 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
609 "snps,dwc2";
610 reg = <0x0 0xff540000 0x0 0x40000>;
611 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&cru HCLK_USBHOST1>;
613 clock-names = "otg";
614 dr_mode = "host";
615 phys = <&usbphy2>;
616 phy-names = "usb2-phy";
617 snps,reset-phy-on-wake;
618 status = "disabled";
619 };
620
621 usb_otg: usb@ff580000 {
622 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
623 "snps,dwc2";
624 reg = <0x0 0xff580000 0x0 0x40000>;
625 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&cru HCLK_OTG0>;
627 clock-names = "otg";
628 dr_mode = "otg";
629 g-np-tx-fifo-size = <16>;
630 g-rx-fifo-size = <275>;
631 g-tx-fifo-size = <256 128 128 64 64 32>;
632 phys = <&usbphy0>;
633 phy-names = "usb2-phy";
634 status = "disabled";
635 };
636
637 usb_hsic: usb@ff5c0000 {
638 compatible = "generic-ehci";
639 reg = <0x0 0xff5c0000 0x0 0x100>;
640 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru HCLK_HSIC>;
642 status = "disabled";
643 };
644
645 dmac_bus_ns: dma-controller@ff600000 {
646 compatible = "arm,pl330", "arm,primecell";
647 reg = <0x0 0xff600000 0x0 0x4000>;
648 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
650 #dma-cells = <1>;
651 arm,pl330-broken-no-flushp;
652 arm,pl330-periph-burst;
653 clocks = <&cru ACLK_DMAC1>;
654 clock-names = "apb_pclk";
655 status = "disabled";
656 };
657
658 i2c0: i2c@ff650000 {
659 compatible = "rockchip,rk3288-i2c";
660 reg = <0x0 0xff650000 0x0 0x1000>;
661 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
662 #address-cells = <1>;
663 #size-cells = <0>;
664 clock-names = "i2c";
665 clocks = <&cru PCLK_I2C0>;
666 pinctrl-names = "default";
667 pinctrl-0 = <&i2c0_xfer>;
668 status = "disabled";
669 };
670
671 i2c2: i2c@ff660000 {
672 compatible = "rockchip,rk3288-i2c";
673 reg = <0x0 0xff660000 0x0 0x1000>;
674 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
675 #address-cells = <1>;
676 #size-cells = <0>;
677 clock-names = "i2c";
678 clocks = <&cru PCLK_I2C2>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&i2c2_xfer>;
681 status = "disabled";
682 };
683
684 pwm0: pwm@ff680000 {
685 compatible = "rockchip,rk3288-pwm";
686 reg = <0x0 0xff680000 0x0 0x10>;
687 #pwm-cells = <3>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pwm0_pin>;
690 clocks = <&cru PCLK_RKPWM>;
691 status = "disabled";
692 };
693
694 pwm1: pwm@ff680010 {
695 compatible = "rockchip,rk3288-pwm";
696 reg = <0x0 0xff680010 0x0 0x10>;
697 #pwm-cells = <3>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pwm1_pin>;
700 clocks = <&cru PCLK_RKPWM>;
701 status = "disabled";
702 };
703
704 pwm2: pwm@ff680020 {
705 compatible = "rockchip,rk3288-pwm";
706 reg = <0x0 0xff680020 0x0 0x10>;
707 #pwm-cells = <3>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pwm2_pin>;
710 clocks = <&cru PCLK_RKPWM>;
711 status = "disabled";
712 };
713
714 pwm3: pwm@ff680030 {
715 compatible = "rockchip,rk3288-pwm";
716 reg = <0x0 0xff680030 0x0 0x10>;
717 #pwm-cells = <3>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&pwm3_pin>;
720 clocks = <&cru PCLK_RKPWM>;
721 status = "disabled";
722 };
723
724 bus_intmem: sram@ff700000 {
725 compatible = "mmio-sram";
726 reg = <0x0 0xff700000 0x0 0x18000>;
727 #address-cells = <1>;
728 #size-cells = <1>;
729 ranges = <0 0x0 0xff700000 0x18000>;
730 smp-sram@0 {
731 compatible = "rockchip,rk3066-smp-sram";
732 reg = <0x00 0x10>;
733 };
734 };
735
736 pmu_sram: sram@ff720000 {
737 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
738 reg = <0x0 0xff720000 0x0 0x1000>;
739 };
740
741 pmu: power-management@ff730000 {
742 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
743 reg = <0x0 0xff730000 0x0 0x100>;
744
745 power: power-controller {
746 compatible = "rockchip,rk3288-power-controller";
747 #power-domain-cells = <1>;
748 #address-cells = <1>;
749 #size-cells = <0>;
750
751 assigned-clocks = <&cru SCLK_EDP_24M>;
752 assigned-clock-parents = <&xin24m>;
753
754 /*
755 * Note: Although SCLK_* are the working clocks
756 * of device without including on the NOC, needed for
757 * synchronous reset.
758 *
759 * The clocks on the which NOC:
760 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
761 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
762 * ACLK_RGA is on ACLK_RGA_NIU.
763 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
764 *
765 * Which clock are device clocks:
766 * clocks devices
767 * *_IEP IEP:Image Enhancement Processor
768 * *_ISP ISP:Image Signal Processing
769 * *_VIP VIP:Video Input Processor
770 * *_VOP* VOP:Visual Output Processor
771 * *_RGA RGA
772 * *_EDP* EDP
773 * *_LVDS_* LVDS
774 * *_HDMI HDMI
775 * *_MIPI_* MIPI
776 */
777 power-domain@RK3288_PD_VIO {
778 reg = <RK3288_PD_VIO>;
779 clocks = <&cru ACLK_IEP>,
780 <&cru ACLK_ISP>,
781 <&cru ACLK_RGA>,
782 <&cru ACLK_VIP>,
783 <&cru ACLK_VOP0>,
784 <&cru ACLK_VOP1>,
785 <&cru DCLK_VOP0>,
786 <&cru DCLK_VOP1>,
787 <&cru HCLK_IEP>,
788 <&cru HCLK_ISP>,
789 <&cru HCLK_RGA>,
790 <&cru HCLK_VIP>,
791 <&cru HCLK_VOP0>,
792 <&cru HCLK_VOP1>,
793 <&cru PCLK_EDP_CTRL>,
794 <&cru PCLK_HDMI_CTRL>,
795 <&cru PCLK_LVDS_PHY>,
796 <&cru PCLK_MIPI_CSI>,
797 <&cru PCLK_MIPI_DSI0>,
798 <&cru PCLK_MIPI_DSI1>,
799 <&cru SCLK_EDP_24M>,
800 <&cru SCLK_EDP>,
801 <&cru SCLK_ISP_JPE>,
802 <&cru SCLK_ISP>,
803 <&cru SCLK_RGA>;
804 pm_qos = <&qos_vio0_iep>,
805 <&qos_vio1_vop>,
806 <&qos_vio1_isp_w0>,
807 <&qos_vio1_isp_w1>,
808 <&qos_vio0_vop>,
809 <&qos_vio0_vip>,
810 <&qos_vio2_rga_r>,
811 <&qos_vio2_rga_w>,
812 <&qos_vio1_isp_r>;
813 #power-domain-cells = <0>;
814 };
815
816 /*
817 * Note: The following 3 are HEVC(H.265) clocks,
818 * and on the ACLK_HEVC_NIU (NOC).
819 */
820 power-domain@RK3288_PD_HEVC {
821 reg = <RK3288_PD_HEVC>;
822 clocks = <&cru ACLK_HEVC>,
823 <&cru SCLK_HEVC_CABAC>,
824 <&cru SCLK_HEVC_CORE>;
825 pm_qos = <&qos_hevc_r>,
826 <&qos_hevc_w>;
827 #power-domain-cells = <0>;
828 };
829
830 /*
831 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
832 * (video endecoder & decoder) clocks that on the
833 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
834 */
835 power-domain@RK3288_PD_VIDEO {
836 reg = <RK3288_PD_VIDEO>;
837 clocks = <&cru ACLK_VCODEC>,
838 <&cru HCLK_VCODEC>;
839 pm_qos = <&qos_video>;
840 #power-domain-cells = <0>;
841 };
842
843 /*
844 * Note: ACLK_GPU is the GPU clock,
845 * and on the ACLK_GPU_NIU (NOC).
846 */
847 power-domain@RK3288_PD_GPU {
848 reg = <RK3288_PD_GPU>;
849 clocks = <&cru ACLK_GPU>;
850 pm_qos = <&qos_gpu_r>,
851 <&qos_gpu_w>;
852 #power-domain-cells = <0>;
853 };
854 };
855
856 reboot-mode {
857 compatible = "syscon-reboot-mode";
858 offset = <0x94>;
859 mode-normal = <BOOT_NORMAL>;
860 mode-recovery = <BOOT_RECOVERY>;
861 mode-bootloader = <BOOT_FASTBOOT>;
862 mode-loader = <BOOT_BL_DOWNLOAD>;
863 };
864 };
865
866 sgrf: syscon@ff740000 {
867 compatible = "rockchip,rk3288-sgrf", "syscon";
868 reg = <0x0 0xff740000 0x0 0x1000>;
869 };
870
871 cru: clock-controller@ff760000 {
872 compatible = "rockchip,rk3288-cru";
873 reg = <0x0 0xff760000 0x0 0x1000>;
874 clocks = <&xin24m>;
875 clock-names = "xin24m";
876 rockchip,grf = <&grf>;
877 #clock-cells = <1>;
878 #reset-cells = <1>;
879 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
880 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
881 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
882 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
883 <&cru PCLK_PERI>;
884 assigned-clock-rates = <594000000>, <400000000>,
885 <500000000>, <300000000>,
886 <150000000>, <75000000>,
887 <300000000>, <150000000>,
888 <75000000>;
889 };
890
891 grf: syscon@ff770000 {
892 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
893 reg = <0x0 0xff770000 0x0 0x1000>;
894
895 edp_phy: edp-phy {
896 compatible = "rockchip,rk3288-dp-phy";
897 clocks = <&cru SCLK_EDP_24M>;
898 clock-names = "24m";
899 #phy-cells = <0>;
900 status = "disabled";
901 };
902
903 io_domains: io-domains {
904 compatible = "rockchip,rk3288-io-voltage-domain";
905 status = "disabled";
906 };
907
908 usbphy: usbphy {
909 compatible = "rockchip,rk3288-usb-phy";
910 #address-cells = <1>;
911 #size-cells = <0>;
912 status = "disabled";
913
914 usbphy0: usb-phy@320 {
915 #phy-cells = <0>;
916 reg = <0x320>;
917 clocks = <&cru SCLK_OTGPHY0>;
918 clock-names = "phyclk";
919 #clock-cells = <0>;
920 resets = <&cru SRST_USBOTG_PHY>;
921 reset-names = "phy-reset";
922 };
923
924 usbphy1: usb-phy@334 {
925 #phy-cells = <0>;
926 reg = <0x334>;
927 clocks = <&cru SCLK_OTGPHY1>;
928 clock-names = "phyclk";
929 #clock-cells = <0>;
930 resets = <&cru SRST_USBHOST0_PHY>;
931 reset-names = "phy-reset";
932 };
933
934 usbphy2: usb-phy@348 {
935 #phy-cells = <0>;
936 reg = <0x348>;
937 clocks = <&cru SCLK_OTGPHY2>;
938 clock-names = "phyclk";
939 #clock-cells = <0>;
940 resets = <&cru SRST_USBHOST1_PHY>;
941 reset-names = "phy-reset";
942 };
943 };
944 };
945
946 wdt: watchdog@ff800000 {
947 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
948 reg = <0x0 0xff800000 0x0 0x100>;
949 clocks = <&cru PCLK_WDT>;
950 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
951 status = "disabled";
952 };
953
954 spdif: sound@ff8b0000 {
955 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
956 reg = <0x0 0xff8b0000 0x0 0x10000>;
957 #sound-dai-cells = <0>;
958 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
959 clock-names = "mclk", "hclk";
960 dmas = <&dmac_bus_s 3>;
961 dma-names = "tx";
962 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
963 pinctrl-names = "default";
964 pinctrl-0 = <&spdif_tx>;
965 rockchip,grf = <&grf>;
966 status = "disabled";
967 };
968
969 i2s: i2s@ff890000 {
970 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
971 reg = <0x0 0xff890000 0x0 0x10000>;
972 #sound-dai-cells = <0>;
973 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
975 clock-names = "i2s_clk", "i2s_hclk";
976 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
977 dma-names = "tx", "rx";
978 pinctrl-names = "default";
979 pinctrl-0 = <&i2s0_bus>;
980 rockchip,playback-channels = <8>;
981 rockchip,capture-channels = <2>;
982 status = "disabled";
983 };
984
985 crypto: crypto@ff8a0000 {
986 compatible = "rockchip,rk3288-crypto";
987 reg = <0x0 0xff8a0000 0x0 0x4000>;
988 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
990 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
991 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
992 resets = <&cru SRST_CRYPTO>;
993 reset-names = "crypto-rst";
994 };
995
996 iep_mmu: iommu@ff900800 {
997 compatible = "rockchip,iommu";
998 reg = <0x0 0xff900800 0x0 0x40>;
999 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1001 clock-names = "aclk", "iface";
1002 #iommu-cells = <0>;
1003 status = "disabled";
1004 };
1005
1006 isp_mmu: iommu@ff914000 {
1007 compatible = "rockchip,iommu";
1008 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1009 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1011 clock-names = "aclk", "iface";
1012 #iommu-cells = <0>;
1013 rockchip,disable-mmu-reset;
1014 status = "disabled";
1015 };
1016
1017 rga: rga@ff920000 {
1018 compatible = "rockchip,rk3288-rga";
1019 reg = <0x0 0xff920000 0x0 0x180>;
1020 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1022 clock-names = "aclk", "hclk", "sclk";
1023 power-domains = <&power RK3288_PD_VIO>;
1024 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1025 reset-names = "core", "axi", "ahb";
1026 };
1027
1028 vopb: vop@ff930000 {
1029 compatible = "rockchip,rk3288-vop";
1030 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1031 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1034 power-domains = <&power RK3288_PD_VIO>;
1035 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1036 reset-names = "axi", "ahb", "dclk";
1037 iommus = <&vopb_mmu>;
1038 status = "disabled";
1039
1040 vopb_out: port {
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043
1044 vopb_out_hdmi: endpoint@0 {
1045 reg = <0>;
1046 remote-endpoint = <&hdmi_in_vopb>;
1047 };
1048
1049 vopb_out_edp: endpoint@1 {
1050 reg = <1>;
1051 remote-endpoint = <&edp_in_vopb>;
1052 };
1053
1054 vopb_out_mipi: endpoint@2 {
1055 reg = <2>;
1056 remote-endpoint = <&mipi_in_vopb>;
1057 };
1058
1059 vopb_out_lvds: endpoint@3 {
1060 reg = <3>;
1061 remote-endpoint = <&lvds_in_vopb>;
1062 };
1063 };
1064 };
1065
1066 vopb_mmu: iommu@ff930300 {
1067 compatible = "rockchip,iommu";
1068 reg = <0x0 0xff930300 0x0 0x100>;
1069 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1071 clock-names = "aclk", "iface";
1072 power-domains = <&power RK3288_PD_VIO>;
1073 #iommu-cells = <0>;
1074 status = "disabled";
1075 };
1076
1077 vopl: vop@ff940000 {
1078 compatible = "rockchip,rk3288-vop";
1079 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1080 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1082 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1083 power-domains = <&power RK3288_PD_VIO>;
1084 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1085 reset-names = "axi", "ahb", "dclk";
1086 iommus = <&vopl_mmu>;
1087 status = "disabled";
1088
1089 vopl_out: port {
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092
1093 vopl_out_hdmi: endpoint@0 {
1094 reg = <0>;
1095 remote-endpoint = <&hdmi_in_vopl>;
1096 };
1097
1098 vopl_out_edp: endpoint@1 {
1099 reg = <1>;
1100 remote-endpoint = <&edp_in_vopl>;
1101 };
1102
1103 vopl_out_mipi: endpoint@2 {
1104 reg = <2>;
1105 remote-endpoint = <&mipi_in_vopl>;
1106 };
1107
1108 vopl_out_lvds: endpoint@3 {
1109 reg = <3>;
1110 remote-endpoint = <&lvds_in_vopl>;
1111 };
1112 };
1113 };
1114
1115 vopl_mmu: iommu@ff940300 {
1116 compatible = "rockchip,iommu";
1117 reg = <0x0 0xff940300 0x0 0x100>;
1118 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1120 clock-names = "aclk", "iface";
1121 power-domains = <&power RK3288_PD_VIO>;
1122 #iommu-cells = <0>;
1123 status = "disabled";
1124 };
1125
1126 mipi_dsi: dsi@ff960000 {
1127 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1128 reg = <0x0 0xff960000 0x0 0x4000>;
1129 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1131 clock-names = "ref", "pclk";
1132 power-domains = <&power RK3288_PD_VIO>;
1133 rockchip,grf = <&grf>;
1134 status = "disabled";
1135
1136 ports {
1137 #address-cells = <1>;
1138 #size-cells = <0>;
1139
1140 mipi_in: port@0 {
1141 reg = <0>;
1142 #address-cells = <1>;
1143 #size-cells = <0>;
1144
1145 mipi_in_vopb: endpoint@0 {
1146 reg = <0>;
1147 remote-endpoint = <&vopb_out_mipi>;
1148 };
1149
1150 mipi_in_vopl: endpoint@1 {
1151 reg = <1>;
1152 remote-endpoint = <&vopl_out_mipi>;
1153 };
1154 };
1155
1156 mipi_out: port@1 {
1157 reg = <1>;
1158 };
1159 };
1160 };
1161
1162 lvds: lvds@ff96c000 {
1163 compatible = "rockchip,rk3288-lvds";
1164 reg = <0x0 0xff96c000 0x0 0x4000>;
1165 clocks = <&cru PCLK_LVDS_PHY>;
1166 clock-names = "pclk_lvds";
1167 pinctrl-names = "lcdc";
1168 pinctrl-0 = <&lcdc_ctl>;
1169 power-domains = <&power RK3288_PD_VIO>;
1170 rockchip,grf = <&grf>;
1171 status = "disabled";
1172
1173 ports {
1174 #address-cells = <1>;
1175 #size-cells = <0>;
1176
1177 lvds_in: port@0 {
1178 reg = <0>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1181
1182 lvds_in_vopb: endpoint@0 {
1183 reg = <0>;
1184 remote-endpoint = <&vopb_out_lvds>;
1185 };
1186
1187 lvds_in_vopl: endpoint@1 {
1188 reg = <1>;
1189 remote-endpoint = <&vopl_out_lvds>;
1190 };
1191 };
1192
1193 lvds_out: port@1 {
1194 reg = <1>;
1195 };
1196 };
1197 };
1198
1199 edp: dp@ff970000 {
1200 compatible = "rockchip,rk3288-dp";
1201 reg = <0x0 0xff970000 0x0 0x4000>;
1202 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1203 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1204 clock-names = "dp", "pclk";
1205 phys = <&edp_phy>;
1206 phy-names = "dp";
1207 power-domains = <&power RK3288_PD_VIO>;
1208 resets = <&cru SRST_EDP>;
1209 reset-names = "dp";
1210 rockchip,grf = <&grf>;
1211 status = "disabled";
1212
1213 ports {
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1216
1217 edp_in: port@0 {
1218 reg = <0>;
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221
1222 edp_in_vopb: endpoint@0 {
1223 reg = <0>;
1224 remote-endpoint = <&vopb_out_edp>;
1225 };
1226
1227 edp_in_vopl: endpoint@1 {
1228 reg = <1>;
1229 remote-endpoint = <&vopl_out_edp>;
1230 };
1231 };
1232
1233 edp_out: port@1 {
1234 reg = <1>;
1235 };
1236 };
1237 };
1238
1239 hdmi: hdmi@ff980000 {
1240 compatible = "rockchip,rk3288-dw-hdmi";
1241 reg = <0x0 0xff980000 0x0 0x20000>;
1242 reg-io-width = <4>;
1243 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1244 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1245 clock-names = "iahb", "isfr", "cec";
1246 power-domains = <&power RK3288_PD_VIO>;
1247 rockchip,grf = <&grf>;
1248 #sound-dai-cells = <0>;
1249 status = "disabled";
1250
1251 ports {
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254
1255 hdmi_in: port@0 {
1256 reg = <0>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259
1260 hdmi_in_vopb: endpoint@0 {
1261 reg = <0>;
1262 remote-endpoint = <&vopb_out_hdmi>;
1263 };
1264
1265 hdmi_in_vopl: endpoint@1 {
1266 reg = <1>;
1267 remote-endpoint = <&vopl_out_hdmi>;
1268 };
1269 };
1270
1271 hdmi_out: port@1 {
1272 reg = <1>;
1273 };
1274 };
1275 };
1276
1277 vpu: video-codec@ff9a0000 {
1278 compatible = "rockchip,rk3288-vpu";
1279 reg = <0x0 0xff9a0000 0x0 0x800>;
1280 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1282 interrupt-names = "vepu", "vdpu";
1283 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1284 clock-names = "aclk", "hclk";
1285 iommus = <&vpu_mmu>;
1286 power-domains = <&power RK3288_PD_VIDEO>;
1287 };
1288
1289 vpu_mmu: iommu@ff9a0800 {
1290 compatible = "rockchip,iommu";
1291 reg = <0x0 0xff9a0800 0x0 0x100>;
1292 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1294 clock-names = "aclk", "iface";
1295 #iommu-cells = <0>;
1296 power-domains = <&power RK3288_PD_VIDEO>;
1297 };
1298
1299 hevc_mmu: iommu@ff9c0440 {
1300 compatible = "rockchip,iommu";
1301 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1302 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1304 clock-names = "aclk", "iface";
1305 #iommu-cells = <0>;
1306 status = "disabled";
1307 };
1308
1309 gpu: gpu@ffa30000 {
1310 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1311 reg = <0x0 0xffa30000 0x0 0x10000>;
1312 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1313 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1315 interrupt-names = "job", "mmu", "gpu";
1316 clocks = <&cru ACLK_GPU>;
1317 operating-points-v2 = <&gpu_opp_table>;
1318 #cooling-cells = <2>; /* min followed by max */
1319 power-domains = <&power RK3288_PD_GPU>;
1320 status = "disabled";
1321 };
1322
1323 gpu_opp_table: opp-table-1 {
1324 compatible = "operating-points-v2";
1325
1326 opp-100000000 {
1327 opp-hz = /bits/ 64 <100000000>;
1328 opp-microvolt = <950000>;
1329 };
1330 opp-200000000 {
1331 opp-hz = /bits/ 64 <200000000>;
1332 opp-microvolt = <950000>;
1333 };
1334 opp-300000000 {
1335 opp-hz = /bits/ 64 <300000000>;
1336 opp-microvolt = <1000000>;
1337 };
1338 opp-400000000 {
1339 opp-hz = /bits/ 64 <400000000>;
1340 opp-microvolt = <1100000>;
1341 };
1342 opp-600000000 {
1343 opp-hz = /bits/ 64 <600000000>;
1344 opp-microvolt = <1250000>;
1345 };
1346 };
1347
1348 qos_gpu_r: qos@ffaa0000 {
1349 compatible = "rockchip,rk3288-qos", "syscon";
1350 reg = <0x0 0xffaa0000 0x0 0x20>;
1351 };
1352
1353 qos_gpu_w: qos@ffaa0080 {
1354 compatible = "rockchip,rk3288-qos", "syscon";
1355 reg = <0x0 0xffaa0080 0x0 0x20>;
1356 };
1357
1358 qos_vio1_vop: qos@ffad0000 {
1359 compatible = "rockchip,rk3288-qos", "syscon";
1360 reg = <0x0 0xffad0000 0x0 0x20>;
1361 };
1362
1363 qos_vio1_isp_w0: qos@ffad0100 {
1364 compatible = "rockchip,rk3288-qos", "syscon";
1365 reg = <0x0 0xffad0100 0x0 0x20>;
1366 };
1367
1368 qos_vio1_isp_w1: qos@ffad0180 {
1369 compatible = "rockchip,rk3288-qos", "syscon";
1370 reg = <0x0 0xffad0180 0x0 0x20>;
1371 };
1372
1373 qos_vio0_vop: qos@ffad0400 {
1374 compatible = "rockchip,rk3288-qos", "syscon";
1375 reg = <0x0 0xffad0400 0x0 0x20>;
1376 };
1377
1378 qos_vio0_vip: qos@ffad0480 {
1379 compatible = "rockchip,rk3288-qos", "syscon";
1380 reg = <0x0 0xffad0480 0x0 0x20>;
1381 };
1382
1383 qos_vio0_iep: qos@ffad0500 {
1384 compatible = "rockchip,rk3288-qos", "syscon";
1385 reg = <0x0 0xffad0500 0x0 0x20>;
1386 };
1387
1388 qos_vio2_rga_r: qos@ffad0800 {
1389 compatible = "rockchip,rk3288-qos", "syscon";
1390 reg = <0x0 0xffad0800 0x0 0x20>;
1391 };
1392
1393 qos_vio2_rga_w: qos@ffad0880 {
1394 compatible = "rockchip,rk3288-qos", "syscon";
1395 reg = <0x0 0xffad0880 0x0 0x20>;
1396 };
1397
1398 qos_vio1_isp_r: qos@ffad0900 {
1399 compatible = "rockchip,rk3288-qos", "syscon";
1400 reg = <0x0 0xffad0900 0x0 0x20>;
1401 };
1402
1403 qos_video: qos@ffae0000 {
1404 compatible = "rockchip,rk3288-qos", "syscon";
1405 reg = <0x0 0xffae0000 0x0 0x20>;
1406 };
1407
1408 qos_hevc_r: qos@ffaf0000 {
1409 compatible = "rockchip,rk3288-qos", "syscon";
1410 reg = <0x0 0xffaf0000 0x0 0x20>;
1411 };
1412
1413 qos_hevc_w: qos@ffaf0080 {
1414 compatible = "rockchip,rk3288-qos", "syscon";
1415 reg = <0x0 0xffaf0080 0x0 0x20>;
1416 };
1417
1418 dmac_bus_s: dma-controller@ffb20000 {
1419 compatible = "arm,pl330", "arm,primecell";
1420 reg = <0x0 0xffb20000 0x0 0x4000>;
1421 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1423 #dma-cells = <1>;
1424 arm,pl330-broken-no-flushp;
1425 arm,pl330-periph-burst;
1426 clocks = <&cru ACLK_DMAC1>;
1427 clock-names = "apb_pclk";
1428 };
1429
1430 efuse: efuse@ffb40000 {
1431 compatible = "rockchip,rk3288-efuse";
1432 reg = <0x0 0xffb40000 0x0 0x20>;
1433 #address-cells = <1>;
1434 #size-cells = <1>;
1435 clocks = <&cru PCLK_EFUSE256>;
1436 clock-names = "pclk_efuse";
1437
1438 cpu_id: cpu-id@7 {
1439 reg = <0x07 0x10>;
1440 };
1441 cpu_leakage: cpu_leakage@17 {
1442 reg = <0x17 0x1>;
1443 };
1444 };
1445
1446 gic: interrupt-controller@ffc01000 {
1447 compatible = "arm,gic-400";
1448 interrupt-controller;
1449 #interrupt-cells = <3>;
1450 #address-cells = <0>;
1451
1452 reg = <0x0 0xffc01000 0x0 0x1000>,
1453 <0x0 0xffc02000 0x0 0x2000>,
1454 <0x0 0xffc04000 0x0 0x2000>,
1455 <0x0 0xffc06000 0x0 0x2000>;
1456 interrupts = <GIC_PPI 9 0xf04>;
1457 };
1458
1459 pinctrl: pinctrl {
1460 compatible = "rockchip,rk3288-pinctrl";
1461 rockchip,grf = <&grf>;
1462 rockchip,pmu = <&pmu>;
1463 #address-cells = <2>;
1464 #size-cells = <2>;
1465 ranges;
1466
1467 gpio0: gpio@ff750000 {
1468 compatible = "rockchip,gpio-bank";
1469 reg = <0x0 0xff750000 0x0 0x100>;
1470 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1471 clocks = <&cru PCLK_GPIO0>;
1472
1473 gpio-controller;
1474 #gpio-cells = <2>;
1475
1476 interrupt-controller;
1477 #interrupt-cells = <2>;
1478 };
1479
1480 gpio1: gpio@ff780000 {
1481 compatible = "rockchip,gpio-bank";
1482 reg = <0x0 0xff780000 0x0 0x100>;
1483 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&cru PCLK_GPIO1>;
1485
1486 gpio-controller;
1487 #gpio-cells = <2>;
1488
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1491 };
1492
1493 gpio2: gpio@ff790000 {
1494 compatible = "rockchip,gpio-bank";
1495 reg = <0x0 0xff790000 0x0 0x100>;
1496 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&cru PCLK_GPIO2>;
1498
1499 gpio-controller;
1500 #gpio-cells = <2>;
1501
1502 interrupt-controller;
1503 #interrupt-cells = <2>;
1504 };
1505
1506 gpio3: gpio@ff7a0000 {
1507 compatible = "rockchip,gpio-bank";
1508 reg = <0x0 0xff7a0000 0x0 0x100>;
1509 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1510 clocks = <&cru PCLK_GPIO3>;
1511
1512 gpio-controller;
1513 #gpio-cells = <2>;
1514
1515 interrupt-controller;
1516 #interrupt-cells = <2>;
1517 };
1518
1519 gpio4: gpio@ff7b0000 {
1520 compatible = "rockchip,gpio-bank";
1521 reg = <0x0 0xff7b0000 0x0 0x100>;
1522 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&cru PCLK_GPIO4>;
1524
1525 gpio-controller;
1526 #gpio-cells = <2>;
1527
1528 interrupt-controller;
1529 #interrupt-cells = <2>;
1530 };
1531
1532 gpio5: gpio@ff7c0000 {
1533 compatible = "rockchip,gpio-bank";
1534 reg = <0x0 0xff7c0000 0x0 0x100>;
1535 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&cru PCLK_GPIO5>;
1537
1538 gpio-controller;
1539 #gpio-cells = <2>;
1540
1541 interrupt-controller;
1542 #interrupt-cells = <2>;
1543 };
1544
1545 gpio6: gpio@ff7d0000 {
1546 compatible = "rockchip,gpio-bank";
1547 reg = <0x0 0xff7d0000 0x0 0x100>;
1548 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1549 clocks = <&cru PCLK_GPIO6>;
1550
1551 gpio-controller;
1552 #gpio-cells = <2>;
1553
1554 interrupt-controller;
1555 #interrupt-cells = <2>;
1556 };
1557
1558 gpio7: gpio@ff7e0000 {
1559 compatible = "rockchip,gpio-bank";
1560 reg = <0x0 0xff7e0000 0x0 0x100>;
1561 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1562 clocks = <&cru PCLK_GPIO7>;
1563
1564 gpio-controller;
1565 #gpio-cells = <2>;
1566
1567 interrupt-controller;
1568 #interrupt-cells = <2>;
1569 };
1570
1571 gpio8: gpio@ff7f0000 {
1572 compatible = "rockchip,gpio-bank";
1573 reg = <0x0 0xff7f0000 0x0 0x100>;
1574 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1575 clocks = <&cru PCLK_GPIO8>;
1576
1577 gpio-controller;
1578 #gpio-cells = <2>;
1579
1580 interrupt-controller;
1581 #interrupt-cells = <2>;
1582 };
1583
1584 hdmi {
1585 hdmi_cec_c0: hdmi-cec-c0 {
1586 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1587 };
1588
1589 hdmi_cec_c7: hdmi-cec-c7 {
1590 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1591 };
1592
1593 hdmi_ddc: hdmi-ddc {
1594 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1595 <7 RK_PC4 2 &pcfg_pull_none>;
1596 };
1597
1598 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1599 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1600 <7 RK_PC4 2 &pcfg_pull_none>;
1601 };
1602 };
1603
1604 pcfg_output_low: pcfg-output-low {
1605 output-low;
1606 };
1607
1608 pcfg_pull_up: pcfg-pull-up {
1609 bias-pull-up;
1610 };
1611
1612 pcfg_pull_down: pcfg-pull-down {
1613 bias-pull-down;
1614 };
1615
1616 pcfg_pull_none: pcfg-pull-none {
1617 bias-disable;
1618 };
1619
1620 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1621 bias-disable;
1622 drive-strength = <12>;
1623 };
1624
1625 suspend {
1626 global_pwroff: global-pwroff {
1627 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1628 };
1629
1630 ddrio_pwroff: ddrio-pwroff {
1631 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1632 };
1633
1634 ddr0_retention: ddr0-retention {
1635 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1636 };
1637
1638 ddr1_retention: ddr1-retention {
1639 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1640 };
1641 };
1642
1643 edp {
1644 edp_hpd: edp-hpd {
1645 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1646 };
1647 };
1648
1649 i2c0 {
1650 i2c0_xfer: i2c0-xfer {
1651 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1652 <0 RK_PC0 1 &pcfg_pull_none>;
1653 };
1654 };
1655
1656 i2c1 {
1657 i2c1_xfer: i2c1-xfer {
1658 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1659 <8 RK_PA5 1 &pcfg_pull_none>;
1660 };
1661 };
1662
1663 i2c2 {
1664 i2c2_xfer: i2c2-xfer {
1665 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1666 <6 RK_PB2 1 &pcfg_pull_none>;
1667 };
1668 };
1669
1670 i2c3 {
1671 i2c3_xfer: i2c3-xfer {
1672 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1673 <2 RK_PC1 1 &pcfg_pull_none>;
1674 };
1675 };
1676
1677 i2c4 {
1678 i2c4_xfer: i2c4-xfer {
1679 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1680 <7 RK_PC2 1 &pcfg_pull_none>;
1681 };
1682 };
1683
1684 i2c5 {
1685 i2c5_xfer: i2c5-xfer {
1686 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1687 <7 RK_PC4 1 &pcfg_pull_none>;
1688 };
1689 };
1690
1691 i2s0 {
1692 i2s0_bus: i2s0-bus {
1693 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1694 <6 RK_PA1 1 &pcfg_pull_none>,
1695 <6 RK_PA2 1 &pcfg_pull_none>,
1696 <6 RK_PA3 1 &pcfg_pull_none>,
1697 <6 RK_PA4 1 &pcfg_pull_none>,
1698 <6 RK_PB0 1 &pcfg_pull_none>;
1699 };
1700 };
1701
1702 lcdc {
1703 lcdc_ctl: lcdc-ctl {
1704 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1705 <1 RK_PD1 1 &pcfg_pull_none>,
1706 <1 RK_PD2 1 &pcfg_pull_none>,
1707 <1 RK_PD3 1 &pcfg_pull_none>;
1708 };
1709 };
1710
1711 sdmmc {
1712 sdmmc_clk: sdmmc-clk {
1713 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1714 };
1715
1716 sdmmc_cmd: sdmmc-cmd {
1717 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1718 };
1719
1720 sdmmc_cd: sdmmc-cd {
1721 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1722 };
1723
1724 sdmmc_bus1: sdmmc-bus1 {
1725 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1726 };
1727
1728 sdmmc_bus4: sdmmc-bus4 {
1729 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1730 <6 RK_PC1 1 &pcfg_pull_up>,
1731 <6 RK_PC2 1 &pcfg_pull_up>,
1732 <6 RK_PC3 1 &pcfg_pull_up>;
1733 };
1734 };
1735
1736 sdio0 {
1737 sdio0_bus1: sdio0-bus1 {
1738 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1739 };
1740
1741 sdio0_bus4: sdio0-bus4 {
1742 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1743 <4 RK_PC5 1 &pcfg_pull_up>,
1744 <4 RK_PC6 1 &pcfg_pull_up>,
1745 <4 RK_PC7 1 &pcfg_pull_up>;
1746 };
1747
1748 sdio0_cmd: sdio0-cmd {
1749 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1750 };
1751
1752 sdio0_clk: sdio0-clk {
1753 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1754 };
1755
1756 sdio0_cd: sdio0-cd {
1757 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1758 };
1759
1760 sdio0_wp: sdio0-wp {
1761 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1762 };
1763
1764 sdio0_pwr: sdio0-pwr {
1765 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1766 };
1767
1768 sdio0_bkpwr: sdio0-bkpwr {
1769 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1770 };
1771
1772 sdio0_int: sdio0-int {
1773 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1774 };
1775 };
1776
1777 sdio1 {
1778 sdio1_bus1: sdio1-bus1 {
1779 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1780 };
1781
1782 sdio1_bus4: sdio1-bus4 {
1783 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1784 <3 RK_PD1 4 &pcfg_pull_up>,
1785 <3 RK_PD2 4 &pcfg_pull_up>,
1786 <3 RK_PD3 4 &pcfg_pull_up>;
1787 };
1788
1789 sdio1_cd: sdio1-cd {
1790 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1791 };
1792
1793 sdio1_wp: sdio1-wp {
1794 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1795 };
1796
1797 sdio1_bkpwr: sdio1-bkpwr {
1798 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1799 };
1800
1801 sdio1_int: sdio1-int {
1802 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1803 };
1804
1805 sdio1_cmd: sdio1-cmd {
1806 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1807 };
1808
1809 sdio1_clk: sdio1-clk {
1810 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1811 };
1812
1813 sdio1_pwr: sdio1-pwr {
1814 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1815 };
1816 };
1817
1818 emmc {
1819 emmc_clk: emmc-clk {
1820 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1821 };
1822
1823 emmc_cmd: emmc-cmd {
1824 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1825 };
1826
1827 emmc_pwr: emmc-pwr {
1828 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1829 };
1830
1831 emmc_bus1: emmc-bus1 {
1832 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1833 };
1834
1835 emmc_bus4: emmc-bus4 {
1836 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1837 <3 RK_PA1 2 &pcfg_pull_up>,
1838 <3 RK_PA2 2 &pcfg_pull_up>,
1839 <3 RK_PA3 2 &pcfg_pull_up>;
1840 };
1841
1842 emmc_bus8: emmc-bus8 {
1843 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1844 <3 RK_PA1 2 &pcfg_pull_up>,
1845 <3 RK_PA2 2 &pcfg_pull_up>,
1846 <3 RK_PA3 2 &pcfg_pull_up>,
1847 <3 RK_PA4 2 &pcfg_pull_up>,
1848 <3 RK_PA5 2 &pcfg_pull_up>,
1849 <3 RK_PA6 2 &pcfg_pull_up>,
1850 <3 RK_PA7 2 &pcfg_pull_up>;
1851 };
1852 };
1853
1854 spi0 {
1855 spi0_clk: spi0-clk {
1856 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1857 };
1858 spi0_cs0: spi0-cs0 {
1859 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1860 };
1861 spi0_tx: spi0-tx {
1862 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1863 };
1864 spi0_rx: spi0-rx {
1865 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1866 };
1867 spi0_cs1: spi0-cs1 {
1868 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1869 };
1870 };
1871 spi1 {
1872 spi1_clk: spi1-clk {
1873 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1874 };
1875 spi1_cs0: spi1-cs0 {
1876 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1877 };
1878 spi1_rx: spi1-rx {
1879 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1880 };
1881 spi1_tx: spi1-tx {
1882 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1883 };
1884 };
1885
1886 spi2 {
1887 spi2_cs1: spi2-cs1 {
1888 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1889 };
1890 spi2_clk: spi2-clk {
1891 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1892 };
1893 spi2_cs0: spi2-cs0 {
1894 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1895 };
1896 spi2_rx: spi2-rx {
1897 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1898 };
1899 spi2_tx: spi2-tx {
1900 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1901 };
1902 };
1903
1904 uart0 {
1905 uart0_xfer: uart0-xfer {
1906 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1907 <4 RK_PC1 1 &pcfg_pull_none>;
1908 };
1909
1910 uart0_cts: uart0-cts {
1911 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1912 };
1913
1914 uart0_rts: uart0-rts {
1915 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1916 };
1917 };
1918
1919 uart1 {
1920 uart1_xfer: uart1-xfer {
1921 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1922 <5 RK_PB1 1 &pcfg_pull_none>;
1923 };
1924
1925 uart1_cts: uart1-cts {
1926 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1927 };
1928
1929 uart1_rts: uart1-rts {
1930 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1931 };
1932 };
1933
1934 uart2 {
1935 uart2_xfer: uart2-xfer {
1936 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1937 <7 RK_PC7 1 &pcfg_pull_none>;
1938 };
1939 /* no rts / cts for uart2 */
1940 };
1941
1942 uart3 {
1943 uart3_xfer: uart3-xfer {
1944 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1945 <7 RK_PB0 1 &pcfg_pull_none>;
1946 };
1947
1948 uart3_cts: uart3-cts {
1949 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1950 };
1951
1952 uart3_rts: uart3-rts {
1953 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1954 };
1955 };
1956
1957 uart4 {
1958 uart4_xfer: uart4-xfer {
1959 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1960 <5 RK_PB6 3 &pcfg_pull_none>;
1961 };
1962
1963 uart4_cts: uart4-cts {
1964 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1965 };
1966
1967 uart4_rts: uart4-rts {
1968 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1969 };
1970 };
1971
1972 tsadc {
1973 otp_pin: otp-pin {
1974 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1975 };
1976
1977 otp_out: otp-out {
1978 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1979 };
1980 };
1981
1982 pwm0 {
1983 pwm0_pin: pwm0-pin {
1984 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1985 };
1986 };
1987
1988 pwm1 {
1989 pwm1_pin: pwm1-pin {
1990 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1991 };
1992 };
1993
1994 pwm2 {
1995 pwm2_pin: pwm2-pin {
1996 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1997 };
1998 };
1999
2000 pwm3 {
2001 pwm3_pin: pwm3-pin {
2002 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
2003 };
2004 };
2005
2006 gmac {
2007 rgmii_pins: rgmii-pins {
2008 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
2009 <3 RK_PD7 3 &pcfg_pull_none>,
2010 <3 RK_PD2 3 &pcfg_pull_none>,
2011 <3 RK_PD3 3 &pcfg_pull_none>,
2012 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
2013 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
2014 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
2015 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
2016 <4 RK_PA0 3 &pcfg_pull_none>,
2017 <4 RK_PA5 3 &pcfg_pull_none>,
2018 <4 RK_PA6 3 &pcfg_pull_none>,
2019 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
2020 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
2021 <4 RK_PA1 3 &pcfg_pull_none>,
2022 <4 RK_PA3 3 &pcfg_pull_none>;
2023 };
2024
2025 rmii_pins: rmii-pins {
2026 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
2027 <3 RK_PD7 3 &pcfg_pull_none>,
2028 <3 RK_PD4 3 &pcfg_pull_none>,
2029 <3 RK_PD5 3 &pcfg_pull_none>,
2030 <4 RK_PA0 3 &pcfg_pull_none>,
2031 <4 RK_PA5 3 &pcfg_pull_none>,
2032 <4 RK_PA4 3 &pcfg_pull_none>,
2033 <4 RK_PA1 3 &pcfg_pull_none>,
2034 <4 RK_PA2 3 &pcfg_pull_none>,
2035 <4 RK_PA3 3 &pcfg_pull_none>;
2036 };
2037 };
2038
2039 spdif {
2040 spdif_tx: spdif-tx {
2041 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2042 };
2043 };
2044 };
2045 };
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