1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <arm64/rockchip/rockchip-pinconf.dtsi>
8
9 /*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13 &pinctrl {
14 clk_out_ethernet {
15 /omit-if-no-ref/
16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17 rockchip,pins =
18 /* clk_out_ethernet_m1 */
19 <2 RK_PC5 2 &pcfg_pull_none>;
20 };
21 };
22 emmc {
23 /omit-if-no-ref/
24 emmc_rstnout: emmc-rstnout {
25 rockchip,pins =
26 /* emmc_rstn */
27 <1 RK_PA3 2 &pcfg_pull_none>;
28 };
29 /omit-if-no-ref/
30 emmc_bus8: emmc-bus8 {
31 rockchip,pins =
32 /* emmc_d0 */
33 <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
34 /* emmc_d1 */
35 <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
36 /* emmc_d2 */
37 <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
38 /* emmc_d3 */
39 <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
40 /* emmc_d4 */
41 <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
42 /* emmc_d5 */
43 <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
44 /* emmc_d6 */
45 <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
46 /* emmc_d7 */
47 <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
48 };
49 /omit-if-no-ref/
50 emmc_clk: emmc-clk {
51 rockchip,pins =
52 /* emmc_clko */
53 <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
54 };
55 /omit-if-no-ref/
56 emmc_cmd: emmc-cmd {
57 rockchip,pins =
58 /* emmc_cmd */
59 <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
60 };
61 };
62 fspi {
63 /omit-if-no-ref/
64 fspi_pins: fspi-pins {
65 rockchip,pins =
66 /* fspi_clk */
67 <1 RK_PA3 3 &pcfg_pull_down>,
68 /* fspi_cs0n */
69 <0 RK_PD4 3 &pcfg_pull_up>,
70 /* fspi_d0 */
71 <1 RK_PA0 3 &pcfg_pull_up>,
72 /* fspi_d1 */
73 <1 RK_PA1 3 &pcfg_pull_up>,
74 /* fspi_d2 */
75 <0 RK_PD6 3 &pcfg_pull_up>,
76 /* fspi_d3 */
77 <1 RK_PA2 3 &pcfg_pull_up>;
78 };
79 };
80 i2c0 {
81 /omit-if-no-ref/
82 i2c0_xfer: i2c0-xfer {
83 rockchip,pins =
84 /* i2c0_scl */
85 <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
86 /* i2c0_sda */
87 <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
88 };
89 };
90 i2c2 {
91 /omit-if-no-ref/
92 i2c2_xfer: i2c2-xfer {
93 rockchip,pins =
94 /* i2c2_scl */
95 <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
96 /* i2c2_sda */
97 <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
98 };
99 };
100 i2c3 {
101 /omit-if-no-ref/
102 i2c3m0_xfer: i2c3m0-xfer {
103 rockchip,pins =
104 /* i2c3_scl_m0 */
105 <3 RK_PA4 5 &pcfg_pull_none>,
106 /* i2c3_sda_m0 */
107 <3 RK_PA5 5 &pcfg_pull_none>;
108 };
109 /omit-if-no-ref/
110 i2c3m1_xfer: i2c3m1-xfer {
111 rockchip,pins =
112 /* i2c3_scl_m1 */
113 <2 RK_PD4 7 &pcfg_pull_none>,
114 /* i2c3_sda_m1 */
115 <2 RK_PD5 7 &pcfg_pull_none>;
116 };
117 /omit-if-no-ref/
118 i2c3m2_xfer: i2c3m2-xfer {
119 rockchip,pins =
120 /* i2c3_scl_m2 */
121 <1 RK_PD6 3 &pcfg_pull_none>,
122 /* i2c3_sda_m2 */
123 <1 RK_PD7 3 &pcfg_pull_none>;
124 };
125 };
126 i2s0 {
127 i2s0m0_lrck_tx: i2s0m0-lrck-tx {
128 rockchip,pins =
129 /* i2s0_lrck_tx_m0 */
130 <3 RK_PD3 1 &pcfg_pull_none>;
131 };
132 i2s0m0_lrck_rx: i2s0m0-lrck-rx {
133 rockchip,pins =
134 /* i2s0_lrck_rx_m0 */
135 <3 RK_PD4 1 &pcfg_pull_none>;
136 };
137 i2s0m0_mclk: i2s0m0-mclk {
138 rockchip,pins =
139 /* i2s0_mclk_m0 */
140 <3 RK_PD2 1 &pcfg_pull_none>;
141 };
142 i2s0m0_sclk_rx: i2s0m0-sclk-rx {
143 rockchip,pins =
144 /* i2s0_sclk_rx_m0 */
145 <3 RK_PD1 1 &pcfg_pull_none>;
146 };
147 i2s0m0_sclk_tx: i2s0m0-sclk-tx {
148 rockchip,pins =
149 /* i2s0_sclk_tx_m0 */
150 <3 RK_PD0 1 &pcfg_pull_none>;
151 };
152 i2s0m0_sdi0: i2s0m0-sdi0 {
153 rockchip,pins =
154 /* i2s0_sdi0_m0 */
155 <3 RK_PD6 1 &pcfg_pull_none>;
156 };
157 i2s0m0_sdo0: i2s0m0-sdo0 {
158 rockchip,pins =
159 /* i2s0_sdo0_m0 */
160 <3 RK_PD5 1 &pcfg_pull_none>;
161 };
162 i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
163 rockchip,pins =
164 /* i2s0_sdo1_sdi3_m0 */
165 <3 RK_PD7 1 &pcfg_pull_none>;
166 };
167 i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
168 rockchip,pins =
169 /* i2s0_sdo2_sdi2_m0 */
170 <4 RK_PA0 1 &pcfg_pull_none>;
171 };
172 i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
173 rockchip,pins =
174 /* i2s0_sdo3_sdi1_m0 */
175 <4 RK_PA1 1 &pcfg_pull_none>;
176 };
177 i2s0m1_lrck_tx: i2s0m1-lrck-tx {
178 rockchip,pins =
179 /* i2s0_lrck_tx_m1 */
180 <3 RK_PA5 3 &pcfg_pull_none>;
181 };
182 i2s0m1_lrck_rx: i2s0m1-lrck-rx {
183 rockchip,pins =
184 /* i2s0_lrck_rx_m1 */
185 <3 RK_PB2 3 &pcfg_pull_none>;
186 };
187 i2s0m1_mclk: i2s0m1-mclk {
188 rockchip,pins =
189 /* i2s0_mclk_m1 */
190 <3 RK_PB0 3 &pcfg_pull_none>;
191 };
192 i2s0m1_sclk_rx: i2s0m1-sclk-rx {
193 rockchip,pins =
194 /* i2s0_sclk_rx_m1 */
195 <3 RK_PB1 3 &pcfg_pull_none>;
196 };
197 i2s0m1_sclk_tx: i2s0m1-sclk-tx {
198 rockchip,pins =
199 /* i2s0_sclk_tx_m1 */
200 <3 RK_PA4 3 &pcfg_pull_none>;
201 };
202 i2s0m1_sdi0: i2s0m1-sdi0 {
203 rockchip,pins =
204 /* i2s0_sdi0_m1 */
205 <3 RK_PA7 3 &pcfg_pull_none>;
206 };
207 i2s0m1_sdo0: i2s0m1-sdo0 {
208 rockchip,pins =
209 /* i2s0_sdo0_m1 */
210 <3 RK_PA6 3 &pcfg_pull_none>;
211 };
212 i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
213 rockchip,pins =
214 /* i2s0_sdo1_sdi3_m1 */
215 <3 RK_PB3 3 &pcfg_pull_none>;
216 };
217 i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
218 rockchip,pins =
219 /* i2s0_sdo2_sdi2_m1 */
220 <3 RK_PB4 3 &pcfg_pull_none>;
221 };
222 i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
223 rockchip,pins =
224 /* i2s0_sdo3_sdi1_m1 */
225 <3 RK_PB5 3 &pcfg_pull_none>;
226 };
227 };
228 pwm0 {
229 /omit-if-no-ref/
230 pwm0m0_pins: pwm0m0-pins {
231 rockchip,pins =
232 /* pwm0_pin_m0 */
233 <0 RK_PB6 3 &pcfg_pull_none>;
234 };
235 /omit-if-no-ref/
236 pwm0m1_pins: pwm0m1-pins {
237 rockchip,pins =
238 /* pwm0_pin_m1 */
239 <2 RK_PB3 5 &pcfg_pull_none>;
240 };
241 };
242 pwm1 {
243 /omit-if-no-ref/
244 pwm1m0_pins: pwm1m0-pins {
245 rockchip,pins =
246 /* pwm1_pin_m0 */
247 <0 RK_PB7 3 &pcfg_pull_none>;
248 };
249 };
250 pwm2 {
251 /omit-if-no-ref/
252 pwm2m0_pins: pwm2m0-pins {
253 rockchip,pins =
254 /* pwm2_pin_m0 */
255 <0 RK_PC0 3 &pcfg_pull_none>;
256 };
257 /omit-if-no-ref/
258 pwm2m1_pins: pwm2m1-pins {
259 rockchip,pins =
260 /* pwm2_pin_m1 */
261 <2 RK_PB1 5 &pcfg_pull_none>;
262 };
263 };
264 pwm3 {
265 /omit-if-no-ref/
266 pwm3m0_pins: pwm3m0-pins {
267 rockchip,pins =
268 /* pwm3_pin_m0 */
269 <0 RK_PC1 3 &pcfg_pull_none>;
270 };
271 };
272 pwm4 {
273 /omit-if-no-ref/
274 pwm4m0_pins: pwm4m0-pins {
275 rockchip,pins =
276 /* pwm4_pin_m0 */
277 <0 RK_PC2 3 &pcfg_pull_none>;
278 };
279 };
280 pwm5 {
281 /omit-if-no-ref/
282 pwm5m0_pins: pwm5m0-pins {
283 rockchip,pins =
284 /* pwm5_pin_m0 */
285 <0 RK_PC3 3 &pcfg_pull_none>;
286 };
287 };
288 pwm6 {
289 /omit-if-no-ref/
290 pwm6m0_pins: pwm6m0-pins {
291 rockchip,pins =
292 /* pwm6_pin_m0 */
293 <0 RK_PB2 3 &pcfg_pull_none>;
294 };
295 /omit-if-no-ref/
296 pwm6m1_pins: pwm6m1-pins {
297 rockchip,pins =
298 /* pwm6_pin_m1 */
299 <2 RK_PD4 5 &pcfg_pull_none>;
300 };
301 };
302 pwm7 {
303 /omit-if-no-ref/
304 pwm7m0_pins: pwm7m0-pins {
305 rockchip,pins =
306 /* pwm7_pin_m0 */
307 <0 RK_PB1 3 &pcfg_pull_none>;
308 };
309 /omit-if-no-ref/
310 pwm7m1_pins: pwm7m1-pins {
311 rockchip,pins =
312 /* pwm7_pin_m1 */
313 <3 RK_PA0 5 &pcfg_pull_none>;
314 };
315 };
316 pwm8 {
317 /omit-if-no-ref/
318 pwm8m0_pins: pwm8m0-pins {
319 rockchip,pins =
320 /* pwm8_pin_m0 */
321 <3 RK_PA4 6 &pcfg_pull_none>;
322 };
323 /omit-if-no-ref/
324 pwm8m1_pins: pwm8m1-pins {
325 rockchip,pins =
326 /* pwm8_pin_m1 */
327 <2 RK_PD7 5 &pcfg_pull_none>;
328 };
329 };
330 pwm9 {
331 /omit-if-no-ref/
332 pwm9m0_pins: pwm9m0-pins {
333 rockchip,pins =
334 /* pwm9_pin_m0 */
335 <3 RK_PA5 6 &pcfg_pull_none>;
336 };
337 /omit-if-no-ref/
338 pwm9m1_pins: pwm9m1-pins {
339 rockchip,pins =
340 /* pwm9_pin_m1 */
341 <2 RK_PD6 5 &pcfg_pull_none>;
342 };
343 };
344 pwm10 {
345 /omit-if-no-ref/
346 pwm10m0_pins: pwm10m0-pins {
347 rockchip,pins =
348 /* pwm10_pin_m0 */
349 <3 RK_PA6 6 &pcfg_pull_none>;
350 };
351 /omit-if-no-ref/
352 pwm10m1_pins: pwm10m1-pins {
353 rockchip,pins =
354 /* pwm10_pin_m1 */
355 <2 RK_PD5 5 &pcfg_pull_none>;
356 };
357 };
358 pwm11 {
359 /omit-if-no-ref/
360 pwm11m0_pins: pwm11m0-pins {
361 rockchip,pins =
362 /* pwm11_pin_m0 */
363 <3 RK_PA7 6 &pcfg_pull_none>;
364 };
365 /omit-if-no-ref/
366 pwm11m1_pins: pwm11m1-pins {
367 rockchip,pins =
368 /* pwm11_pin_m1 */
369 <3 RK_PA1 5 &pcfg_pull_none>;
370 };
371 };
372 rgmii {
373 /omit-if-no-ref/
374 rgmiim1_miim: rgmiim1-miim {
375 rockchip,pins =
376 /* rgmii_mdc_m1 */
377 <2 RK_PC2 2 &pcfg_pull_none>,
378 /* rgmii_mdio_m1 */
379 <2 RK_PC1 2 &pcfg_pull_none>;
380 };
381 /omit-if-no-ref/
382 rgmiim1_rxer: rgmiim1-rxer {
383 rockchip,pins =
384 /* rgmii_rxer_m1 */
385 <2 RK_PC0 2 &pcfg_pull_none>;
386 };
387 /omit-if-no-ref/
388 rgmiim1_bus2: rgmiim1-bus2 {
389 rockchip,pins =
390 /* rgmii_rxd0_m1 */
391 <2 RK_PB5 2 &pcfg_pull_none>,
392 /* rgmii_rxd1_m1 */
393 <2 RK_PB6 2 &pcfg_pull_none>,
394 /* rgmii_rxdv_m1 */
395 <2 RK_PB4 2 &pcfg_pull_none>,
396 /* rgmii_txd0_m1 */
397 <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
398 /* rgmii_txd1_m1 */
399 <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
400 /* rgmii_txen_m1 */
401 <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
402 };
403 /omit-if-no-ref/
404 rgmiim1_bus4: rgmiim1-bus4 {
405 rockchip,pins =
406 /* rgmii_rxclk_m1 */
407 <2 RK_PD3 2 &pcfg_pull_none>,
408 /* rgmii_rxd2_m1 */
409 <2 RK_PC7 2 &pcfg_pull_none>,
410 /* rgmii_rxd3_m1 */
411 <2 RK_PD0 2 &pcfg_pull_none>,
412 /* rgmii_txclk_m1 */
413 <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
414 /* rgmii_txd2_m1 */
415 <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
416 /* rgmii_txd3_m1 */
417 <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
418 };
419 /omit-if-no-ref/
420 rgmiim1_mclkinout: rgmiim1-mclkinout {
421 rockchip,pins =
422 /* rgmii_clk_m1 */
423 <2 RK_PB7 2 &pcfg_pull_none>;
424 };
425 };
426 sdmmc0 {
427 /omit-if-no-ref/
428 sdmmc0_bus4: sdmmc0-bus4 {
429 rockchip,pins =
430 /* sdmmc0_d0 */
431 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
432 /* sdmmc0_d1 */
433 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
434 /* sdmmc0_d2 */
435 <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
436 /* sdmmc0_d3 */
437 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
438 };
439 /omit-if-no-ref/
440 sdmmc0_clk: sdmmc0-clk {
441 rockchip,pins =
442 /* sdmmc0_clk */
443 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
444 };
445 /omit-if-no-ref/
446 sdmmc0_cmd: sdmmc0-cmd {
447 rockchip,pins =
448 /* sdmmc0_cmd */
449 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
450 };
451 /omit-if-no-ref/
452 sdmmc0_det: sdmmc0-det {
453 rockchip,pins =
454 <0 RK_PA3 1 &pcfg_pull_none>;
455 };
456 /omit-if-no-ref/
457 sdmmc0_pwr: sdmmc0-pwr {
458 rockchip,pins =
459 <0 RK_PC0 1 &pcfg_pull_none>;
460 };
461 };
462 sdmmc1 {
463 /omit-if-no-ref/
464 sdmmc1_bus4: sdmmc1-bus4 {
465 rockchip,pins =
466 /* sdmmc1_d0 */
467 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
468 /* sdmmc1_d1 */
469 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
470 /* sdmmc1_d2 */
471 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
472 /* sdmmc1_d3 */
473 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
474 };
475 /omit-if-no-ref/
476 sdmmc1_clk: sdmmc1-clk {
477 rockchip,pins =
478 /* sdmmc1_clk */
479 <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
480 };
481 /omit-if-no-ref/
482 sdmmc1_cmd: sdmmc1-cmd {
483 rockchip,pins =
484 /* sdmmc1_cmd */
485 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
486 };
487 /omit-if-no-ref/
488 sdmmc1_det: sdmmc1-det {
489 rockchip,pins =
490 <1 RK_PD0 2 &pcfg_pull_none>;
491 };
492 /omit-if-no-ref/
493 sdmmc1_pwr: sdmmc1-pwr {
494 rockchip,pins =
495 <1 RK_PD1 2 &pcfg_pull_none>;
496 };
497 };
498 uart0 {
499 /omit-if-no-ref/
500 uart0_xfer: uart0-xfer {
501 rockchip,pins =
502 /* uart0_rx */
503 <1 RK_PC2 1 &pcfg_pull_up>,
504 /* uart0_tx */
505 <1 RK_PC3 1 &pcfg_pull_up>;
506 };
507 /omit-if-no-ref/
508 uart0_ctsn: uart0-ctsn {
509 rockchip,pins =
510 <1 RK_PC1 1 &pcfg_pull_none>;
511 };
512 /omit-if-no-ref/
513 uart0_rtsn: uart0-rtsn {
514 rockchip,pins =
515 <1 RK_PC0 1 &pcfg_pull_none>;
516 };
517 /omit-if-no-ref/
518 uart0_rtsn_gpio: uart0-rts-pin {
519 rockchip,pins =
520 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
521 };
522 };
523 uart1 {
524 /omit-if-no-ref/
525 uart1m0_xfer: uart1m0-xfer {
526 rockchip,pins =
527 /* uart1_rx_m0 */
528 <0 RK_PB7 2 &pcfg_pull_up>,
529 /* uart1_tx_m0 */
530 <0 RK_PB6 2 &pcfg_pull_up>;
531 };
532 };
533 uart2 {
534 /omit-if-no-ref/
535 uart2m1_xfer: uart2m1-xfer {
536 rockchip,pins =
537 /* uart2_rx_m1 */
538 <3 RK_PA3 1 &pcfg_pull_up>,
539 /* uart2_tx_m1 */
540 <3 RK_PA2 1 &pcfg_pull_up>;
541 };
542 };
543 uart3 {
544 /omit-if-no-ref/
545 uart3m0_xfer: uart3m0-xfer {
546 rockchip,pins =
547 /* uart3_rx_m0 */
548 <3 RK_PC7 4 &pcfg_pull_up>,
549 /* uart3_tx_m0 */
550 <3 RK_PC6 4 &pcfg_pull_up>;
551 };
552 /omit-if-no-ref/
553 uart3m2_xfer: uart3m2-xfer {
554 rockchip,pins =
555 /* uart3_rx_m2 */
556 <3 RK_PA1 4 &pcfg_pull_up>,
557 /* uart3_tx_m2 */
558 <3 RK_PA0 4 &pcfg_pull_up>;
559 };
560 };
561 uart4 {
562 /omit-if-no-ref/
563 uart4m0_xfer: uart4m0-xfer {
564 rockchip,pins =
565 /* uart4_rx_m0 */
566 <3 RK_PA5 4 &pcfg_pull_up>,
567 /* uart4_tx_m0 */
568 <3 RK_PA4 4 &pcfg_pull_up>;
569 };
570 /omit-if-no-ref/
571 uart4m2_xfer: uart4m2-xfer {
572 rockchip,pins =
573 /* uart4_rx_m2 */
574 <1 RK_PD4 3 &pcfg_pull_up>,
575 /* uart4_tx_m2 */
576 <1 RK_PD5 3 &pcfg_pull_up>;
577 };
578 };
579 uart5 {
580 /omit-if-no-ref/
581 uart5m0_xfer: uart5m0-xfer {
582 rockchip,pins =
583 /* uart5_rx_m0 */
584 <3 RK_PA7 4 &pcfg_pull_up>,
585 /* uart5_tx_m0 */
586 <3 RK_PA6 4 &pcfg_pull_up>;
587 };
588 /omit-if-no-ref/
589 uart5m2_xfer: uart5m2-xfer {
590 rockchip,pins =
591 /* uart5_rx_m2 */
592 <2 RK_PA1 3 &pcfg_pull_up>,
593 /* uart5_tx_m2 */
594 <2 RK_PA0 3 &pcfg_pull_up>;
595 };
596 };
597 };
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