1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 compatible = "rockchip,rv1126";
19
20 interrupt-parent = <&gic>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c2 = &i2c2;
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 serial3 = &uart3;
29 serial4 = &uart4;
30 serial5 = &uart5;
31 };
32
33 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 cpu0: cpu@f00 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0xf00>;
41 enable-method = "psci";
42 clocks = <&cru ARMCLK>;
43 };
44
45 cpu1: cpu@f01 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <0xf01>;
49 enable-method = "psci";
50 clocks = <&cru ARMCLK>;
51 };
52
53 cpu2: cpu@f02 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0xf02>;
57 enable-method = "psci";
58 clocks = <&cru ARMCLK>;
59 };
60
61 cpu3: cpu@f03 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a7";
64 reg = <0xf03>;
65 enable-method = "psci";
66 clocks = <&cru ARMCLK>;
67 };
68 };
69
70 arm-pmu {
71 compatible = "arm,cortex-a7-pmu";
72 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
76 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
77 };
78
79 psci {
80 compatible = "arm,psci-1.0";
81 method = "smc";
82 };
83
84 timer {
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
90 clock-frequency = <24000000>;
91 };
92
93 display_subsystem {
94 compatible = "rockchip,display-subsystem";
95 ports = <&vop_out>;
96 };
97
98 xin24m: oscillator {
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 clock-output-names = "xin24m";
102 #clock-cells = <0>;
103 };
104
105 grf: syscon@fe000000 {
106 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
107 reg = <0xfe000000 0x20000>;
108 };
109
110 pmugrf: syscon@fe020000 {
111 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
112 reg = <0xfe020000 0x1000>;
113
114 pmu_io_domains: io-domains {
115 compatible = "rockchip,rv1126-pmu-io-voltage-domain";
116 status = "disabled";
117 };
118 };
119
120 qos_emmc: qos@fe860000 {
121 compatible = "rockchip,rv1126-qos", "syscon";
122 reg = <0xfe860000 0x20>;
123 };
124
125 qos_nandc: qos@fe860080 {
126 compatible = "rockchip,rv1126-qos", "syscon";
127 reg = <0xfe860080 0x20>;
128 };
129
130 qos_sfc: qos@fe860200 {
131 compatible = "rockchip,rv1126-qos", "syscon";
132 reg = <0xfe860200 0x20>;
133 };
134
135 qos_sdio: qos@fe86c000 {
136 compatible = "rockchip,rv1126-qos", "syscon";
137 reg = <0xfe86c000 0x20>;
138 };
139
140 qos_iep: qos@fe8a0000 {
141 compatible = "rockchip,rv1126-qos", "syscon";
142 reg = <0xfe8a0000 0x20>;
143 };
144
145 qos_rga_rd: qos@fe8a0080 {
146 compatible = "rockchip,rv1126-qos", "syscon";
147 reg = <0xfe8a0080 0x20>;
148 };
149
150 qos_rga_wr: qos@fe8a0100 {
151 compatible = "rockchip,rv1126-qos", "syscon";
152 reg = <0xfe8a0100 0x20>;
153 };
154
155 qos_vop: qos@fe8a0180 {
156 compatible = "rockchip,rv1126-qos", "syscon";
157 reg = <0xfe8a0180 0x20>;
158 };
159
160 gic: interrupt-controller@feff0000 {
161 compatible = "arm,gic-400";
162 interrupt-controller;
163 #interrupt-cells = <3>;
164 #address-cells = <0>;
165
166 reg = <0xfeff1000 0x1000>,
167 <0xfeff2000 0x2000>,
168 <0xfeff4000 0x2000>,
169 <0xfeff6000 0x2000>;
170 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
171 };
172
173 pmu: power-management@ff3e0000 {
174 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
175 reg = <0xff3e0000 0x1000>;
176
177 power: power-controller {
178 compatible = "rockchip,rv1126-power-controller";
179 #power-domain-cells = <1>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182
183 power-domain@RV1126_PD_NVM {
184 reg = <RV1126_PD_NVM>;
185 clocks = <&cru HCLK_EMMC>,
186 <&cru CLK_EMMC>,
187 <&cru HCLK_NANDC>,
188 <&cru CLK_NANDC>,
189 <&cru HCLK_SFC>,
190 <&cru HCLK_SFCXIP>,
191 <&cru SCLK_SFC>;
192 pm_qos = <&qos_emmc>,
193 <&qos_nandc>,
194 <&qos_sfc>;
195 #power-domain-cells = <0>;
196 };
197
198 power-domain@RV1126_PD_SDIO {
199 reg = <RV1126_PD_SDIO>;
200 clocks = <&cru HCLK_SDIO>,
201 <&cru CLK_SDIO>;
202 pm_qos = <&qos_sdio>;
203 #power-domain-cells = <0>;
204 };
205
206 power-domain@RV1126_PD_VO {
207 reg = <RV1126_PD_VO>;
208 clocks = <&cru ACLK_RGA>,
209 <&cru HCLK_RGA>,
210 <&cru CLK_RGA_CORE>,
211 <&cru ACLK_VOP>,
212 <&cru HCLK_VOP>,
213 <&cru DCLK_VOP>,
214 <&cru PCLK_DSIHOST>,
215 <&cru ACLK_IEP>,
216 <&cru HCLK_IEP>,
217 <&cru CLK_IEP_CORE>;
218 pm_qos = <&qos_rga_rd>,
219 <&qos_rga_wr>,
220 <&qos_vop>,
221 <&qos_iep>;
222 #power-domain-cells = <0>;
223 };
224 };
225 };
226
227 i2c0: i2c@ff3f0000 {
228 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
229 reg = <0xff3f0000 0x1000>;
230 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
231 rockchip,grf = <&pmugrf>;
232 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
233 clock-names = "i2c", "pclk";
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c0_xfer>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 i2c2: i2c@ff400000 {
242 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
243 reg = <0xff400000 0x1000>;
244 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
245 rockchip,grf = <&pmugrf>;
246 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
247 clock-names = "i2c", "pclk";
248 pinctrl-names = "default";
249 pinctrl-0 = <&i2c2_xfer>;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 status = "disabled";
253 };
254
255 uart1: serial@ff410000 {
256 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
257 reg = <0xff410000 0x100>;
258 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
259 clock-frequency = <24000000>;
260 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
261 clock-names = "baudclk", "apb_pclk";
262 dmas = <&dmac 7>, <&dmac 6>;
263 dma-names = "tx", "rx";
264 pinctrl-names = "default";
265 pinctrl-0 = <&uart1m0_xfer>;
266 reg-shift = <2>;
267 reg-io-width = <4>;
268 status = "disabled";
269 };
270
271 pwm2: pwm@ff430020 {
272 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
273 reg = <0xff430020 0x10>;
274 clock-names = "pwm", "pclk";
275 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pwm2m0_pins>;
278 #pwm-cells = <3>;
279 status = "disabled";
280 };
281
282 pmucru: clock-controller@ff480000 {
283 compatible = "rockchip,rv1126-pmucru";
284 reg = <0xff480000 0x1000>;
285 rockchip,grf = <&grf>;
286 #clock-cells = <1>;
287 #reset-cells = <1>;
288 };
289
290 cru: clock-controller@ff490000 {
291 compatible = "rockchip,rv1126-cru";
292 reg = <0xff490000 0x1000>;
293 clocks = <&xin24m>;
294 clock-names = "xin24m";
295 rockchip,grf = <&grf>;
296 #clock-cells = <1>;
297 #reset-cells = <1>;
298 };
299
300 dmac: dma-controller@ff4e0000 {
301 compatible = "arm,pl330", "arm,primecell";
302 reg = <0xff4e0000 0x4000>;
303 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
305 #dma-cells = <1>;
306 arm,pl330-periph-burst;
307 clocks = <&cru ACLK_DMAC>;
308 clock-names = "apb_pclk";
309 };
310
311 pwm11: pwm@ff550030 {
312 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
313 reg = <0xff550030 0x10>;
314 clock-names = "pwm", "pclk";
315 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
316 pinctrl-0 = <&pwm11m0_pins>;
317 pinctrl-names = "default";
318 #pwm-cells = <3>;
319 status = "disabled";
320 };
321
322 uart0: serial@ff560000 {
323 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
324 reg = <0xff560000 0x100>;
325 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
326 clock-frequency = <24000000>;
327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
328 clock-names = "baudclk", "apb_pclk";
329 dmas = <&dmac 5>, <&dmac 4>;
330 dma-names = "tx", "rx";
331 pinctrl-names = "default";
332 pinctrl-0 = <&uart0_xfer>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 status = "disabled";
336 };
337
338 uart2: serial@ff570000 {
339 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
340 reg = <0xff570000 0x100>;
341 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
342 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
344 clock-names = "baudclk", "apb_pclk";
345 dmas = <&dmac 9>, <&dmac 8>;
346 dma-names = "tx", "rx";
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart2m1_xfer>;
349 reg-shift = <2>;
350 reg-io-width = <4>;
351 status = "disabled";
352 };
353
354 uart3: serial@ff580000 {
355 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
356 reg = <0xff580000 0x100>;
357 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
358 clock-frequency = <24000000>;
359 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
360 clock-names = "baudclk", "apb_pclk";
361 dmas = <&dmac 11>, <&dmac 10>;
362 dma-names = "tx", "rx";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart3m0_xfer>;
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 status = "disabled";
368 };
369
370 uart4: serial@ff590000 {
371 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
372 reg = <0xff590000 0x100>;
373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
374 clock-frequency = <24000000>;
375 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
376 clock-names = "baudclk", "apb_pclk";
377 dmas = <&dmac 13>, <&dmac 12>;
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&uart4m0_xfer>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 status = "disabled";
384 };
385
386 uart5: serial@ff5a0000 {
387 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
388 reg = <0xff5a0000 0x100>;
389 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
390 clock-frequency = <24000000>;
391 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
392 clock-names = "baudclk", "apb_pclk";
393 dmas = <&dmac 15>, <&dmac 14>;
394 dma-names = "tx", "rx";
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart5m0_xfer>;
397 reg-shift = <2>;
398 reg-io-width = <4>;
399 status = "disabled";
400 };
401
402 saradc: adc@ff5e0000 {
403 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
404 reg = <0xff5e0000 0x100>;
405 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
406 #io-channel-cells = <1>;
407 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
408 clock-names = "saradc", "apb_pclk";
409 resets = <&cru SRST_SARADC_P>;
410 reset-names = "saradc-apb";
411 status = "disabled";
412 };
413
414 timer0: timer@ff660000 {
415 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
416 reg = <0xff660000 0x20>;
417 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
419 clock-names = "pclk", "timer";
420 };
421
422 vop: vop@ffb00000 {
423 compatible = "rockchip,rv1126-vop";
424 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
425 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
426 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
427 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
428 reset-names = "axi", "ahb", "dclk";
429 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
430 iommus = <&vop_mmu>;
431 power-domains = <&power RV1126_PD_VO>;
432 status = "disabled";
433
434 vop_out: port {
435 #address-cells = <1>;
436 #size-cells = <0>;
437
438 vop_out_rgb: endpoint@0 {
439 reg = <0>;
440 };
441
442 vop_out_dsi: endpoint@1 {
443 reg = <1>;
444 };
445 };
446 };
447
448 vop_mmu: iommu@ffb00f00 {
449 compatible = "rockchip,iommu";
450 reg = <0xffb00f00 0x100>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 clock-names = "aclk", "iface";
453 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
454 #iommu-cells = <0>;
455 power-domains = <&power RV1126_PD_VO>;
456 status = "disabled";
457 };
458
459 gmac: ethernet@ffc40000 {
460 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
461 reg = <0xffc40000 0x4000>;
462 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
464 interrupt-names = "macirq", "eth_wake_irq";
465 rockchip,grf = <&grf>;
466 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
467 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
468 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
469 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
470 clock-names = "stmmaceth", "mac_clk_rx",
471 "mac_clk_tx", "clk_mac_ref",
472 "aclk_mac", "pclk_mac",
473 "clk_mac_speed", "ptp_ref";
474 resets = <&cru SRST_GMAC_A>;
475 reset-names = "stmmaceth";
476
477 snps,mixed-burst;
478 snps,tso;
479
480 snps,axi-config = <&stmmac_axi_setup>;
481 snps,mtl-rx-config = <&mtl_rx_setup>;
482 snps,mtl-tx-config = <&mtl_tx_setup>;
483 status = "disabled";
484
485 mdio: mdio {
486 compatible = "snps,dwmac-mdio";
487 #address-cells = <0x1>;
488 #size-cells = <0x0>;
489 };
490
491 stmmac_axi_setup: stmmac-axi-config {
492 snps,wr_osr_lmt = <4>;
493 snps,rd_osr_lmt = <8>;
494 snps,blen = <0 0 0 0 16 8 4>;
495 };
496
497 mtl_rx_setup: rx-queues-config {
498 snps,rx-queues-to-use = <1>;
499 queue0 {};
500 };
501
502 mtl_tx_setup: tx-queues-config {
503 snps,tx-queues-to-use = <1>;
504 queue0 {};
505 };
506 };
507
508 emmc: mmc@ffc50000 {
509 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
510 reg = <0xffc50000 0x4000>;
511 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
513 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
514 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
515 fifo-depth = <0x100>;
516 max-frequency = <200000000>;
517 power-domains = <&power RV1126_PD_NVM>;
518 status = "disabled";
519 };
520
521 sdmmc: mmc@ffc60000 {
522 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
523 reg = <0xffc60000 0x4000>;
524 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
526 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
527 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
528 fifo-depth = <0x100>;
529 max-frequency = <200000000>;
530 status = "disabled";
531 };
532
533 sdio: mmc@ffc70000 {
534 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
535 reg = <0xffc70000 0x4000>;
536 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
538 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
539 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
540 fifo-depth = <0x100>;
541 max-frequency = <200000000>;
542 power-domains = <&power RV1126_PD_SDIO>;
543 status = "disabled";
544 };
545
546 sfc: spi@ffc90000 {
547 compatible = "rockchip,sfc";
548 reg = <0xffc90000 0x4000>;
549 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
550 assigned-clocks = <&cru SCLK_SFC>;
551 assigned-clock-rates = <80000000>;
552 clock-names = "clk_sfc", "hclk_sfc";
553 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
554 power-domains = <&power RV1126_PD_NVM>;
555 status = "disabled";
556 };
557
558 pinctrl: pinctrl {
559 compatible = "rockchip,rv1126-pinctrl";
560 rockchip,grf = <&grf>;
561 rockchip,pmu = <&pmugrf>;
562 #address-cells = <1>;
563 #size-cells = <1>;
564 ranges;
565
566 gpio0: gpio@ff460000 {
567 compatible = "rockchip,gpio-bank";
568 reg = <0xff460000 0x100>;
569 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
571 gpio-controller;
572 #gpio-cells = <2>;
573 interrupt-controller;
574 #interrupt-cells = <2>;
575 };
576
577 gpio1: gpio@ff620000 {
578 compatible = "rockchip,gpio-bank";
579 reg = <0xff620000 0x100>;
580 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 };
587
588 gpio2: gpio@ff630000 {
589 compatible = "rockchip,gpio-bank";
590 reg = <0xff630000 0x100>;
591 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
597 };
598
599 gpio3: gpio@ff640000 {
600 compatible = "rockchip,gpio-bank";
601 reg = <0xff640000 0x100>;
602 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
604 gpio-controller;
605 #gpio-cells = <2>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
608 };
609
610 gpio4: gpio@ff650000 {
611 compatible = "rockchip,gpio-bank";
612 reg = <0xff650000 0x100>;
613 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
615 gpio-controller;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 };
620 };
621 };
622
623 #include "rv1126-pinctrl.dtsi"
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