1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
4 *
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Device tree source file for Samsung's ARTIK5 evaluation board
9 * which is based on Samsung Exynos3250 SoC.
10 */
11
12 /dts-v1/;
13 #include "exynos3250-artik5.dtsi"
14
15 / {
16 model = "Samsung ARTIK5 evaluation board";
17 compatible = "samsung,artik5-eval", "samsung,artik5",
18 "samsung,exynos3250", "samsung,exynos3";
19
20 aliases {
21 mmc0 = &mshc_2;
22 };
23 };
24
25 &mshc_2 {
26 cap-sd-highspeed;
27 disable-wp;
28 vqmmc-supply = <&ldo3_reg>;
29 card-detect-delay = <200>;
30 clock-frequency = <100000000>;
31 max-frequency = <100000000>;
32 samsung,dw-mshc-ciu-div = <1>;
33 samsung,dw-mshc-sdr-timing = <0 1>;
34 samsung,dw-mshc-ddr-timing = <1 2>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
37 bus-width = <4>;
38 status = "okay";
39 };
40
41 &serial_2 {
42 status = "okay";
43 };
44
45 &spi_0 {
46 status = "okay";
47 cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>;
48
49 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
50 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
51 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
52 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
53 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
54 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
55
56 ethernet@0 {
57 compatible = "asix,ax88796c";
58 reg = <0x0>;
59 local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */
60 interrupt-parent = <&gpx2>;
61 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
62 spi-max-frequency = <40000000>;
63 reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
64
65 controller-data {
66 samsung,spi-feedback-delay = <2>;
67 };
68 };
69 };
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