1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org
9 *
10 * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
11 * based board files can include this file and provide values for board specific
12 * bindings.
13 *
14 * Note: This file does not include device nodes for all the controllers in
15 * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
16 * nodes can be added to this file.
17 */
18
19 #include "exynos4.dtsi"
20 #include "exynos4-cpu-thermal.dtsi"
21
22 / {
23 compatible = "samsung,exynos4210", "samsung,exynos4";
24
25 aliases {
26 pinctrl0 = &pinctrl_0;
27 pinctrl1 = &pinctrl_1;
28 pinctrl2 = &pinctrl_2;
29 };
30
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
33 clocks = <&clock CLK_DIV_ACP>;
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
36 status = "disabled";
37
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
41
42 opp-134000000 {
43 opp-hz = /bits/ 64 <134000000>;
44 };
45 opp-160000000 {
46 opp-hz = /bits/ 64 <160000000>;
47 };
48 opp-200000000 {
49 opp-hz = /bits/ 64 <200000000>;
50 };
51 };
52 };
53
54 bus_display: bus-display {
55 compatible = "samsung,exynos-bus";
56 clocks = <&clock CLK_ACLK160>;
57 clock-names = "bus";
58 operating-points-v2 = <&bus_display_opp_table>;
59 status = "disabled";
60
61 bus_display_opp_table: opp-table {
62 compatible = "operating-points-v2";
63 opp-shared;
64
65 opp-100000000 {
66 opp-hz = /bits/ 64 <100000000>;
67 };
68 opp-134000000 {
69 opp-hz = /bits/ 64 <134000000>;
70 };
71 opp-160000000 {
72 opp-hz = /bits/ 64 <160000000>;
73 };
74 };
75 };
76
77 bus_dmc: bus-dmc {
78 compatible = "samsung,exynos-bus";
79 clocks = <&clock CLK_DIV_DMC>;
80 clock-names = "bus";
81 operating-points-v2 = <&bus_dmc_opp_table>;
82 status = "disabled";
83
84 bus_dmc_opp_table: opp-table {
85 compatible = "operating-points-v2";
86 opp-shared;
87
88 opp-134000000 {
89 opp-hz = /bits/ 64 <134000000>;
90 opp-microvolt = <1025000>;
91 };
92 opp-267000000 {
93 opp-hz = /bits/ 64 <267000000>;
94 opp-microvolt = <1050000>;
95 };
96 opp-400000000 {
97 opp-hz = /bits/ 64 <400000000>;
98 opp-microvolt = <1150000>;
99 opp-suspend;
100 };
101 };
102 };
103
104 bus_fsys: bus-fsys {
105 compatible = "samsung,exynos-bus";
106 clocks = <&clock CLK_ACLK133>;
107 clock-names = "bus";
108 operating-points-v2 = <&bus_fsys_opp_table>;
109 status = "disabled";
110
111 bus_fsys_opp_table: opp-table {
112 compatible = "operating-points-v2";
113 opp-shared;
114
115 opp-10000000 {
116 opp-hz = /bits/ 64 <10000000>;
117 };
118 opp-134000000 {
119 opp-hz = /bits/ 64 <134000000>;
120 };
121 };
122 };
123
124 bus_lcd0: bus-lcd0 {
125 compatible = "samsung,exynos-bus";
126 clocks = <&clock CLK_ACLK200>;
127 clock-names = "bus";
128 operating-points-v2 = <&bus_leftbus_opp_table>;
129 status = "disabled";
130 };
131
132 bus_leftbus: bus-leftbus {
133 compatible = "samsung,exynos-bus";
134 clocks = <&clock CLK_DIV_GDL>;
135 clock-names = "bus";
136 operating-points-v2 = <&bus_leftbus_opp_table>;
137 status = "disabled";
138 };
139
140 bus_mfc: bus-mfc {
141 compatible = "samsung,exynos-bus";
142 clocks = <&clock CLK_SCLK_MFC>;
143 clock-names = "bus";
144 operating-points-v2 = <&bus_leftbus_opp_table>;
145 status = "disabled";
146 };
147
148 bus_peri: bus-peri {
149 compatible = "samsung,exynos-bus";
150 clocks = <&clock CLK_ACLK100>;
151 clock-names = "bus";
152 operating-points-v2 = <&bus_peri_opp_table>;
153 status = "disabled";
154
155 bus_peri_opp_table: opp-table {
156 compatible = "operating-points-v2";
157 opp-shared;
158
159 opp-5000000 {
160 opp-hz = /bits/ 64 <5000000>;
161 };
162 opp-100000000 {
163 opp-hz = /bits/ 64 <100000000>;
164 };
165 };
166 };
167
168 bus_rightbus: bus-rightbus {
169 compatible = "samsung,exynos-bus";
170 clocks = <&clock CLK_DIV_GDR>;
171 clock-names = "bus";
172 operating-points-v2 = <&bus_leftbus_opp_table>;
173 status = "disabled";
174 };
175
176 cpus {
177 #address-cells = <1>;
178 #size-cells = <0>;
179
180 cpu-map {
181 cluster0 {
182 core0 {
183 cpu = <&cpu0>;
184 };
185 core1 {
186 cpu = <&cpu1>;
187 };
188 };
189 };
190
191 cpu0: cpu@900 {
192 device_type = "cpu";
193 compatible = "arm,cortex-a9";
194 reg = <0x900>;
195 clocks = <&clock CLK_ARM_CLK>;
196 clock-names = "cpu";
197 clock-latency = <160000>;
198
199 operating-points = <
200 1200000 1250000
201 1000000 1150000
202 800000 1075000
203 500000 975000
204 400000 975000
205 200000 950000
206 >;
207 #cooling-cells = <2>; /* min followed by max */
208 };
209
210 cpu1: cpu@901 {
211 device_type = "cpu";
212 compatible = "arm,cortex-a9";
213 reg = <0x901>;
214 clocks = <&clock CLK_ARM_CLK>;
215 clock-names = "cpu";
216 clock-latency = <160000>;
217
218 operating-points = <
219 1200000 1250000
220 1000000 1150000
221 800000 1075000
222 500000 975000
223 400000 975000
224 200000 950000
225 >;
226 #cooling-cells = <2>; /* min followed by max */
227 };
228 };
229
230 bus_leftbus_opp_table: opp-table-0 {
231 compatible = "operating-points-v2";
232 opp-shared;
233
234 opp-100000000 {
235 opp-hz = /bits/ 64 <100000000>;
236 };
237 opp-160000000 {
238 opp-hz = /bits/ 64 <160000000>;
239 };
240 opp-200000000 {
241 opp-hz = /bits/ 64 <200000000>;
242 opp-suspend;
243 };
244 };
245
246 soc: soc {
247 sysram: sram@2020000 {
248 compatible = "mmio-sram";
249 reg = <0x02020000 0x20000>;
250 #address-cells = <1>;
251 #size-cells = <1>;
252 ranges = <0 0x02020000 0x20000>;
253
254 smp-sram@0 {
255 compatible = "samsung,exynos4210-sysram";
256 reg = <0x0 0x1000>;
257 };
258
259 smp-sram@1f000 {
260 compatible = "samsung,exynos4210-sysram-ns";
261 reg = <0x1f000 0x1000>;
262 };
263 };
264
265 pd_lcd1: power-domain@10023ca0 {
266 compatible = "samsung,exynos4210-pd";
267 reg = <0x10023ca0 0x20>;
268 #power-domain-cells = <0>;
269 label = "LCD1";
270 };
271
272 l2c: cache-controller@10502000 {
273 compatible = "arm,pl310-cache";
274 reg = <0x10502000 0x1000>;
275 cache-unified;
276 cache-level = <2>;
277 prefetch-data = <1>;
278 prefetch-instr = <1>;
279 arm,tag-latency = <2 2 1>;
280 arm,data-latency = <2 2 1>;
281 };
282
283 mct: timer@10050000 {
284 compatible = "samsung,exynos4210-mct";
285 reg = <0x10050000 0x800>;
286 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
287 clock-names = "fin_pll", "mct";
288 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
289 <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
290 <&combiner 12 6>,
291 <&combiner 12 7>,
292 <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
293 <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
294 };
295
296 watchdog: watchdog@10060000 {
297 compatible = "samsung,s3c6410-wdt";
298 reg = <0x10060000 0x100>;
299 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clock CLK_WDT>;
301 clock-names = "watchdog";
302 };
303
304 clock: clock-controller@10030000 {
305 compatible = "samsung,exynos4210-clock";
306 reg = <0x10030000 0x20000>;
307 #clock-cells = <1>;
308 };
309
310 pinctrl_0: pinctrl@11400000 {
311 compatible = "samsung,exynos4210-pinctrl";
312 reg = <0x11400000 0x1000>;
313 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
314 };
315
316 pinctrl_1: pinctrl@11000000 {
317 compatible = "samsung,exynos4210-pinctrl";
318 reg = <0x11000000 0x1000>;
319 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
320
321 wakup_eint: wakeup-interrupt-controller {
322 compatible = "samsung,exynos4210-wakeup-eint";
323 interrupt-parent = <&gic>;
324 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
325 };
326 };
327
328 pinctrl_2: pinctrl@3860000 {
329 compatible = "samsung,exynos4210-pinctrl";
330 reg = <0x03860000 0x1000>;
331 };
332
333 g2d: g2d@12800000 {
334 compatible = "samsung,s5pv210-g2d";
335 reg = <0x12800000 0x1000>;
336 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
338 clock-names = "sclk_fimg2d", "fimg2d";
339 power-domains = <&pd_lcd0>;
340 iommus = <&sysmmu_g2d>;
341 };
342
343 ppmu_acp: ppmu@10ae0000 {
344 compatible = "samsung,exynos-ppmu";
345 reg = <0x10ae0000 0x2000>;
346 status = "disabled";
347 };
348
349 ppmu_lcd1: ppmu@12240000 {
350 compatible = "samsung,exynos-ppmu";
351 reg = <0x12240000 0x2000>;
352 clocks = <&clock CLK_PPMULCD1>;
353 clock-names = "ppmu";
354 status = "disabled";
355 };
356
357 sysmmu_g2d: sysmmu@12a20000 {
358 compatible = "samsung,exynos-sysmmu";
359 reg = <0x12a20000 0x1000>;
360 interrupt-parent = <&combiner>;
361 interrupts = <4 7>;
362 clock-names = "sysmmu", "master";
363 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
364 power-domains = <&pd_lcd0>;
365 #iommu-cells = <0>;
366 };
367
368 sysmmu_fimd1: sysmmu@12220000 {
369 compatible = "samsung,exynos-sysmmu";
370 interrupt-parent = <&combiner>;
371 reg = <0x12220000 0x1000>;
372 interrupts = <5 3>;
373 clock-names = "sysmmu", "master";
374 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
375 power-domains = <&pd_lcd1>;
376 #iommu-cells = <0>;
377 };
378 };
379 };
380
381 &cpu_alert0 {
382 temperature = <85000>; /* millicelsius */
383 };
384
385 &cpu_alert1 {
386 temperature = <100000>; /* millicelsius */
387 };
388
389 &cpu_alert2 {
390 temperature = <110000>; /* millicelsius */
391 };
392
393 &cpu_thermal {
394 /*
395 * Exynos 4210 supports thermal interrupts, but only for the rising
396 * threshold. This means that polling is not needed for preventing
397 * overheating, but only for decreasing cooling when possible. Hence we
398 * poll with a high delay. Ideally, we would disable polling for the
399 * first trip point, but this isn't really possible without outrageous
400 * hacks.
401 */
402 polling-delay-passive = <5000>;
403 polling-delay = <5000>;
404 };
405
406 &gic {
407 cpu-offset = <0x8000>;
408 };
409
410 &camera {
411 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
412 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
413 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
414 };
415
416 &combiner {
417 samsung,combiner-nr = <16>;
418 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
434 };
435
436 &fimc_0 {
437 samsung,pix-limits = <4224 8192 1920 4224>;
438 samsung,mainscaler-ext;
439 samsung,cam-if;
440 };
441
442 &fimc_1 {
443 samsung,pix-limits = <4224 8192 1920 4224>;
444 samsung,mainscaler-ext;
445 samsung,cam-if;
446 };
447
448 &fimc_2 {
449 samsung,pix-limits = <4224 8192 1920 4224>;
450 samsung,mainscaler-ext;
451 samsung,lcd-wb;
452 };
453
454 &fimc_3 {
455 samsung,pix-limits = <1920 8192 1366 1920>;
456 samsung,rotators = <0>;
457 samsung,mainscaler-ext;
458 samsung,lcd-wb;
459 };
460
461 &gpu {
462 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-names = "gp",
473 "gpmmu",
474 "pp0",
475 "ppmmu0",
476 "pp1",
477 "ppmmu1",
478 "pp2",
479 "ppmmu2",
480 "pp3",
481 "ppmmu3";
482 operating-points-v2 = <&gpu_opp_table>;
483
484 gpu_opp_table: opp-table {
485 compatible = "operating-points-v2";
486
487 opp-160000000 {
488 opp-hz = /bits/ 64 <160000000>;
489 opp-microvolt = <950000>;
490 };
491 opp-267000000 {
492 opp-hz = /bits/ 64 <267000000>;
493 opp-microvolt = <1050000>;
494 };
495 };
496 };
497
498 &mdma1 {
499 power-domains = <&pd_lcd0>;
500 };
501
502 &mixer {
503 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
504 "sclk_mixer";
505 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
506 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
507 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
508 };
509
510 &pmu {
511 interrupts = <2 2>, <3 2>;
512 interrupt-affinity = <&cpu0>, <&cpu1>;
513 status = "okay";
514 };
515
516 &pmu_system_controller {
517 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
518 "clkout4", "clkout8", "clkout9";
519 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
520 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
521 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
522 #clock-cells = <1>;
523 };
524
525 &rotator {
526 power-domains = <&pd_lcd0>;
527 };
528
529 &sysmmu_rotator {
530 power-domains = <&pd_lcd0>;
531 };
532
533 &tmu {
534 compatible = "samsung,exynos4210-tmu";
535 clocks = <&clock CLK_TMU_APBIF>;
536 clock-names = "tmu_apbif";
537 };
538
539 #include "exynos4210-pinctrl.dtsi"
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