1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos4x12 SoC series device nodes are listed in this file.
9 * Particular SoCs from Exynos4x12 series can include this file and provide
10 * values for SoCs specific bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4x12 SoCs. As device tree coverage for Exynos4x12 increases, additional
14 * nodes can be added to this file.
15 */
16
17 #include "exynos4.dtsi"
18
19 #include "exynos4-cpu-thermal.dtsi"
20
21 / {
22 aliases {
23 pinctrl0 = &pinctrl_0;
24 pinctrl1 = &pinctrl_1;
25 pinctrl2 = &pinctrl_2;
26 pinctrl3 = &pinctrl_3;
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
29 };
30
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
33 clocks = <&clock CLK_DIV_ACP>;
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
36 status = "disabled";
37
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
40
41 opp-100000000 {
42 opp-hz = /bits/ 64 <100000000>;
43 };
44 opp-134000000 {
45 opp-hz = /bits/ 64 <134000000>;
46 };
47 opp-160000000 {
48 opp-hz = /bits/ 64 <160000000>;
49 };
50 opp-267000000 {
51 opp-hz = /bits/ 64 <267000000>;
52 };
53 };
54 };
55
56 bus_c2c: bus-c2c {
57 compatible = "samsung,exynos-bus";
58 clocks = <&clock CLK_DIV_C2C>;
59 clock-names = "bus";
60 operating-points-v2 = <&bus_dmc_opp_table>;
61 status = "disabled";
62 };
63
64 bus_dmc: bus-dmc {
65 compatible = "samsung,exynos-bus";
66 clocks = <&clock CLK_DIV_DMC>;
67 clock-names = "bus";
68 operating-points-v2 = <&bus_dmc_opp_table>;
69 samsung,data-clock-ratio = <4>;
70 #interconnect-cells = <0>;
71 status = "disabled";
72 };
73
74 bus_display: bus-display {
75 compatible = "samsung,exynos-bus";
76 clocks = <&clock CLK_ACLK160>;
77 clock-names = "bus";
78 operating-points-v2 = <&bus_display_opp_table>;
79 interconnects = <&bus_leftbus &bus_dmc>;
80 #interconnect-cells = <0>;
81 status = "disabled";
82
83 bus_display_opp_table: opp-table {
84 compatible = "operating-points-v2";
85
86 opp-160000000 {
87 opp-hz = /bits/ 64 <160000000>;
88 };
89 opp-200000000 {
90 opp-hz = /bits/ 64 <200000000>;
91 };
92 };
93 };
94
95 bus_fsys: bus-fsys {
96 compatible = "samsung,exynos-bus";
97 clocks = <&clock CLK_ACLK133>;
98 clock-names = "bus";
99 operating-points-v2 = <&bus_fsys_opp_table>;
100 status = "disabled";
101
102 bus_fsys_opp_table: opp-table {
103 compatible = "operating-points-v2";
104
105 opp-100000000 {
106 opp-hz = /bits/ 64 <100000000>;
107 };
108 opp-134000000 {
109 opp-hz = /bits/ 64 <134000000>;
110 };
111 };
112 };
113
114 bus_leftbus: bus-leftbus {
115 compatible = "samsung,exynos-bus";
116 clocks = <&clock CLK_DIV_GDL>;
117 clock-names = "bus";
118 operating-points-v2 = <&bus_leftbus_opp_table>;
119 interconnects = <&bus_dmc>;
120 #interconnect-cells = <0>;
121 status = "disabled";
122 };
123
124 bus_mfc: bus-mfc {
125 compatible = "samsung,exynos-bus";
126 clocks = <&clock CLK_SCLK_MFC>;
127 clock-names = "bus";
128 operating-points-v2 = <&bus_leftbus_opp_table>;
129 status = "disabled";
130 };
131
132 bus_peri: bus-peri {
133 compatible = "samsung,exynos-bus";
134 clocks = <&clock CLK_ACLK100>;
135 clock-names = "bus";
136 operating-points-v2 = <&bus_peri_opp_table>;
137 status = "disabled";
138
139 bus_peri_opp_table: opp-table {
140 compatible = "operating-points-v2";
141
142 opp-50000000 {
143 opp-hz = /bits/ 64 <50000000>;
144 };
145 opp-100000000 {
146 opp-hz = /bits/ 64 <100000000>;
147 };
148 };
149 };
150
151 bus_rightbus: bus-rightbus {
152 compatible = "samsung,exynos-bus";
153 clocks = <&clock CLK_DIV_GDR>;
154 clock-names = "bus";
155 operating-points-v2 = <&bus_leftbus_opp_table>;
156 status = "disabled";
157 };
158
159 bus_dmc_opp_table: opp-table-1 {
160 compatible = "operating-points-v2";
161
162 opp-100000000 {
163 opp-hz = /bits/ 64 <100000000>;
164 opp-microvolt = <900000>;
165 };
166 opp-134000000 {
167 opp-hz = /bits/ 64 <134000000>;
168 opp-microvolt = <900000>;
169 };
170 opp-160000000 {
171 opp-hz = /bits/ 64 <160000000>;
172 opp-microvolt = <900000>;
173 };
174 opp-267000000 {
175 opp-hz = /bits/ 64 <267000000>;
176 opp-microvolt = <950000>;
177 };
178 opp-400000000 {
179 opp-hz = /bits/ 64 <400000000>;
180 opp-microvolt = <1050000>;
181 opp-suspend;
182 };
183 };
184
185 bus_leftbus_opp_table: opp-table-2 {
186 compatible = "operating-points-v2";
187
188 opp-100000000 {
189 opp-hz = /bits/ 64 <100000000>;
190 opp-microvolt = <900000>;
191 };
192 opp-134000000 {
193 opp-hz = /bits/ 64 <134000000>;
194 opp-microvolt = <925000>;
195 };
196 opp-160000000 {
197 opp-hz = /bits/ 64 <160000000>;
198 opp-microvolt = <950000>;
199 };
200 opp-200000000 {
201 opp-hz = /bits/ 64 <200000000>;
202 opp-microvolt = <1000000>;
203 opp-suspend;
204 };
205 };
206
207 soc: soc {
208
209 pinctrl_0: pinctrl@11400000 {
210 compatible = "samsung,exynos4x12-pinctrl";
211 reg = <0x11400000 0x1000>;
212 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 pinctrl_1: pinctrl@11000000 {
216 compatible = "samsung,exynos4x12-pinctrl";
217 reg = <0x11000000 0x1000>;
218 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
219
220 wakup_eint: wakeup-interrupt-controller {
221 compatible = "samsung,exynos4210-wakeup-eint";
222 interrupt-parent = <&gic>;
223 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
224 };
225 };
226
227 pinctrl_2: pinctrl@3860000 {
228 compatible = "samsung,exynos4x12-pinctrl";
229 reg = <0x03860000 0x1000>;
230 interrupt-parent = <&combiner>;
231 interrupts = <10 0>;
232 };
233
234 pinctrl_3: pinctrl@106e0000 {
235 compatible = "samsung,exynos4x12-pinctrl";
236 reg = <0x106e0000 0x1000>;
237 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
238 };
239
240 sram@2020000 {
241 compatible = "mmio-sram";
242 reg = <0x02020000 0x40000>;
243 #address-cells = <1>;
244 #size-cells = <1>;
245 ranges = <0 0x02020000 0x40000>;
246
247 smp-sram@0 {
248 compatible = "samsung,exynos4210-sysram";
249 reg = <0x0 0x1000>;
250 };
251
252 smp-sram@2f000 {
253 compatible = "samsung,exynos4210-sysram-ns";
254 reg = <0x2f000 0x1000>;
255 };
256 };
257
258 pd_isp: power-domain@10023ca0 {
259 compatible = "samsung,exynos4210-pd";
260 reg = <0x10023ca0 0x20>;
261 #power-domain-cells = <0>;
262 label = "ISP";
263 };
264
265 l2c: cache-controller@10502000 {
266 compatible = "arm,pl310-cache";
267 reg = <0x10502000 0x1000>;
268 cache-unified;
269 cache-level = <2>;
270 prefetch-data = <1>;
271 prefetch-instr = <1>;
272 arm,tag-latency = <2 2 1>;
273 arm,data-latency = <3 2 1>;
274 arm,double-linefill = <1>;
275 arm,double-linefill-incr = <0>;
276 arm,double-linefill-wrap = <1>;
277 arm,prefetch-drop = <1>;
278 arm,prefetch-offset = <7>;
279 };
280
281 clock: clock-controller@10030000 {
282 reg = <0x10030000 0x18000>;
283 #clock-cells = <1>;
284 };
285
286 isp_clock: clock-controller@10048000 {
287 compatible = "samsung,exynos4412-isp-clock";
288 reg = <0x10048000 0x1000>;
289 #clock-cells = <1>;
290 power-domains = <&pd_isp>;
291 clocks = <&clock CLK_ACLK200>,
292 <&clock CLK_ACLK400_MCUISP>;
293 clock-names = "aclk200", "aclk400_mcuisp";
294 };
295
296 timer@10050000 {
297 compatible = "samsung,exynos4412-mct";
298 reg = <0x10050000 0x800>;
299 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
300 clock-names = "fin_pll", "mct";
301 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
302 <&combiner 12 5>,
303 <&combiner 12 6>,
304 <&combiner 12 7>,
305 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
306 };
307
308 watchdog: watchdog@10060000 {
309 compatible = "samsung,exynos5250-wdt";
310 reg = <0x10060000 0x100>;
311 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&clock CLK_WDT>;
313 clock-names = "watchdog";
314 samsung,syscon-phandle = <&pmu_system_controller>;
315 };
316
317 adc: adc@126c0000 {
318 compatible = "samsung,exynos4212-adc";
319 reg = <0x126c0000 0x100>;
320 interrupt-parent = <&combiner>;
321 interrupts = <10 3>;
322 clocks = <&clock CLK_TSADC>;
323 clock-names = "adc";
324 #io-channel-cells = <1>;
325 samsung,syscon-phandle = <&pmu_system_controller>;
326 status = "disabled";
327 };
328
329 g2d: g2d@10800000 {
330 compatible = "samsung,exynos4212-g2d";
331 reg = <0x10800000 0x1000>;
332 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
334 clock-names = "sclk_fimg2d", "fimg2d";
335 iommus = <&sysmmu_g2d>;
336 };
337
338 mshc_0: mmc@12550000 {
339 compatible = "samsung,exynos4412-dw-mshc";
340 reg = <0x12550000 0x1000>;
341 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 fifo-depth = <0x80>;
345 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
346 clock-names = "biu", "ciu";
347 status = "disabled";
348 };
349
350 sysmmu_g2d: sysmmu@10a40000 {
351 compatible = "samsung,exynos-sysmmu";
352 reg = <0x10a40000 0x1000>;
353 interrupt-parent = <&combiner>;
354 interrupts = <4 7>;
355 clock-names = "sysmmu", "master";
356 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
357 #iommu-cells = <0>;
358 };
359
360 sysmmu_fimc_isp: sysmmu@12260000 {
361 compatible = "samsung,exynos-sysmmu";
362 reg = <0x12260000 0x1000>;
363 interrupt-parent = <&combiner>;
364 interrupts = <16 2>;
365 power-domains = <&pd_isp>;
366 clock-names = "sysmmu";
367 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
368 #iommu-cells = <0>;
369 };
370
371 sysmmu_fimc_drc: sysmmu@12270000 {
372 compatible = "samsung,exynos-sysmmu";
373 reg = <0x12270000 0x1000>;
374 interrupt-parent = <&combiner>;
375 interrupts = <16 3>;
376 power-domains = <&pd_isp>;
377 clock-names = "sysmmu";
378 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
379 #iommu-cells = <0>;
380 };
381
382 sysmmu_fimc_fd: sysmmu@122a0000 {
383 compatible = "samsung,exynos-sysmmu";
384 reg = <0x122a0000 0x1000>;
385 interrupt-parent = <&combiner>;
386 interrupts = <16 4>;
387 power-domains = <&pd_isp>;
388 clock-names = "sysmmu";
389 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
390 #iommu-cells = <0>;
391 };
392
393 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
394 compatible = "samsung,exynos-sysmmu";
395 reg = <0x122b0000 0x1000>;
396 interrupt-parent = <&combiner>;
397 interrupts = <16 5>;
398 power-domains = <&pd_isp>;
399 clock-names = "sysmmu";
400 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
401 #iommu-cells = <0>;
402 };
403
404 sysmmu_fimc_lite0: sysmmu@123b0000 {
405 compatible = "samsung,exynos-sysmmu";
406 reg = <0x123b0000 0x1000>;
407 interrupt-parent = <&combiner>;
408 interrupts = <16 0>;
409 power-domains = <&pd_isp>;
410 clock-names = "sysmmu", "master";
411 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
412 <&isp_clock CLK_ISP_FIMC_LITE0>;
413 #iommu-cells = <0>;
414 };
415
416 sysmmu_fimc_lite1: sysmmu@123c0000 {
417 compatible = "samsung,exynos-sysmmu";
418 reg = <0x123c0000 0x1000>;
419 interrupt-parent = <&combiner>;
420 interrupts = <16 1>;
421 power-domains = <&pd_isp>;
422 clock-names = "sysmmu", "master";
423 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
424 <&isp_clock CLK_ISP_FIMC_LITE1>;
425 #iommu-cells = <0>;
426 };
427 };
428 };
429
430 &combiner {
431 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
451 };
452
453 &camera {
454 ranges = <0x0 0x11800000 0xba1000>;
455 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
456 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
457 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
458
459 /* fimc_[0-3] are configured outside, under phandles */
460 fimc_lite_0: fimc-lite@b90000 {
461 compatible = "samsung,exynos4212-fimc-lite";
462 reg = <0x00b90000 0x1000>;
463 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
464 power-domains = <&pd_isp>;
465 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
466 clock-names = "flite";
467 iommus = <&sysmmu_fimc_lite0>;
468 status = "disabled";
469 };
470
471 fimc_lite_1: fimc-lite@ba0000 {
472 compatible = "samsung,exynos4212-fimc-lite";
473 reg = <0x00ba0000 0x1000>;
474 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
475 power-domains = <&pd_isp>;
476 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
477 clock-names = "flite";
478 iommus = <&sysmmu_fimc_lite1>;
479 status = "disabled";
480 };
481
482 fimc_is: fimc-is@800000 {
483 compatible = "samsung,exynos4212-fimc-is";
484 reg = <0x00800000 0x260000>;
485 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
487 power-domains = <&pd_isp>;
488 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
489 <&isp_clock CLK_ISP_FIMC_LITE1>,
490 <&isp_clock CLK_ISP_PPMUISPX>,
491 <&isp_clock CLK_ISP_PPMUISPMX>,
492 <&isp_clock CLK_ISP_FIMC_ISP>,
493 <&isp_clock CLK_ISP_FIMC_DRC>,
494 <&isp_clock CLK_ISP_FIMC_FD>,
495 <&isp_clock CLK_ISP_MCUISP>,
496 <&isp_clock CLK_ISP_GICISP>,
497 <&isp_clock CLK_ISP_MCUCTL_ISP>,
498 <&isp_clock CLK_ISP_PWM_ISP>,
499 <&isp_clock CLK_ISP_DIV_ISP0>,
500 <&isp_clock CLK_ISP_DIV_ISP1>,
501 <&isp_clock CLK_ISP_DIV_MCUISP0>,
502 <&isp_clock CLK_ISP_DIV_MCUISP1>,
503 <&clock CLK_MOUT_MPLL_USER_T>,
504 <&clock CLK_ACLK200>,
505 <&clock CLK_ACLK400_MCUISP>,
506 <&clock CLK_DIV_ACLK200>,
507 <&clock CLK_DIV_ACLK400_MCUISP>,
508 <&clock CLK_UART_ISP_SCLK>;
509 clock-names = "lite0", "lite1", "ppmuispx",
510 "ppmuispmx", "isp",
511 "drc", "fd", "mcuisp",
512 "gicisp", "mcuctl_isp", "pwm_isp",
513 "ispdiv0", "ispdiv1", "mcuispdiv0",
514 "mcuispdiv1", "mpll", "aclk200",
515 "aclk400mcuisp", "div_aclk200",
516 "div_aclk400mcuisp", "uart";
517 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
518 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
519 iommu-names = "isp", "drc", "fd", "mcuctl";
520 samsung,pmu-syscon = <&pmu_system_controller>;
521 #address-cells = <1>;
522 #size-cells = <1>;
523 ranges;
524 status = "disabled";
525
526 i2c1_isp: i2c-isp@940000 {
527 compatible = "samsung,exynos4212-i2c-isp";
528 reg = <0x00940000 0x100>;
529 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
530 clock-names = "i2c_isp";
531 #address-cells = <1>;
532 #size-cells = <0>;
533 };
534 };
535 };
536
537 &exynos_usbphy {
538 compatible = "samsung,exynos4x12-usb2-phy";
539 samsung,sysreg-phandle = <&sys_reg>;
540 };
541
542 &fimc_0 {
543 compatible = "samsung,exynos4212-fimc";
544 samsung,pix-limits = <4224 8192 1920 4224>;
545 samsung,mainscaler-ext;
546 samsung,isp-wb;
547 samsung,cam-if;
548 };
549
550 &fimc_1 {
551 compatible = "samsung,exynos4212-fimc";
552 samsung,pix-limits = <4224 8192 1920 4224>;
553 samsung,mainscaler-ext;
554 samsung,isp-wb;
555 samsung,cam-if;
556 };
557
558 &fimc_2 {
559 compatible = "samsung,exynos4212-fimc";
560 samsung,pix-limits = <4224 8192 1920 4224>;
561 samsung,mainscaler-ext;
562 samsung,isp-wb;
563 samsung,lcd-wb;
564 samsung,cam-if;
565 };
566
567 &fimc_3 {
568 compatible = "samsung,exynos4212-fimc";
569 samsung,pix-limits = <1920 8192 1366 1920>;
570 samsung,rotators = <0>;
571 samsung,mainscaler-ext;
572 samsung,isp-wb;
573 samsung,lcd-wb;
574 };
575
576 &gpu {
577 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
588 interrupt-names = "gp",
589 "gpmmu",
590 "pp0",
591 "ppmmu0",
592 "pp1",
593 "ppmmu1",
594 "pp2",
595 "ppmmu2",
596 "pp3",
597 "ppmmu3",
598 "pmu";
599 operating-points-v2 = <&gpu_opp_table>;
600
601 gpu_opp_table: opp-table {
602 compatible = "operating-points-v2";
603
604 opp-160000000 {
605 opp-hz = /bits/ 64 <160000000>;
606 opp-microvolt = <875000>;
607 };
608 opp-267000000 {
609 opp-hz = /bits/ 64 <267000000>;
610 opp-microvolt = <900000>;
611 };
612 opp-350000000 {
613 opp-hz = /bits/ 64 <350000000>;
614 opp-microvolt = <950000>;
615 };
616 opp-440000000 {
617 opp-hz = /bits/ 64 <440000000>;
618 opp-microvolt = <1025000>;
619 };
620 };
621 };
622
623 &hdmi {
624 compatible = "samsung,exynos4212-hdmi";
625 };
626
627 &jpeg_codec {
628 compatible = "samsung,exynos4212-jpeg";
629 };
630
631 &rotator {
632 compatible = "samsung,exynos4212-rotator";
633 };
634
635 &mixer {
636 compatible = "samsung,exynos4212-mixer";
637 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
638 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
639 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
640 interconnects = <&bus_display &bus_dmc>;
641 };
642
643 &pmu_system_controller {
644 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
645 "clkout4", "clkout8", "clkout9";
646 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
647 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
648 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
649 #clock-cells = <1>;
650 };
651
652 &tmu {
653 compatible = "samsung,exynos4412-tmu";
654 interrupt-parent = <&combiner>;
655 interrupts = <2 4>;
656 reg = <0x100c0000 0x100>;
657 clocks = <&clock CLK_TMU_APBIF>;
658 clock-names = "tmu_apbif";
659 status = "disabled";
660 };
661
662 #include "exynos4x12-pinctrl.dtsi"
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