1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Samsung Exynos5420 SoC device tree source
4 *
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung Exynos5420 SoC device nodes are listed in this file.
9 * Exynos5420 based board files can include this file and provide
10 * values for board specific bindings.
11 */
12
13 #include "exynos54xx.dtsi"
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17
18 / {
19 compatible = "samsung,exynos5420", "samsung,exynos5";
20
21 aliases {
22 pinctrl0 = &pinctrl_0;
23 pinctrl1 = &pinctrl_1;
24 pinctrl2 = &pinctrl_2;
25 pinctrl3 = &pinctrl_3;
26 pinctrl4 = &pinctrl_4;
27 i2c8 = &hsi2c_8;
28 i2c9 = &hsi2c_9;
29 i2c10 = &hsi2c_10;
30 gsc0 = &gsc_0;
31 gsc1 = &gsc_1;
32 spi0 = &spi_0;
33 spi1 = &spi_1;
34 spi2 = &spi_2;
35 };
36
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
40 clock-names = "bus";
41 status = "disabled";
42 };
43
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
47 clock-names = "bus";
48 status = "disabled";
49 };
50
51 bus_fsys: bus-fsys {
52 compatible = "samsung,exynos-bus";
53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
54 clock-names = "bus";
55 status = "disabled";
56 };
57
58 bus_fsys2: bus-fsys2 {
59 compatible = "samsung,exynos-bus";
60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
61 clock-names = "bus";
62 status = "disabled";
63 };
64
65 bus_fsys_apb: bus-fsys-apb {
66 compatible = "samsung,exynos-bus";
67 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
68 clock-names = "bus";
69 status = "disabled";
70 };
71
72 bus_g2d: bus-g2d {
73 compatible = "samsung,exynos-bus";
74 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
75 clock-names = "bus";
76 status = "disabled";
77 };
78
79 bus_g2d_acp: bus-g2d-acp {
80 compatible = "samsung,exynos-bus";
81 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
82 clock-names = "bus";
83 status = "disabled";
84 };
85 bus_gen: bus-gen {
86 compatible = "samsung,exynos-bus";
87 clocks = <&clock CLK_DOUT_ACLK266>;
88 clock-names = "bus";
89 status = "disabled";
90 };
91
92 bus_gscl_scaler: bus-gscl-scaler {
93 compatible = "samsung,exynos-bus";
94 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
95 clock-names = "bus";
96 status = "disabled";
97 };
98
99 bus_jpeg: bus-jpeg {
100 compatible = "samsung,exynos-bus";
101 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
102 clock-names = "bus";
103 status = "disabled";
104 };
105
106 bus_jpeg_apb: bus-jpeg-apb {
107 compatible = "samsung,exynos-bus";
108 clocks = <&clock CLK_DOUT_ACLK166>;
109 clock-names = "bus";
110 status = "disabled";
111 };
112
113 bus_mfc: bus-mfc {
114 compatible = "samsung,exynos-bus";
115 clocks = <&clock CLK_DOUT_ACLK333>;
116 clock-names = "bus";
117 status = "disabled";
118 };
119
120 bus_mscl: bus-mscl {
121 compatible = "samsung,exynos-bus";
122 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
123 clock-names = "bus";
124 status = "disabled";
125 };
126
127 bus_noc: bus-noc {
128 compatible = "samsung,exynos-bus";
129 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
130 clock-names = "bus";
131 status = "disabled";
132 };
133
134 bus_peri: bus-peri {
135 compatible = "samsung,exynos-bus";
136 clocks = <&clock CLK_DOUT_ACLK66>;
137 clock-names = "bus";
138 status = "disabled";
139 };
140
141 bus_wcore: bus-wcore {
142 compatible = "samsung,exynos-bus";
143 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
144 clock-names = "bus";
145 status = "disabled";
146 };
147
148 /*
149 * The 'cpus' node is not present here but instead it is provided
150 * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
151 */
152
153 cluster_a15_opp_table: opp-table-0 {
154 compatible = "operating-points-v2";
155 opp-shared;
156
157 opp-1800000000 {
158 opp-hz = /bits/ 64 <1800000000>;
159 opp-microvolt = <1250000 1250000 1500000>;
160 clock-latency-ns = <140000>;
161 };
162 opp-1700000000 {
163 opp-hz = /bits/ 64 <1700000000>;
164 opp-microvolt = <1212500 1212500 1500000>;
165 clock-latency-ns = <140000>;
166 };
167 opp-1600000000 {
168 opp-hz = /bits/ 64 <1600000000>;
169 opp-microvolt = <1175000 1175000 1500000>;
170 clock-latency-ns = <140000>;
171 };
172 opp-1500000000 {
173 opp-hz = /bits/ 64 <1500000000>;
174 opp-microvolt = <1137500 1137500 1500000>;
175 clock-latency-ns = <140000>;
176 };
177 opp-1400000000 {
178 opp-hz = /bits/ 64 <1400000000>;
179 opp-microvolt = <1112500 1112500 1500000>;
180 clock-latency-ns = <140000>;
181 };
182 opp-1300000000 {
183 opp-hz = /bits/ 64 <1300000000>;
184 opp-microvolt = <1062500 1062500 1500000>;
185 clock-latency-ns = <140000>;
186 };
187 opp-1200000000 {
188 opp-hz = /bits/ 64 <1200000000>;
189 opp-microvolt = <1037500 1037500 1500000>;
190 clock-latency-ns = <140000>;
191 };
192 opp-1100000000 {
193 opp-hz = /bits/ 64 <1100000000>;
194 opp-microvolt = <1012500 1012500 1500000>;
195 clock-latency-ns = <140000>;
196 };
197 opp-1000000000 {
198 opp-hz = /bits/ 64 <1000000000>;
199 opp-microvolt = < 987500 987500 1500000>;
200 clock-latency-ns = <140000>;
201 };
202 opp-900000000 {
203 opp-hz = /bits/ 64 <900000000>;
204 opp-microvolt = < 962500 962500 1500000>;
205 clock-latency-ns = <140000>;
206 };
207 opp-800000000 {
208 opp-hz = /bits/ 64 <800000000>;
209 opp-microvolt = < 937500 937500 1500000>;
210 clock-latency-ns = <140000>;
211 };
212 opp-700000000 {
213 opp-hz = /bits/ 64 <700000000>;
214 opp-microvolt = < 912500 912500 1500000>;
215 clock-latency-ns = <140000>;
216 };
217 };
218
219 cluster_a7_opp_table: opp-table-1 {
220 compatible = "operating-points-v2";
221 opp-shared;
222
223 opp-1300000000 {
224 opp-hz = /bits/ 64 <1300000000>;
225 opp-microvolt = <1275000>;
226 clock-latency-ns = <140000>;
227 };
228 opp-1200000000 {
229 opp-hz = /bits/ 64 <1200000000>;
230 opp-microvolt = <1212500>;
231 clock-latency-ns = <140000>;
232 };
233 opp-1100000000 {
234 opp-hz = /bits/ 64 <1100000000>;
235 opp-microvolt = <1162500>;
236 clock-latency-ns = <140000>;
237 };
238 opp-1000000000 {
239 opp-hz = /bits/ 64 <1000000000>;
240 opp-microvolt = <1112500>;
241 clock-latency-ns = <140000>;
242 };
243 opp-900000000 {
244 opp-hz = /bits/ 64 <900000000>;
245 opp-microvolt = <1062500>;
246 clock-latency-ns = <140000>;
247 };
248 opp-800000000 {
249 opp-hz = /bits/ 64 <800000000>;
250 opp-microvolt = <1025000>;
251 clock-latency-ns = <140000>;
252 };
253 opp-700000000 {
254 opp-hz = /bits/ 64 <700000000>;
255 opp-microvolt = <975000>;
256 clock-latency-ns = <140000>;
257 };
258 opp-600000000 {
259 opp-hz = /bits/ 64 <600000000>;
260 opp-microvolt = <937500>;
261 clock-latency-ns = <140000>;
262 };
263 };
264
265 soc: soc {
266 cci: cci@10d20000 {
267 compatible = "arm,cci-400";
268 #address-cells = <1>;
269 #size-cells = <1>;
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
272
273 cci_control0: slave-if@4000 {
274 compatible = "arm,cci-400-ctrl-if";
275 interface-type = "ace";
276 reg = <0x4000 0x1000>;
277 };
278 cci_control1: slave-if@5000 {
279 compatible = "arm,cci-400-ctrl-if";
280 interface-type = "ace";
281 reg = <0x5000 0x1000>;
282 };
283 };
284
285 clock: clock-controller@10010000 {
286 compatible = "samsung,exynos5420-clock", "syscon";
287 reg = <0x10010000 0x30000>;
288 #clock-cells = <1>;
289 };
290
291 clock_audss: audss-clock-controller@3810000 {
292 compatible = "samsung,exynos5420-audss-clock";
293 reg = <0x03810000 0x0c>;
294 #clock-cells = <1>;
295 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
296 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
297 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
298 power-domains = <&mau_pd>;
299 };
300
301 mfc: codec@11000000 {
302 compatible = "samsung,mfc-v7";
303 reg = <0x11000000 0x10000>;
304 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clock CLK_MFC>;
306 clock-names = "mfc";
307 power-domains = <&mfc_pd>;
308 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
309 iommu-names = "left", "right";
310 };
311
312 mmc_0: mmc@12200000 {
313 compatible = "samsung,exynos5420-dw-mshc-smu";
314 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
318 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
319 clock-names = "biu", "ciu";
320 fifo-depth = <0x40>;
321 status = "disabled";
322 };
323
324 mmc_1: mmc@12210000 {
325 compatible = "samsung,exynos5420-dw-mshc-smu";
326 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
327 #address-cells = <1>;
328 #size-cells = <0>;
329 reg = <0x12210000 0x2000>;
330 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
331 clock-names = "biu", "ciu";
332 fifo-depth = <0x40>;
333 status = "disabled";
334 };
335
336 mmc_2: mmc@12220000 {
337 compatible = "samsung,exynos5420-dw-mshc";
338 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 reg = <0x12220000 0x1000>;
342 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
343 clock-names = "biu", "ciu";
344 fifo-depth = <0x40>;
345 status = "disabled";
346 };
347
348 dmc: memory-controller@10c20000 {
349 compatible = "samsung,exynos5422-dmc";
350 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
351 clocks = <&clock CLK_FOUT_SPLL>,
352 <&clock CLK_MOUT_SCLK_SPLL>,
353 <&clock CLK_FF_DOUT_SPLL2>,
354 <&clock CLK_FOUT_BPLL>,
355 <&clock CLK_MOUT_BPLL>,
356 <&clock CLK_SCLK_BPLL>,
357 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
358 <&clock CLK_MOUT_MCLK_CDREX>;
359 clock-names = "fout_spll",
360 "mout_sclk_spll",
361 "ff_dout_spll2",
362 "fout_bpll",
363 "mout_bpll",
364 "sclk_bpll",
365 "mout_mx_mspll_ccore",
366 "mout_mclk_cdrex";
367 samsung,syscon-clk = <&clock>;
368 status = "disabled";
369 };
370
371 nocp_mem0_0: nocp@10ca1000 {
372 compatible = "samsung,exynos5420-nocp";
373 reg = <0x10ca1000 0x200>;
374 status = "disabled";
375 };
376
377 nocp_mem0_1: nocp@10ca1400 {
378 compatible = "samsung,exynos5420-nocp";
379 reg = <0x10ca1400 0x200>;
380 status = "disabled";
381 };
382
383 nocp_mem1_0: nocp@10ca1800 {
384 compatible = "samsung,exynos5420-nocp";
385 reg = <0x10ca1800 0x200>;
386 status = "disabled";
387 };
388
389 nocp_mem1_1: nocp@10ca1c00 {
390 compatible = "samsung,exynos5420-nocp";
391 reg = <0x10ca1c00 0x200>;
392 status = "disabled";
393 };
394
395 nocp_g3d_0: nocp@11a51000 {
396 compatible = "samsung,exynos5420-nocp";
397 reg = <0x11a51000 0x200>;
398 status = "disabled";
399 };
400
401 nocp_g3d_1: nocp@11a51400 {
402 compatible = "samsung,exynos5420-nocp";
403 reg = <0x11a51400 0x200>;
404 status = "disabled";
405 };
406
407 ppmu_dmc0_0: ppmu@10d00000 {
408 compatible = "samsung,exynos-ppmu";
409 reg = <0x10d00000 0x2000>;
410 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
411 clock-names = "ppmu";
412 events {
413 ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 {
414 event-name = "ppmu-event3-dmc0-0";
415 };
416 };
417 };
418
419 ppmu_dmc0_1: ppmu@10d10000 {
420 compatible = "samsung,exynos-ppmu";
421 reg = <0x10d10000 0x2000>;
422 clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
423 clock-names = "ppmu";
424 events {
425 ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 {
426 event-name = "ppmu-event3-dmc0-1";
427 };
428 };
429 };
430
431 ppmu_dmc1_0: ppmu@10d60000 {
432 compatible = "samsung,exynos-ppmu";
433 reg = <0x10d60000 0x2000>;
434 clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
435 clock-names = "ppmu";
436 events {
437 ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 {
438 event-name = "ppmu-event3-dmc1-0";
439 };
440 };
441 };
442
443 ppmu_dmc1_1: ppmu@10d70000 {
444 compatible = "samsung,exynos-ppmu";
445 reg = <0x10d70000 0x2000>;
446 clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
447 clock-names = "ppmu";
448 events {
449 ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 {
450 event-name = "ppmu-event3-dmc1-1";
451 };
452 };
453 };
454
455 gsc_pd: power-domain@10044000 {
456 compatible = "samsung,exynos4210-pd";
457 reg = <0x10044000 0x20>;
458 #power-domain-cells = <0>;
459 label = "GSC";
460 };
461
462 isp_pd: power-domain@10044020 {
463 compatible = "samsung,exynos4210-pd";
464 reg = <0x10044020 0x20>;
465 #power-domain-cells = <0>;
466 label = "ISP";
467 };
468
469 mfc_pd: power-domain@10044060 {
470 compatible = "samsung,exynos4210-pd";
471 reg = <0x10044060 0x20>;
472 #power-domain-cells = <0>;
473 label = "MFC";
474 };
475
476 g3d_pd: power-domain@10044080 {
477 compatible = "samsung,exynos4210-pd";
478 reg = <0x10044080 0x20>;
479 #power-domain-cells = <0>;
480 label = "G3D";
481 };
482
483 disp_pd: power-domain@100440c0 {
484 compatible = "samsung,exynos4210-pd";
485 reg = <0x100440c0 0x20>;
486 #power-domain-cells = <0>;
487 label = "DISP";
488 };
489
490 mau_pd: power-domain@100440e0 {
491 compatible = "samsung,exynos4210-pd";
492 reg = <0x100440e0 0x20>;
493 #power-domain-cells = <0>;
494 label = "MAU";
495 };
496
497 msc_pd: power-domain@10044120 {
498 compatible = "samsung,exynos4210-pd";
499 reg = <0x10044120 0x20>;
500 #power-domain-cells = <0>;
501 label = "MSC";
502 };
503
504 pinctrl_0: pinctrl@13400000 {
505 compatible = "samsung,exynos5420-pinctrl";
506 reg = <0x13400000 0x1000>;
507 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
508
509 wakeup-interrupt-controller {
510 compatible = "samsung,exynos4210-wakeup-eint";
511 interrupt-parent = <&gic>;
512 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
513 };
514 };
515
516 pinctrl_1: pinctrl@13410000 {
517 compatible = "samsung,exynos5420-pinctrl";
518 reg = <0x13410000 0x1000>;
519 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
520 };
521
522 pinctrl_2: pinctrl@14000000 {
523 compatible = "samsung,exynos5420-pinctrl";
524 reg = <0x14000000 0x1000>;
525 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
526 };
527
528 pinctrl_3: pinctrl@14010000 {
529 compatible = "samsung,exynos5420-pinctrl";
530 reg = <0x14010000 0x1000>;
531 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
532 };
533
534 pinctrl_4: pinctrl@3860000 {
535 compatible = "samsung,exynos5420-pinctrl";
536 reg = <0x03860000 0x1000>;
537 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
538 power-domains = <&mau_pd>;
539 };
540
541 adma: dma-controller@3880000 {
542 compatible = "arm,pl330", "arm,primecell";
543 reg = <0x03880000 0x1000>;
544 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&clock_audss EXYNOS_ADMA>;
546 clock-names = "apb_pclk";
547 #dma-cells = <1>;
548 power-domains = <&mau_pd>;
549 };
550
551 pdma0: dma-controller@121a0000 {
552 compatible = "arm,pl330", "arm,primecell";
553 reg = <0x121a0000 0x1000>;
554 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clock CLK_PDMA0>;
556 clock-names = "apb_pclk";
557 #dma-cells = <1>;
558 };
559
560 pdma1: dma-controller@121b0000 {
561 compatible = "arm,pl330", "arm,primecell";
562 reg = <0x121b0000 0x1000>;
563 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clock CLK_PDMA1>;
565 clock-names = "apb_pclk";
566 #dma-cells = <1>;
567 };
568
569 mdma0: dma-controller@10800000 {
570 compatible = "arm,pl330", "arm,primecell";
571 reg = <0x10800000 0x1000>;
572 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clock CLK_MDMA0>;
574 clock-names = "apb_pclk";
575 #dma-cells = <1>;
576 };
577
578 mdma1: dma-controller@11c10000 {
579 compatible = "arm,pl330", "arm,primecell";
580 reg = <0x11c10000 0x1000>;
581 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clock CLK_MDMA1>;
583 clock-names = "apb_pclk";
584 #dma-cells = <1>;
585 /*
586 * MDMA1 can support both secure and non-secure
587 * AXI transactions. When this is enabled in
588 * the kernel for boards that run in secure
589 * mode, we are getting imprecise external
590 * aborts causing the kernel to oops.
591 */
592 status = "disabled";
593 };
594
595 i2s0: i2s@3830000 {
596 compatible = "samsung,exynos5420-i2s";
597 reg = <0x03830000 0x100>;
598 dmas = <&adma 0>,
599 <&adma 2>,
600 <&adma 1>;
601 dma-names = "tx", "rx", "tx-sec";
602 clocks = <&clock_audss EXYNOS_I2S_BUS>,
603 <&clock_audss EXYNOS_I2S_BUS>,
604 <&clock_audss EXYNOS_SCLK_I2S>;
605 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
606 #clock-cells = <1>;
607 clock-output-names = "i2s_cdclk0";
608 #sound-dai-cells = <1>;
609 samsung,idma-addr = <0x03000000>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2s0_bus>;
612 power-domains = <&mau_pd>;
613 status = "disabled";
614 };
615
616 i2s1: i2s@12d60000 {
617 compatible = "samsung,exynos5420-i2s";
618 reg = <0x12d60000 0x100>;
619 dmas = <&pdma1 12>,
620 <&pdma1 11>;
621 dma-names = "tx", "rx";
622 clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
623 clock-names = "iis", "i2s_opclk0";
624 #clock-cells = <1>;
625 clock-output-names = "i2s_cdclk1";
626 #sound-dai-cells = <1>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2s1_bus>;
629 status = "disabled";
630 };
631
632 i2s2: i2s@12d70000 {
633 compatible = "samsung,exynos5420-i2s";
634 reg = <0x12d70000 0x100>;
635 dmas = <&pdma0 12>,
636 <&pdma0 11>;
637 dma-names = "tx", "rx";
638 clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
639 clock-names = "iis", "i2s_opclk0";
640 #clock-cells = <1>;
641 clock-output-names = "i2s_cdclk2";
642 #sound-dai-cells = <1>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2s2_bus>;
645 status = "disabled";
646 };
647
648 spi_0: spi@12d20000 {
649 compatible = "samsung,exynos4210-spi";
650 reg = <0x12d20000 0x100>;
651 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
652 dmas = <&pdma0 5
653 &pdma0 4>;
654 dma-names = "tx", "rx";
655 #address-cells = <1>;
656 #size-cells = <0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&spi0_bus>;
659 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
660 clock-names = "spi", "spi_busclk0";
661 fifo-depth = <256>;
662 status = "disabled";
663 };
664
665 spi_1: spi@12d30000 {
666 compatible = "samsung,exynos4210-spi";
667 reg = <0x12d30000 0x100>;
668 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
669 dmas = <&pdma1 5
670 &pdma1 4>;
671 dma-names = "tx", "rx";
672 #address-cells = <1>;
673 #size-cells = <0>;
674 pinctrl-names = "default";
675 pinctrl-0 = <&spi1_bus>;
676 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
677 clock-names = "spi", "spi_busclk0";
678 fifo-depth = <64>;
679 status = "disabled";
680 };
681
682 spi_2: spi@12d40000 {
683 compatible = "samsung,exynos4210-spi";
684 reg = <0x12d40000 0x100>;
685 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
686 dmas = <&pdma0 7
687 &pdma0 6>;
688 dma-names = "tx", "rx";
689 #address-cells = <1>;
690 #size-cells = <0>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&spi2_bus>;
693 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
694 clock-names = "spi", "spi_busclk0";
695 fifo-depth = <64>;
696 status = "disabled";
697 };
698
699 dsi: dsi@14500000 {
700 compatible = "samsung,exynos5410-mipi-dsi";
701 reg = <0x14500000 0x10000>;
702 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
703 phys = <&mipi_phy 1>;
704 phy-names = "dsim";
705 clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
706 clock-names = "bus_clk", "pll_clk";
707 #address-cells = <1>;
708 #size-cells = <0>;
709 status = "disabled";
710 };
711
712 hsi2c_8: i2c@12e00000 {
713 compatible = "samsung,exynos5250-hsi2c";
714 reg = <0x12e00000 0x1000>;
715 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&i2c8_hs_bus>;
720 clocks = <&clock CLK_USI4>;
721 clock-names = "hsi2c";
722 status = "disabled";
723 };
724
725 hsi2c_9: i2c@12e10000 {
726 compatible = "samsung,exynos5250-hsi2c";
727 reg = <0x12e10000 0x1000>;
728 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
729 #address-cells = <1>;
730 #size-cells = <0>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&i2c9_hs_bus>;
733 clocks = <&clock CLK_USI5>;
734 clock-names = "hsi2c";
735 status = "disabled";
736 };
737
738 hsi2c_10: i2c@12e20000 {
739 compatible = "samsung,exynos5250-hsi2c";
740 reg = <0x12e20000 0x1000>;
741 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
742 #address-cells = <1>;
743 #size-cells = <0>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&i2c10_hs_bus>;
746 clocks = <&clock CLK_USI6>;
747 clock-names = "hsi2c";
748 status = "disabled";
749 };
750
751 hdmi: hdmi@14530000 {
752 compatible = "samsung,exynos5420-hdmi";
753 reg = <0x14530000 0x70000>;
754 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
756 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
757 <&clock CLK_MOUT_HDMI>;
758 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
759 "sclk_hdmiphy", "mout_hdmi";
760 phy = <&hdmiphy>;
761 samsung,syscon-phandle = <&pmu_system_controller>;
762 status = "disabled";
763 power-domains = <&disp_pd>;
764 #sound-dai-cells = <0>;
765 };
766
767 hdmiphy: hdmi-phy@145d0000 {
768 reg = <0x145d0000 0x20>;
769 };
770
771 hdmicec: cec@101b0000 {
772 compatible = "samsung,s5p-cec";
773 reg = <0x101b0000 0x200>;
774 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clock CLK_HDMI_CEC>;
776 clock-names = "hdmicec";
777 samsung,syscon-phandle = <&pmu_system_controller>;
778 hdmi-phandle = <&hdmi>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&hdmi_cec>;
781 status = "disabled";
782 };
783
784 mixer: mixer@14450000 {
785 compatible = "samsung,exynos5420-mixer";
786 reg = <0x14450000 0x10000>;
787 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
789 <&clock CLK_SCLK_HDMI>;
790 clock-names = "mixer", "hdmi", "sclk_hdmi";
791 power-domains = <&disp_pd>;
792 iommus = <&sysmmu_tv>;
793 status = "disabled";
794 };
795
796 rotator: rotator@11c00000 {
797 compatible = "samsung,exynos5250-rotator";
798 reg = <0x11c00000 0x64>;
799 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clock CLK_ROTATOR>;
801 clock-names = "rotator";
802 iommus = <&sysmmu_rotator>;
803 };
804
805 gsc_0: video-scaler@13e00000 {
806 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
807 reg = <0x13e00000 0x1000>;
808 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&clock CLK_GSCL0>;
810 clock-names = "gscl";
811 power-domains = <&gsc_pd>;
812 iommus = <&sysmmu_gscl0>;
813 };
814
815 gsc_1: video-scaler@13e10000 {
816 compatible = "samsung,exynos5420-gsc", "samsung,exynos5-gsc";
817 reg = <0x13e10000 0x1000>;
818 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clock CLK_GSCL1>;
820 clock-names = "gscl";
821 power-domains = <&gsc_pd>;
822 iommus = <&sysmmu_gscl1>;
823 };
824
825 gpu: gpu@11800000 {
826 compatible = "samsung,exynos5420-mali", "arm,mali-t628";
827 reg = <0x11800000 0x5000>;
828 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
831 interrupt-names = "job", "mmu", "gpu";
832
833 clocks = <&clock CLK_G3D>;
834 clock-names = "core";
835 power-domains = <&g3d_pd>;
836 operating-points-v2 = <&gpu_opp_table>;
837
838 status = "disabled";
839 #cooling-cells = <2>;
840
841 gpu_opp_table: opp-table {
842 compatible = "operating-points-v2";
843
844 opp-177000000 {
845 opp-hz = /bits/ 64 <177000000>;
846 opp-microvolt = <812500>;
847 };
848 opp-266000000 {
849 opp-hz = /bits/ 64 <266000000>;
850 opp-microvolt = <862500>;
851 };
852 opp-350000000 {
853 opp-hz = /bits/ 64 <350000000>;
854 opp-microvolt = <912500>;
855 };
856 opp-420000000 {
857 opp-hz = /bits/ 64 <420000000>;
858 opp-microvolt = <962500>;
859 };
860 opp-480000000 {
861 opp-hz = /bits/ 64 <480000000>;
862 opp-microvolt = <1000000>;
863 };
864 opp-543000000 {
865 opp-hz = /bits/ 64 <543000000>;
866 opp-microvolt = <1037500>;
867 };
868 opp-600000000 {
869 opp-hz = /bits/ 64 <600000000>;
870 opp-microvolt = <1150000>;
871 };
872 };
873 };
874
875 scaler_0: scaler@12800000 {
876 compatible = "samsung,exynos5420-scaler";
877 reg = <0x12800000 0x1294>;
878 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clock CLK_MSCL0>;
880 clock-names = "mscl";
881 power-domains = <&msc_pd>;
882 iommus = <&sysmmu_scaler0r>, <&sysmmu_scaler0w>;
883 };
884
885 scaler_1: scaler@12810000 {
886 compatible = "samsung,exynos5420-scaler";
887 reg = <0x12810000 0x1294>;
888 interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&clock CLK_MSCL1>;
890 clock-names = "mscl";
891 power-domains = <&msc_pd>;
892 iommus = <&sysmmu_scaler1r>, <&sysmmu_scaler1w>;
893 };
894
895 scaler_2: scaler@12820000 {
896 compatible = "samsung,exynos5420-scaler";
897 reg = <0x12820000 0x1294>;
898 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&clock CLK_MSCL2>;
900 clock-names = "mscl";
901 power-domains = <&msc_pd>;
902 iommus = <&sysmmu_scaler2r>, <&sysmmu_scaler2w>;
903 };
904
905 jpeg_0: jpeg@11f50000 {
906 compatible = "samsung,exynos5420-jpeg";
907 reg = <0x11f50000 0x1000>;
908 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
909 clock-names = "jpeg";
910 clocks = <&clock CLK_JPEG>;
911 iommus = <&sysmmu_jpeg0>;
912 };
913
914 jpeg_1: jpeg@11f60000 {
915 compatible = "samsung,exynos5420-jpeg";
916 reg = <0x11f60000 0x1000>;
917 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
918 clock-names = "jpeg";
919 clocks = <&clock CLK_JPEG2>;
920 iommus = <&sysmmu_jpeg1>;
921 };
922
923 pmu_system_controller: system-controller@10040000 {
924 compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon";
925 reg = <0x10040000 0x5000>;
926 clock-names = "clkout16";
927 clocks = <&clock CLK_FIN_PLL>;
928 #clock-cells = <1>;
929 interrupt-controller;
930 #interrupt-cells = <3>;
931 interrupt-parent = <&gic>;
932
933 dp_phy: dp-phy {
934 compatible = "samsung,exynos5420-dp-video-phy";
935 #phy-cells = <0>;
936 };
937
938 mipi_phy: mipi-phy {
939 compatible = "samsung,exynos5420-mipi-video-phy";
940 #phy-cells = <1>;
941 };
942 };
943
944 tmu_cpu0: tmu@10060000 {
945 compatible = "samsung,exynos5420-tmu";
946 reg = <0x10060000 0x100>;
947 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&clock CLK_TMU>;
949 clock-names = "tmu_apbif";
950 #thermal-sensor-cells = <0>;
951 };
952
953 tmu_cpu1: tmu@10064000 {
954 compatible = "samsung,exynos5420-tmu";
955 reg = <0x10064000 0x100>;
956 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&clock CLK_TMU>;
958 clock-names = "tmu_apbif";
959 #thermal-sensor-cells = <0>;
960 };
961
962 tmu_cpu2: tmu@10068000 {
963 compatible = "samsung,exynos5420-tmu-ext-triminfo";
964 reg = <0x10068000 0x100>, <0x1006c000 0x4>;
965 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
967 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
968 #thermal-sensor-cells = <0>;
969 };
970
971 tmu_cpu3: tmu@1006c000 {
972 compatible = "samsung,exynos5420-tmu-ext-triminfo";
973 reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
974 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
976 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
977 #thermal-sensor-cells = <0>;
978 };
979
980 tmu_gpu: tmu@100a0000 {
981 compatible = "samsung,exynos5420-tmu-ext-triminfo";
982 reg = <0x100a0000 0x100>, <0x10068000 0x4>;
983 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
985 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
986 #thermal-sensor-cells = <0>;
987 };
988
989 sysmmu_g2dr: sysmmu@10a60000 {
990 compatible = "samsung,exynos-sysmmu";
991 reg = <0x10a60000 0x1000>;
992 interrupt-parent = <&combiner>;
993 interrupts = <24 5>;
994 clock-names = "sysmmu", "master";
995 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
996 #iommu-cells = <0>;
997 };
998
999 sysmmu_g2dw: sysmmu@10a70000 {
1000 compatible = "samsung,exynos-sysmmu";
1001 reg = <0x10a70000 0x1000>;
1002 interrupt-parent = <&combiner>;
1003 interrupts = <22 2>;
1004 clock-names = "sysmmu", "master";
1005 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
1006 #iommu-cells = <0>;
1007 };
1008
1009 sysmmu_tv: sysmmu@14650000 {
1010 compatible = "samsung,exynos-sysmmu";
1011 reg = <0x14650000 0x1000>;
1012 interrupt-parent = <&combiner>;
1013 interrupts = <7 4>;
1014 clock-names = "sysmmu", "master";
1015 clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
1016 power-domains = <&disp_pd>;
1017 #iommu-cells = <0>;
1018 };
1019
1020 sysmmu_gscl0: sysmmu@13e80000 {
1021 compatible = "samsung,exynos-sysmmu";
1022 reg = <0x13e80000 0x1000>;
1023 interrupt-parent = <&combiner>;
1024 interrupts = <2 0>;
1025 clock-names = "sysmmu", "master";
1026 clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
1027 power-domains = <&gsc_pd>;
1028 #iommu-cells = <0>;
1029 };
1030
1031 sysmmu_gscl1: sysmmu@13e90000 {
1032 compatible = "samsung,exynos-sysmmu";
1033 reg = <0x13e90000 0x1000>;
1034 interrupt-parent = <&combiner>;
1035 interrupts = <2 2>;
1036 clock-names = "sysmmu", "master";
1037 clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
1038 power-domains = <&gsc_pd>;
1039 #iommu-cells = <0>;
1040 };
1041
1042 sysmmu_scaler0r: sysmmu@12880000 {
1043 compatible = "samsung,exynos-sysmmu";
1044 reg = <0x12880000 0x1000>;
1045 interrupt-parent = <&combiner>;
1046 interrupts = <22 4>;
1047 clock-names = "sysmmu", "master";
1048 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1049 power-domains = <&msc_pd>;
1050 #iommu-cells = <0>;
1051 };
1052
1053 sysmmu_scaler1r: sysmmu@12890000 {
1054 compatible = "samsung,exynos-sysmmu";
1055 reg = <0x12890000 0x1000>;
1056 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1057 clock-names = "sysmmu", "master";
1058 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1059 power-domains = <&msc_pd>;
1060 #iommu-cells = <0>;
1061 };
1062
1063 sysmmu_scaler2r: sysmmu@128a0000 {
1064 compatible = "samsung,exynos-sysmmu";
1065 reg = <0x128a0000 0x1000>;
1066 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1067 clock-names = "sysmmu", "master";
1068 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1069 power-domains = <&msc_pd>;
1070 #iommu-cells = <0>;
1071 };
1072
1073 sysmmu_scaler0w: sysmmu@128c0000 {
1074 compatible = "samsung,exynos-sysmmu";
1075 reg = <0x128c0000 0x1000>;
1076 interrupt-parent = <&combiner>;
1077 interrupts = <27 2>;
1078 clock-names = "sysmmu", "master";
1079 clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
1080 power-domains = <&msc_pd>;
1081 #iommu-cells = <0>;
1082 };
1083
1084 sysmmu_scaler1w: sysmmu@128d0000 {
1085 compatible = "samsung,exynos-sysmmu";
1086 reg = <0x128d0000 0x1000>;
1087 interrupt-parent = <&combiner>;
1088 interrupts = <22 6>;
1089 clock-names = "sysmmu", "master";
1090 clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
1091 power-domains = <&msc_pd>;
1092 #iommu-cells = <0>;
1093 };
1094
1095 sysmmu_scaler2w: sysmmu@128e0000 {
1096 compatible = "samsung,exynos-sysmmu";
1097 reg = <0x128e0000 0x1000>;
1098 interrupt-parent = <&combiner>;
1099 interrupts = <19 6>;
1100 clock-names = "sysmmu", "master";
1101 clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
1102 power-domains = <&msc_pd>;
1103 #iommu-cells = <0>;
1104 };
1105
1106 sysmmu_rotator: sysmmu@11d40000 {
1107 compatible = "samsung,exynos-sysmmu";
1108 reg = <0x11d40000 0x1000>;
1109 interrupt-parent = <&combiner>;
1110 interrupts = <4 0>;
1111 clock-names = "sysmmu", "master";
1112 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
1113 #iommu-cells = <0>;
1114 };
1115
1116 sysmmu_jpeg0: sysmmu@11f10000 {
1117 compatible = "samsung,exynos-sysmmu";
1118 reg = <0x11f10000 0x1000>;
1119 interrupt-parent = <&combiner>;
1120 interrupts = <4 2>;
1121 clock-names = "sysmmu", "master";
1122 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
1123 #iommu-cells = <0>;
1124 };
1125
1126 sysmmu_jpeg1: sysmmu@11f20000 {
1127 compatible = "samsung,exynos-sysmmu";
1128 reg = <0x11f20000 0x1000>;
1129 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1130 clock-names = "sysmmu", "master";
1131 clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
1132 #iommu-cells = <0>;
1133 };
1134
1135 sysmmu_mfc_l: sysmmu@11200000 {
1136 compatible = "samsung,exynos-sysmmu";
1137 reg = <0x11200000 0x1000>;
1138 interrupt-parent = <&combiner>;
1139 interrupts = <6 2>;
1140 clock-names = "sysmmu", "master";
1141 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
1142 power-domains = <&mfc_pd>;
1143 #iommu-cells = <0>;
1144 };
1145
1146 sysmmu_mfc_r: sysmmu@11210000 {
1147 compatible = "samsung,exynos-sysmmu";
1148 reg = <0x11210000 0x1000>;
1149 interrupt-parent = <&combiner>;
1150 interrupts = <8 5>;
1151 clock-names = "sysmmu", "master";
1152 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
1153 power-domains = <&mfc_pd>;
1154 #iommu-cells = <0>;
1155 };
1156
1157 sysmmu_fimd1_0: sysmmu@14640000 {
1158 compatible = "samsung,exynos-sysmmu";
1159 reg = <0x14640000 0x1000>;
1160 interrupt-parent = <&combiner>;
1161 interrupts = <3 2>;
1162 clock-names = "sysmmu", "master";
1163 clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
1164 power-domains = <&disp_pd>;
1165 #iommu-cells = <0>;
1166 };
1167
1168 sysmmu_fimd1_1: sysmmu@14680000 {
1169 compatible = "samsung,exynos-sysmmu";
1170 reg = <0x14680000 0x1000>;
1171 interrupt-parent = <&combiner>;
1172 interrupts = <3 0>;
1173 clock-names = "sysmmu", "master";
1174 clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
1175 power-domains = <&disp_pd>;
1176 #iommu-cells = <0>;
1177 };
1178 };
1179
1180 thermal-zones {
1181 cpu0_thermal: cpu0-thermal {
1182 thermal-sensors = <&tmu_cpu0>;
1183 #include "exynos5420-trip-points.dtsi"
1184 };
1185 cpu1_thermal: cpu1-thermal {
1186 thermal-sensors = <&tmu_cpu1>;
1187 #include "exynos5420-trip-points.dtsi"
1188 };
1189 cpu2_thermal: cpu2-thermal {
1190 thermal-sensors = <&tmu_cpu2>;
1191 #include "exynos5420-trip-points.dtsi"
1192 };
1193 cpu3_thermal: cpu3-thermal {
1194 thermal-sensors = <&tmu_cpu3>;
1195 #include "exynos5420-trip-points.dtsi"
1196 };
1197 gpu_thermal: gpu-thermal {
1198 thermal-sensors = <&tmu_gpu>;
1199 #include "exynos5420-trip-points.dtsi"
1200 };
1201 };
1202 };
1203
1204 &adc {
1205 clocks = <&clock CLK_TSADC>;
1206 clock-names = "adc";
1207 samsung,syscon-phandle = <&pmu_system_controller>;
1208 };
1209
1210 &dp {
1211 clocks = <&clock CLK_DP1>;
1212 clock-names = "dp";
1213 phys = <&dp_phy>;
1214 phy-names = "dp";
1215 power-domains = <&disp_pd>;
1216 };
1217
1218 &fimd {
1219 compatible = "samsung,exynos5420-fimd";
1220 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1221 clock-names = "sclk_fimd", "fimd";
1222 power-domains = <&disp_pd>;
1223 iommus = <&sysmmu_fimd1_0>, <&sysmmu_fimd1_1>;
1224 iommu-names = "m0", "m1";
1225 };
1226
1227 &g2d {
1228 iommus = <&sysmmu_g2dr>, <&sysmmu_g2dw>;
1229 clocks = <&clock CLK_G2D>;
1230 clock-names = "fimg2d";
1231 status = "okay";
1232 };
1233
1234 &i2c_0 {
1235 clocks = <&clock CLK_I2C0>;
1236 clock-names = "i2c";
1237 pinctrl-names = "default";
1238 pinctrl-0 = <&i2c0_bus>;
1239 };
1240
1241 &i2c_1 {
1242 clocks = <&clock CLK_I2C1>;
1243 clock-names = "i2c";
1244 pinctrl-names = "default";
1245 pinctrl-0 = <&i2c1_bus>;
1246 };
1247
1248 &i2c_2 {
1249 clocks = <&clock CLK_I2C2>;
1250 clock-names = "i2c";
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&i2c2_bus>;
1253 };
1254
1255 &i2c_3 {
1256 clocks = <&clock CLK_I2C3>;
1257 clock-names = "i2c";
1258 pinctrl-names = "default";
1259 pinctrl-0 = <&i2c3_bus>;
1260 };
1261
1262 &hsi2c_4 {
1263 clocks = <&clock CLK_USI0>;
1264 clock-names = "hsi2c";
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&i2c4_hs_bus>;
1267 };
1268
1269 &hsi2c_5 {
1270 clocks = <&clock CLK_USI1>;
1271 clock-names = "hsi2c";
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&i2c5_hs_bus>;
1274 };
1275
1276 &hsi2c_6 {
1277 clocks = <&clock CLK_USI2>;
1278 clock-names = "hsi2c";
1279 pinctrl-names = "default";
1280 pinctrl-0 = <&i2c6_hs_bus>;
1281 };
1282
1283 &hsi2c_7 {
1284 clocks = <&clock CLK_USI3>;
1285 clock-names = "hsi2c";
1286 pinctrl-names = "default";
1287 pinctrl-0 = <&i2c7_hs_bus>;
1288 };
1289
1290 &mct {
1291 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
1292 clock-names = "fin_pll", "mct";
1293 };
1294
1295 &prng {
1296 clocks = <&clock CLK_SSS>;
1297 clock-names = "secss";
1298 };
1299
1300 &pwm {
1301 clocks = <&clock CLK_PWM>;
1302 clock-names = "timers";
1303 };
1304
1305 &rtc {
1306 clocks = <&clock CLK_RTC>;
1307 clock-names = "rtc";
1308 interrupt-parent = <&pmu_system_controller>;
1309 status = "disabled";
1310 };
1311
1312 &serial_0 {
1313 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1314 clock-names = "uart", "clk_uart_baud0";
1315 dmas = <&pdma0 13>, <&pdma0 14>;
1316 dma-names = "rx", "tx";
1317 };
1318
1319 &serial_1 {
1320 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1321 clock-names = "uart", "clk_uart_baud0";
1322 dmas = <&pdma1 15>, <&pdma1 16>;
1323 dma-names = "rx", "tx";
1324 };
1325
1326 &serial_2 {
1327 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1328 clock-names = "uart", "clk_uart_baud0";
1329 dmas = <&pdma0 15>, <&pdma0 16>;
1330 dma-names = "rx", "tx";
1331 };
1332
1333 &serial_3 {
1334 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1335 clock-names = "uart", "clk_uart_baud0";
1336 dmas = <&pdma1 17>, <&pdma1 18>;
1337 dma-names = "rx", "tx";
1338 };
1339
1340 &sss {
1341 clocks = <&clock CLK_SSS>;
1342 clock-names = "secss";
1343 };
1344
1345 &trng {
1346 clocks = <&clock CLK_SSS>;
1347 clock-names = "secss";
1348 };
1349
1350 &usbdrd3_0 {
1351 clocks = <&clock CLK_USBD300>;
1352 clock-names = "usbdrd30";
1353 };
1354
1355 &usbdrd_phy0 {
1356 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1357 clock-names = "phy", "ref";
1358 samsung,pmu-syscon = <&pmu_system_controller>;
1359 };
1360
1361 &usbdrd3_1 {
1362 clocks = <&clock CLK_USBD301>;
1363 clock-names = "usbdrd30";
1364 };
1365
1366 &usbdrd_dwc3_1 {
1367 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1368 };
1369
1370 &usbdrd_phy1 {
1371 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1372 clock-names = "phy", "ref";
1373 samsung,pmu-syscon = <&pmu_system_controller>;
1374 };
1375
1376 &usbhost1 {
1377 clocks = <&clock CLK_USBH20>;
1378 clock-names = "usbhost";
1379 };
1380
1381 &usbhost2 {
1382 clocks = <&clock CLK_USBH20>;
1383 clock-names = "usbhost";
1384 };
1385
1386 &usb2_phy {
1387 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1388 clock-names = "phy", "ref";
1389 samsung,sysreg-phandle = <&sysreg_system_controller>;
1390 samsung,pmureg-phandle = <&pmu_system_controller>;
1391 };
1392
1393 &watchdog {
1394 clocks = <&clock CLK_WDT>;
1395 clock-names = "watchdog";
1396 samsung,syscon-phandle = <&pmu_system_controller>;
1397 };
1398
1399 #include "exynos5420-pinctrl.dtsi"
1400 #include "exynos-syscon-restart.dtsi"
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