1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
4 *
5 * Copyright (c) 2017 Marek Szyprowski
6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
8 */
9
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "exynos5800.dtsi"
14 #include "exynos5422-cpus.dtsi"
15
16 / {
17 memory@40000000 {
18 device_type = "memory";
19 reg = <0x40000000 0x7ea00000>;
20 };
21
22 aliases {
23 mmc2 = &mmc_2;
24 };
25
26 chosen {
27 stdout-path = "serial2:115200n8";
28 };
29
30 firmware@2073000 {
31 compatible = "samsung,secure-firmware";
32 reg = <0x02073000 0x1000>;
33 };
34
35 fixed-rate-clocks {
36 oscclk {
37 compatible = "samsung,exynos5420-oscclk";
38 clock-frequency = <24000000>;
39 };
40 };
41
42 bus_wcore_opp_table: opp-table-2 {
43 compatible = "operating-points-v2";
44
45 /* derived from 532MHz MPLL */
46 opp00 {
47 opp-hz = /bits/ 64 <88700000>;
48 opp-microvolt = <925000 925000 1400000>;
49 };
50 opp01 {
51 opp-hz = /bits/ 64 <133000000>;
52 opp-microvolt = <950000 950000 1400000>;
53 };
54 opp02 {
55 opp-hz = /bits/ 64 <177400000>;
56 opp-microvolt = <950000 950000 1400000>;
57 };
58 opp03 {
59 opp-hz = /bits/ 64 <266000000>;
60 opp-microvolt = <950000 950000 1400000>;
61 };
62 opp04 {
63 opp-hz = /bits/ 64 <532000000>;
64 opp-microvolt = <1000000 1000000 1400000>;
65 };
66 };
67
68 bus_noc_opp_table: opp-table-3 {
69 compatible = "operating-points-v2";
70
71 /* derived from 666MHz CPLL */
72 opp00 {
73 opp-hz = /bits/ 64 <66600000>;
74 };
75 opp01 {
76 opp-hz = /bits/ 64 <74000000>;
77 };
78 opp02 {
79 opp-hz = /bits/ 64 <83250000>;
80 };
81 opp03 {
82 opp-hz = /bits/ 64 <111000000>;
83 };
84 };
85
86 bus_fsys_apb_opp_table: opp-table-4 {
87 compatible = "operating-points-v2";
88
89 /* derived from 666MHz CPLL */
90 opp00 {
91 opp-hz = /bits/ 64 <111000000>;
92 };
93 opp01 {
94 opp-hz = /bits/ 64 <222000000>;
95 };
96 };
97
98 bus_fsys2_opp_table: opp-table-5 {
99 compatible = "operating-points-v2";
100
101 /* derived from 600MHz DPLL */
102 opp00 {
103 opp-hz = /bits/ 64 <75000000>;
104 };
105 opp01 {
106 opp-hz = /bits/ 64 <120000000>;
107 };
108 opp02 {
109 opp-hz = /bits/ 64 <200000000>;
110 };
111 };
112
113 bus_mfc_opp_table: opp-table-6 {
114 compatible = "operating-points-v2";
115
116 /* derived from 666MHz CPLL */
117 opp00 {
118 opp-hz = /bits/ 64 <83250000>;
119 };
120 opp01 {
121 opp-hz = /bits/ 64 <111000000>;
122 };
123 opp02 {
124 opp-hz = /bits/ 64 <166500000>;
125 };
126 opp03 {
127 opp-hz = /bits/ 64 <222000000>;
128 };
129 opp04 {
130 opp-hz = /bits/ 64 <333000000>;
131 };
132 };
133
134 bus_gen_opp_table: opp-table-7 {
135 compatible = "operating-points-v2";
136
137 /* derived from 532MHz MPLL */
138 opp00 {
139 opp-hz = /bits/ 64 <88700000>;
140 };
141 opp01 {
142 opp-hz = /bits/ 64 <133000000>;
143 };
144 opp02 {
145 opp-hz = /bits/ 64 <178000000>;
146 };
147 opp03 {
148 opp-hz = /bits/ 64 <266000000>;
149 };
150 };
151
152 bus_peri_opp_table: opp-table-8 {
153 compatible = "operating-points-v2";
154
155 /* derived from 666MHz CPLL */
156 opp00 {
157 opp-hz = /bits/ 64 <66600000>;
158 };
159 };
160
161 bus_g2d_opp_table: opp-table-9 {
162 compatible = "operating-points-v2";
163
164 /* derived from 666MHz CPLL */
165 opp00 {
166 opp-hz = /bits/ 64 <83250000>;
167 };
168 opp01 {
169 opp-hz = /bits/ 64 <111000000>;
170 };
171 opp02 {
172 opp-hz = /bits/ 64 <166500000>;
173 };
174 opp03 {
175 opp-hz = /bits/ 64 <222000000>;
176 };
177 opp04 {
178 opp-hz = /bits/ 64 <333000000>;
179 };
180 };
181
182 bus_g2d_acp_opp_table: opp-table-10 {
183 compatible = "operating-points-v2";
184
185 /* derived from 532MHz MPLL */
186 opp00 {
187 opp-hz = /bits/ 64 <66500000>;
188 };
189 opp01 {
190 opp-hz = /bits/ 64 <133000000>;
191 };
192 opp02 {
193 opp-hz = /bits/ 64 <178000000>;
194 };
195 opp03 {
196 opp-hz = /bits/ 64 <266000000>;
197 };
198 };
199
200 bus_jpeg_opp_table: opp-table-11 {
201 compatible = "operating-points-v2";
202
203 /* derived from 600MHz DPLL */
204 opp00 {
205 opp-hz = /bits/ 64 <75000000>;
206 };
207 opp01 {
208 opp-hz = /bits/ 64 <150000000>;
209 };
210 opp02 {
211 opp-hz = /bits/ 64 <200000000>;
212 };
213 opp03 {
214 opp-hz = /bits/ 64 <300000000>;
215 };
216 };
217
218 bus_jpeg_apb_opp_table: opp-table-12 {
219 compatible = "operating-points-v2";
220
221 /* derived from 666MHz CPLL */
222 opp00 {
223 opp-hz = /bits/ 64 <83250000>;
224 };
225 opp01 {
226 opp-hz = /bits/ 64 <111000000>;
227 };
228 opp02 {
229 opp-hz = /bits/ 64 <133000000>;
230 };
231 opp03 {
232 opp-hz = /bits/ 64 <166500000>;
233 };
234 };
235
236 bus_disp1_fimd_opp_table: opp-table-13 {
237 compatible = "operating-points-v2";
238
239 /* derived from 600MHz DPLL */
240 opp00 {
241 opp-hz = /bits/ 64 <120000000>;
242 };
243 opp01 {
244 opp-hz = /bits/ 64 <200000000>;
245 };
246 };
247
248 bus_disp1_opp_table: opp-table-14 {
249 compatible = "operating-points-v2";
250
251 /* derived from 600MHz DPLL */
252 opp00 {
253 opp-hz = /bits/ 64 <120000000>;
254 };
255 opp01 {
256 opp-hz = /bits/ 64 <200000000>;
257 };
258 opp02 {
259 opp-hz = /bits/ 64 <300000000>;
260 };
261 };
262
263 bus_gscl_opp_table: opp-table-15 {
264 compatible = "operating-points-v2";
265
266 /* derived from 600MHz DPLL */
267 opp00 {
268 opp-hz = /bits/ 64 <150000000>;
269 };
270 opp01 {
271 opp-hz = /bits/ 64 <200000000>;
272 };
273 opp02 {
274 opp-hz = /bits/ 64 <300000000>;
275 };
276 };
277
278 bus_mscl_opp_table: opp-table-16 {
279 compatible = "operating-points-v2";
280
281 /* derived from 666MHz CPLL */
282 opp00 {
283 opp-hz = /bits/ 64 <84000000>;
284 };
285 opp01 {
286 opp-hz = /bits/ 64 <167000000>;
287 };
288 opp02 {
289 opp-hz = /bits/ 64 <222000000>;
290 };
291 opp03 {
292 opp-hz = /bits/ 64 <333000000>;
293 };
294 opp04 {
295 opp-hz = /bits/ 64 <666000000>;
296 };
297 };
298
299 dmc_opp_table: opp-table-17 {
300 compatible = "operating-points-v2";
301
302 opp00 {
303 opp-hz = /bits/ 64 <165000000>;
304 opp-microvolt = <875000>;
305 };
306 opp01 {
307 opp-hz = /bits/ 64 <206000000>;
308 opp-microvolt = <875000>;
309 };
310 opp02 {
311 opp-hz = /bits/ 64 <275000000>;
312 opp-microvolt = <875000>;
313 };
314 opp03 {
315 opp-hz = /bits/ 64 <413000000>;
316 opp-microvolt = <887500>;
317 };
318 opp04 {
319 opp-hz = /bits/ 64 <543000000>;
320 opp-microvolt = <937500>;
321 };
322 opp05 {
323 opp-hz = /bits/ 64 <633000000>;
324 opp-microvolt = <1012500>;
325 };
326 opp06 {
327 opp-hz = /bits/ 64 <728000000>;
328 opp-microvolt = <1037500>;
329 };
330 opp07 {
331 opp-hz = /bits/ 64 <825000000>;
332 opp-microvolt = <1050000>;
333 };
334 };
335
336 samsung_K3QF2F20DB: lpddr3 {
337 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
338 density = <16384>;
339 io-width = <32>;
340
341 tRFC-min-tck = <17>;
342 tRRD-min-tck = <2>;
343 tRPab-min-tck = <2>;
344 tRPpb-min-tck = <2>;
345 tRCD-min-tck = <3>;
346 tRC-min-tck = <6>;
347 tRAS-min-tck = <5>;
348 tWTR-min-tck = <2>;
349 tWR-min-tck = <7>;
350 tRTP-min-tck = <2>;
351 tW2W-C2C-min-tck = <0>;
352 tR2R-C2C-min-tck = <0>;
353 tWL-min-tck = <8>;
354 tDQSCK-min-tck = <5>;
355 tRL-min-tck = <14>;
356 tFAW-min-tck = <5>;
357 tXSR-min-tck = <12>;
358 tXP-min-tck = <2>;
359 tCKE-min-tck = <2>;
360 tCKESR-min-tck = <2>;
361 tMRD-min-tck = <5>;
362
363 timings_samsung_K3QF2F20DB_800mhz: timings {
364 compatible = "jedec,lpddr3-timings";
365 max-freq = <800000000>;
366 min-freq = <100000000>;
367 tRFC = <65000>;
368 tRRD = <6000>;
369 tRPab = <12000>;
370 tRPpb = <12000>;
371 tRCD = <10000>;
372 tRC = <33750>;
373 tRAS = <23000>;
374 tWTR = <3750>;
375 tWR = <7500>;
376 tRTP = <3750>;
377 tW2W-C2C = <0>;
378 tR2R-C2C = <0>;
379 tFAW = <25000>;
380 tXSR = <70000>;
381 tXP = <3750>;
382 tCKE = <3750>;
383 tCKESR = <3750>;
384 tMRD = <7000>;
385 };
386 };
387 };
388
389 &adc {
390 vdd-supply = <&ldo4_reg>;
391 status = "okay";
392 };
393
394 &bus_wcore {
395 operating-points-v2 = <&bus_wcore_opp_table>;
396 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
397 <&nocp_mem1_0>, <&nocp_mem1_1>;
398 vdd-supply = <&buck3_reg>;
399 exynos,saturation-ratio = <100>;
400 status = "okay";
401 };
402
403 &bus_noc {
404 operating-points-v2 = <&bus_noc_opp_table>;
405 devfreq = <&bus_wcore>;
406 status = "okay";
407 };
408
409 &bus_fsys_apb {
410 operating-points-v2 = <&bus_fsys_apb_opp_table>;
411 devfreq = <&bus_wcore>;
412 status = "okay";
413 };
414
415 &bus_fsys2 {
416 operating-points-v2 = <&bus_fsys2_opp_table>;
417 devfreq = <&bus_wcore>;
418 status = "okay";
419 };
420
421 &bus_mfc {
422 operating-points-v2 = <&bus_mfc_opp_table>;
423 devfreq = <&bus_wcore>;
424 status = "okay";
425 };
426
427 &bus_gen {
428 operating-points-v2 = <&bus_gen_opp_table>;
429 devfreq = <&bus_wcore>;
430 status = "okay";
431 };
432
433 &bus_peri {
434 operating-points-v2 = <&bus_peri_opp_table>;
435 devfreq = <&bus_wcore>;
436 status = "okay";
437 };
438
439 &bus_g2d {
440 operating-points-v2 = <&bus_g2d_opp_table>;
441 devfreq = <&bus_wcore>;
442 status = "okay";
443 };
444
445 &bus_g2d_acp {
446 operating-points-v2 = <&bus_g2d_acp_opp_table>;
447 devfreq = <&bus_wcore>;
448 status = "okay";
449 };
450
451 &bus_jpeg {
452 operating-points-v2 = <&bus_jpeg_opp_table>;
453 devfreq = <&bus_wcore>;
454 status = "okay";
455 };
456
457 &bus_jpeg_apb {
458 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
459 devfreq = <&bus_wcore>;
460 status = "okay";
461 };
462
463 &bus_disp1_fimd {
464 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
465 devfreq = <&bus_wcore>;
466 status = "okay";
467 };
468
469 &bus_disp1 {
470 operating-points-v2 = <&bus_disp1_opp_table>;
471 devfreq = <&bus_wcore>;
472 status = "okay";
473 };
474
475 &bus_gscl_scaler {
476 operating-points-v2 = <&bus_gscl_opp_table>;
477 devfreq = <&bus_wcore>;
478 status = "okay";
479 };
480
481 &bus_mscl {
482 operating-points-v2 = <&bus_mscl_opp_table>;
483 devfreq = <&bus_wcore>;
484 status = "okay";
485 };
486
487 &cpu0 {
488 cpu-supply = <&buck6_reg>;
489 };
490
491 &cpu4 {
492 cpu-supply = <&buck2_reg>;
493 };
494
495 &dmc {
496 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
497 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
498 device-handle = <&samsung_K3QF2F20DB>;
499 operating-points-v2 = <&dmc_opp_table>;
500 vdd-supply = <&buck1_reg>;
501 status = "okay";
502 };
503
504 &hsi2c_4 {
505 status = "okay";
506
507 pmic@66 {
508 compatible = "samsung,s2mps11-pmic";
509 reg = <0x66>;
510 samsung,s2mps11-acokb-ground;
511
512 interrupt-parent = <&gpx0>;
513 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&s2mps11_irq>;
516 wakeup-source;
517
518 s2mps11_osc: clocks {
519 compatible = "samsung,s2mps11-clk";
520 #clock-cells = <1>;
521 clock-output-names = "s2mps11_ap",
522 "s2mps11_cp", "s2mps11_bt";
523 };
524
525 regulators {
526 ldo1_reg: LDO1 {
527 regulator-name = "vdd_ldo1";
528 regulator-min-microvolt = <1000000>;
529 regulator-max-microvolt = <1000000>;
530 regulator-always-on;
531 };
532
533 ldo2_reg: LDO2 {
534 regulator-name = "vdd_ldo2";
535 regulator-min-microvolt = <1800000>;
536 regulator-max-microvolt = <1800000>;
537 regulator-always-on;
538 };
539
540 ldo3_reg: LDO3 {
541 regulator-name = "vddq_mmc0";
542 regulator-min-microvolt = <1800000>;
543 regulator-max-microvolt = <1800000>;
544 };
545
546 ldo4_reg: LDO4 {
547 regulator-name = "vdd_adc";
548 regulator-min-microvolt = <1800000>;
549 regulator-max-microvolt = <1800000>;
550
551 regulator-state-mem {
552 regulator-off-in-suspend;
553 };
554 };
555
556 ldo5_reg: LDO5 {
557 regulator-name = "vdd_ldo5";
558 regulator-min-microvolt = <1800000>;
559 regulator-max-microvolt = <1800000>;
560 regulator-always-on;
561
562 regulator-state-mem {
563 regulator-off-in-suspend;
564 };
565 };
566
567 ldo6_reg: LDO6 {
568 regulator-name = "vdd_ldo6";
569 regulator-min-microvolt = <1000000>;
570 regulator-max-microvolt = <1000000>;
571 regulator-always-on;
572
573 regulator-state-mem {
574 regulator-off-in-suspend;
575 };
576 };
577
578 ldo7_reg: LDO7 {
579 regulator-name = "vdd_ldo7";
580 regulator-min-microvolt = <1800000>;
581 regulator-max-microvolt = <1800000>;
582 regulator-always-on;
583
584 regulator-state-mem {
585 regulator-off-in-suspend;
586 };
587 };
588
589 ldo8_reg: LDO8 {
590 regulator-name = "vdd_ldo8";
591 regulator-min-microvolt = <1800000>;
592 regulator-max-microvolt = <1800000>;
593 regulator-always-on;
594
595 regulator-state-mem {
596 regulator-off-in-suspend;
597 };
598 };
599
600 ldo9_reg: LDO9 {
601 regulator-name = "vdd_ldo9";
602 regulator-min-microvolt = <3000000>;
603 regulator-max-microvolt = <3000000>;
604 regulator-always-on;
605
606 regulator-state-mem {
607 regulator-off-in-suspend;
608 };
609 };
610
611 ldo10_reg: LDO10 {
612 regulator-name = "vdd_ldo10";
613 regulator-min-microvolt = <1800000>;
614 regulator-max-microvolt = <1800000>;
615 regulator-always-on;
616
617 regulator-state-mem {
618 regulator-off-in-suspend;
619 };
620 };
621
622 ldo11_reg: LDO11 {
623 regulator-name = "vdd_ldo11";
624 regulator-min-microvolt = <1000000>;
625 regulator-max-microvolt = <1000000>;
626 regulator-always-on;
627
628 regulator-state-mem {
629 regulator-off-in-suspend;
630 };
631 };
632
633 ldo12_reg: LDO12 {
634 /* Unused */
635 regulator-name = "vdd_ldo12";
636 regulator-min-microvolt = <800000>;
637 regulator-max-microvolt = <2375000>;
638 };
639
640 ldo13_reg: LDO13 {
641 regulator-name = "vddq_mmc2";
642 regulator-min-microvolt = <1800000>;
643 regulator-max-microvolt = <2800000>;
644
645 regulator-state-mem {
646 regulator-off-in-suspend;
647 };
648 };
649
650 ldo14_reg: LDO14 {
651 /* Unused */
652 regulator-name = "vdd_ldo14";
653 regulator-min-microvolt = <800000>;
654 regulator-max-microvolt = <3950000>;
655 };
656
657 ldo15_reg: LDO15 {
658 regulator-name = "vdd_ldo15";
659 regulator-min-microvolt = <3300000>;
660 regulator-max-microvolt = <3300000>;
661 regulator-always-on;
662
663 regulator-state-mem {
664 regulator-off-in-suspend;
665 };
666 };
667
668 ldo16_reg: LDO16 {
669 /* Unused */
670 regulator-name = "vdd_ldo16";
671 regulator-min-microvolt = <800000>;
672 regulator-max-microvolt = <3950000>;
673 };
674
675 ldo17_reg: LDO17 {
676 regulator-name = "vdd_ldo17";
677 regulator-min-microvolt = <3300000>;
678 regulator-max-microvolt = <3300000>;
679 regulator-always-on;
680
681 regulator-state-mem {
682 regulator-off-in-suspend;
683 };
684 };
685
686 ldo18_reg: LDO18 {
687 regulator-name = "vdd_emmc_1V8";
688 regulator-min-microvolt = <1800000>;
689 regulator-max-microvolt = <1800000>;
690
691 regulator-state-mem {
692 regulator-off-in-suspend;
693 };
694 };
695
696 ldo19_reg: LDO19 {
697 regulator-name = "vdd_sd";
698 regulator-min-microvolt = <2800000>;
699 regulator-max-microvolt = <2800000>;
700
701 regulator-state-mem {
702 regulator-off-in-suspend;
703 };
704 };
705
706 ldo20_reg: LDO20 {
707 /* Unused */
708 regulator-name = "vdd_ldo20";
709 regulator-min-microvolt = <800000>;
710 regulator-max-microvolt = <3950000>;
711 };
712
713 ldo21_reg: LDO21 {
714 /* Unused */
715 regulator-name = "vdd_ldo21";
716 regulator-min-microvolt = <800000>;
717 regulator-max-microvolt = <3950000>;
718 };
719
720 ldo22_reg: LDO22 {
721 /* Unused */
722 regulator-name = "vdd_ldo22";
723 regulator-min-microvolt = <800000>;
724 regulator-max-microvolt = <2375000>;
725 };
726
727 ldo23_reg: LDO23 {
728 regulator-name = "vdd_mifs";
729 regulator-min-microvolt = <1100000>;
730 regulator-max-microvolt = <1100000>;
731 regulator-always-on;
732
733 regulator-state-mem {
734 regulator-off-in-suspend;
735 };
736 };
737
738 ldo24_reg: LDO24 {
739 /* Unused */
740 regulator-name = "vdd_ldo24";
741 regulator-min-microvolt = <800000>;
742 regulator-max-microvolt = <3950000>;
743 };
744
745 ldo25_reg: LDO25 {
746 /* Unused */
747 regulator-name = "vdd_ldo25";
748 regulator-min-microvolt = <800000>;
749 regulator-max-microvolt = <3950000>;
750 };
751
752 ldo26_reg: LDO26 {
753 /* Used on XU3, XU3-Lite and XU4 */
754 regulator-name = "vdd_ldo26";
755 regulator-min-microvolt = <800000>;
756 regulator-max-microvolt = <3950000>;
757
758 regulator-state-mem {
759 regulator-off-in-suspend;
760 };
761 };
762
763 ldo27_reg: LDO27 {
764 regulator-name = "vdd_g3ds";
765 regulator-min-microvolt = <1000000>;
766 regulator-max-microvolt = <1000000>;
767 regulator-always-on;
768
769 regulator-state-mem {
770 regulator-off-in-suspend;
771 };
772 };
773
774 ldo28_reg: LDO28 {
775 /* Used on XU3 */
776 regulator-name = "vdd_ldo28";
777 regulator-min-microvolt = <800000>;
778 regulator-max-microvolt = <3950000>;
779
780 regulator-state-mem {
781 regulator-off-in-suspend;
782 };
783 };
784
785 ldo29_reg: LDO29 {
786 /* Unused */
787 regulator-name = "vdd_ldo29";
788 regulator-min-microvolt = <800000>;
789 regulator-max-microvolt = <3950000>;
790 };
791
792 ldo30_reg: LDO30 {
793 /* Unused */
794 regulator-name = "vdd_ldo30";
795 regulator-min-microvolt = <800000>;
796 regulator-max-microvolt = <3950000>;
797 };
798
799 ldo31_reg: LDO31 {
800 /* Unused */
801 regulator-name = "vdd_ldo31";
802 regulator-min-microvolt = <800000>;
803 regulator-max-microvolt = <3950000>;
804 };
805
806 ldo32_reg: LDO32 {
807 /* Unused */
808 regulator-name = "vdd_ldo32";
809 regulator-min-microvolt = <800000>;
810 regulator-max-microvolt = <3950000>;
811 };
812
813 ldo33_reg: LDO33 {
814 /* Unused */
815 regulator-name = "vdd_ldo33";
816 regulator-min-microvolt = <800000>;
817 regulator-max-microvolt = <3950000>;
818 };
819
820 ldo34_reg: LDO34 {
821 /* Unused */
822 regulator-name = "vdd_ldo34";
823 regulator-min-microvolt = <800000>;
824 regulator-max-microvolt = <3950000>;
825 };
826
827 ldo35_reg: LDO35 {
828 /* Unused */
829 regulator-name = "vdd_ldo35";
830 regulator-min-microvolt = <800000>;
831 regulator-max-microvolt = <2375000>;
832 };
833
834 ldo36_reg: LDO36 {
835 /* Unused */
836 regulator-name = "vdd_ldo36";
837 regulator-min-microvolt = <800000>;
838 regulator-max-microvolt = <3950000>;
839 };
840
841 ldo37_reg: LDO37 {
842 /* Unused */
843 regulator-name = "vdd_ldo37";
844 regulator-min-microvolt = <800000>;
845 regulator-max-microvolt = <3950000>;
846 };
847
848 ldo38_reg: LDO38 {
849 /* Unused */
850 regulator-name = "vdd_ldo38";
851 regulator-min-microvolt = <800000>;
852 regulator-max-microvolt = <3950000>;
853 };
854
855 buck1_reg: BUCK1 {
856 regulator-name = "vdd_mif";
857 regulator-min-microvolt = <800000>;
858 regulator-max-microvolt = <1300000>;
859 regulator-always-on;
860 regulator-boot-on;
861
862 regulator-state-mem {
863 regulator-off-in-suspend;
864 };
865 };
866
867 buck2_reg: BUCK2 {
868 regulator-name = "vdd_arm";
869 regulator-min-microvolt = <800000>;
870 regulator-max-microvolt = <1500000>;
871 regulator-always-on;
872 regulator-boot-on;
873 regulator-coupled-with = <&buck3_reg>;
874 regulator-coupled-max-spread = <300000>;
875
876 regulator-state-mem {
877 regulator-off-in-suspend;
878 };
879 };
880
881 buck3_reg: BUCK3 {
882 regulator-name = "vdd_int";
883 regulator-min-microvolt = <800000>;
884 regulator-max-microvolt = <1400000>;
885 regulator-always-on;
886 regulator-boot-on;
887 regulator-coupled-with = <&buck2_reg>;
888 regulator-coupled-max-spread = <300000>;
889
890 regulator-state-mem {
891 regulator-off-in-suspend;
892 };
893 };
894
895 buck4_reg: BUCK4 {
896 regulator-name = "vdd_g3d";
897 regulator-min-microvolt = <800000>;
898 regulator-max-microvolt = <1400000>;
899 regulator-boot-on;
900 regulator-always-on;
901
902 regulator-state-mem {
903 regulator-off-in-suspend;
904 };
905 };
906
907 buck5_reg: BUCK5 {
908 regulator-name = "vdd_mem";
909 regulator-min-microvolt = <800000>;
910 regulator-max-microvolt = <1400000>;
911 regulator-always-on;
912 regulator-boot-on;
913 };
914
915 buck6_reg: BUCK6 {
916 regulator-name = "vdd_kfc";
917 regulator-min-microvolt = <800000>;
918 regulator-max-microvolt = <1500000>;
919 regulator-always-on;
920 regulator-boot-on;
921
922 regulator-state-mem {
923 regulator-off-in-suspend;
924 };
925 };
926
927 buck7_reg: BUCK7 {
928 regulator-name = "vdd_1.35v_ldo";
929 regulator-min-microvolt = <1200000>;
930 regulator-max-microvolt = <1500000>;
931 regulator-always-on;
932 regulator-boot-on;
933 };
934
935 buck8_reg: BUCK8 {
936 regulator-name = "vdd_2.0v_ldo";
937 regulator-min-microvolt = <1800000>;
938 regulator-max-microvolt = <2100000>;
939 regulator-always-on;
940 regulator-boot-on;
941 };
942
943 buck9_reg: BUCK9 {
944 regulator-name = "vdd_2.8v_ldo";
945 regulator-min-microvolt = <3000000>;
946 regulator-max-microvolt = <3750000>;
947 regulator-always-on;
948 regulator-boot-on;
949
950 regulator-state-mem {
951 regulator-off-in-suspend;
952 };
953 };
954
955 buck10_reg: BUCK10 {
956 regulator-name = "vdd_vmem";
957 regulator-min-microvolt = <2850000>;
958 regulator-max-microvolt = <2850000>;
959
960 regulator-state-mem {
961 regulator-off-in-suspend;
962 };
963 };
964 };
965 };
966 };
967
968 &mmc_2 {
969 status = "okay";
970 card-detect-delay = <200>;
971 samsung,dw-mshc-ciu-div = <3>;
972 samsung,dw-mshc-sdr-timing = <0 4>;
973 samsung,dw-mshc-ddr-timing = <0 2>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
976 bus-width = <4>;
977 cap-sd-highspeed;
978 max-frequency = <200000000>;
979 vmmc-supply = <&ldo19_reg>;
980 vqmmc-supply = <&ldo13_reg>;
981 sd-uhs-sdr50;
982 sd-uhs-sdr104;
983 sd-uhs-ddr50;
984 };
985
986 &nocp_mem0_0 {
987 status = "okay";
988 };
989
990 &nocp_mem0_1 {
991 status = "okay";
992 };
993
994 &nocp_mem1_0 {
995 status = "okay";
996 };
997
998 &nocp_mem1_1 {
999 status = "okay";
1000 };
1001
1002 &pinctrl_0 {
1003 s2mps11_irq: s2mps11-irq-pins {
1004 samsung,pins = "gpx0-4";
1005 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
1006 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
1007 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
1008 };
1009 };
1010
1011 &ppmu_dmc0_0 {
1012 status = "okay";
1013 };
1014
1015 &ppmu_dmc0_1 {
1016 status = "okay";
1017 };
1018
1019 &ppmu_dmc1_0 {
1020 status = "okay";
1021 };
1022
1023 &ppmu_dmc1_1 {
1024 status = "okay";
1025 };
1026
1027 &tmu_cpu0 {
1028 vtmu-supply = <&ldo7_reg>;
1029 };
1030
1031 &tmu_cpu1 {
1032 vtmu-supply = <&ldo7_reg>;
1033 };
1034
1035 &tmu_cpu2 {
1036 vtmu-supply = <&ldo7_reg>;
1037 };
1038
1039 &tmu_cpu3 {
1040 vtmu-supply = <&ldo7_reg>;
1041 };
1042
1043 &tmu_gpu {
1044 vtmu-supply = <&ldo7_reg>;
1045 };
1046
1047 &gpu {
1048 mali-supply = <&buck4_reg>;
1049 status = "okay";
1050 };
1051
1052 &rtc {
1053 status = "okay";
1054 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
1055 clock-names = "rtc", "rtc_src";
1056 };
1057
1058 &usbdrd_dwc3_0 {
1059 dr_mode = "host";
1060 };
1061
1062 /* usbdrd_dwc3_1 mode customized in each board */
1063
1064 &usbdrd3_0 {
1065 vdd33-supply = <&ldo9_reg>;
1066 vdd10-supply = <&ldo11_reg>;
1067 };
1068
1069 &usbdrd3_1 {
1070 vdd33-supply = <&ldo9_reg>;
1071 vdd10-supply = <&ldo11_reg>;
1072 };
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