1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2021 STMicroelectronics 4 * Author: Alain Volmat <avolmat@me.com> 5 */ 6 /dts-v1/; 7 #include "stih418.dtsi" 8 #include <dt-bindings/gpio/gpio.h> 9 / { 10 model = "STiH418 B2264"; 11 compatible = "st,stih418-b2264", "st,stih418"; 12 13 chosen { 14 stdout-path = &sbc_serial0; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x40000000 0xc0000000>; 20 }; 21 22 cpus { 23 cpu@0 { 24 operating-points-v2 = <&cpu_opp_table>; 25 /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 26 cpu-release-addr = <0x94100b8>; 27 }; 28 cpu@1 { 29 operating-points-v2 = <&cpu_opp_table>; 30 /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 31 cpu-release-addr = <0x94100b8>; 32 }; 33 cpu@2 { 34 operating-points-v2 = <&cpu_opp_table>; 35 /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 36 cpu-release-addr = <0x94100b8>; 37 }; 38 cpu@3 { 39 operating-points-v2 = <&cpu_opp_table>; 40 /* u-boot puts hpen in SBC dmem at 0xb8 offset */ 41 cpu-release-addr = <0x94100b8>; 42 }; 43 }; 44 45 cpu_opp_table: opp-table { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp00 { 50 opp-hz = /bits/ 64 <300000000>; 51 opp-microvolt = <784000>; 52 }; 53 opp01 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <784000>; 56 }; 57 opp02 { 58 opp-hz = /bits/ 64 <800000000>; 59 opp-microvolt = <784000>; 60 }; 61 opp03 { 62 opp-hz = /bits/ 64 <1200000000>; 63 opp-microvolt = <784000>; 64 }; 65 opp04 { 66 opp-hz = /bits/ 64 <1500000000>; 67 opp-microvolt = <784000>; 68 }; 69 }; 70 71 aliases { 72 serial0 = &sbc_serial0; 73 ethernet0 = ðernet0; 74 }; 75 76 leds { 77 compatible = "gpio-leds"; 78 led-green { 79 gpios = <&pio1 3 GPIO_ACTIVE_LOW>; 80 default-state = "off"; 81 }; 82 }; 83 84 soc { 85 pin-controller-sbc@961f080 { 86 gmac1 { 87 rgmii1-0 { 88 st,pins { 89 rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>; 90 rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>; 91 rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>; 92 rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>; 93 rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>; 94 }; 95 }; 96 }; 97 }; 98 99 }; 100 }; 101 102 &ehci0 { 103 status = "okay"; 104 }; 105 106 ðernet0 { 107 phy-mode = "rgmii"; 108 pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; 109 st,tx-retime-src = "clkgen"; 110 111 snps,reset-gpio = <&pio0 7 0>; 112 snps,reset-active-low; 113 snps,reset-delays-us = <0 10000 1000000>; 114 115 status = "okay"; 116 }; 117 118 &miphy28lp_phy { 119 phy_port0: port@9b22000 { 120 st,sata-gen = <2>; /* SATA GEN3 */ 121 st,osc-rdy; 122 }; 123 }; 124 125 &mmc0 { 126 status = "okay"; 127 }; 128 129 &ohci1 { 130 status = "okay"; 131 }; 132 133 &pwm1 { 134 status = "okay"; 135 }; 136 137 &sata0 { 138 status = "okay"; 139 }; 140 141 &sbc_serial0 { 142 status = "okay"; 143 }; 144 145 &spifsm { 146 status = "okay"; 147 }; 148 149 &st_dwc3 { 150 status = "okay"; 151 };
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