1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */
6
7 /dts-v1/;
8
9 #include "stm32mp157c-ed1.dts"
10 #include "stm32mp15-scmi.dtsi"
11
12 / {
13 model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
14 compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157";
15
16 reserved-memory {
17 optee@fe000000 {
18 reg = <0xfe000000 0x2000000>;
19 no-map;
20 };
21 };
22 };
23
24 &cpu0 {
25 clocks = <&scmi_clk CK_SCMI_MPU>;
26 };
27
28 &cpu1 {
29 clocks = <&scmi_clk CK_SCMI_MPU>;
30 };
31
32 &cryp1 {
33 clocks = <&scmi_clk CK_SCMI_CRYP1>;
34 resets = <&scmi_reset RST_SCMI_CRYP1>;
35 };
36
37 &dsi {
38 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
39 };
40
41 &gpioz {
42 clocks = <&scmi_clk CK_SCMI_GPIOZ>;
43 };
44
45 &hash1 {
46 clocks = <&scmi_clk CK_SCMI_HASH1>;
47 resets = <&scmi_reset RST_SCMI_HASH1>;
48 };
49
50 &i2c4 {
51 clocks = <&scmi_clk CK_SCMI_I2C4>;
52 resets = <&scmi_reset RST_SCMI_I2C4>;
53 };
54
55 &iwdg2 {
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
57 };
58
59 &mdma1 {
60 resets = <&scmi_reset RST_SCMI_MDMA>;
61 };
62
63 &m4_rproc {
64 /delete-property/ st,syscfg-holdboot;
65 resets = <&scmi_reset RST_SCMI_MCU>,
66 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
67 reset-names = "mcu_rst", "hold_boot";
68 };
69
70 &optee {
71 interrupt-parent = <&intc>;
72 interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
73 };
74
75 &rcc {
76 compatible = "st,stm32mp1-rcc-secure", "syscon";
77 clock-names = "hse", "hsi", "csi", "lse", "lsi";
78 clocks = <&scmi_clk CK_SCMI_HSE>,
79 <&scmi_clk CK_SCMI_HSI>,
80 <&scmi_clk CK_SCMI_CSI>,
81 <&scmi_clk CK_SCMI_LSE>,
82 <&scmi_clk CK_SCMI_LSI>;
83 };
84
85 &rng1 {
86 clocks = <&scmi_clk CK_SCMI_RNG1>;
87 resets = <&scmi_reset RST_SCMI_RNG1>;
88 };
89
90 &rtc {
91 clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
92 };
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