1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * support for the bosch am335x based shc c3 board
4 *
5 * Copyright, C) 2015 Heiko Schocher <hs@denx.de>
6 *
7 */
8 /dts-v1/;
9
10 #include "am33xx.dtsi"
11 #include <dt-bindings/input/input.h>
12
13 / {
14 model = "Bosch SHC";
15 compatible = "ti,am335x-shc", "ti,am335x-bone", "ti,am33xx";
16
17 aliases {
18 mmcblk0 = &mmc1;
19 mmcblk1 = &mmc2;
20 };
21
22 cpus {
23 cpu@0 {
24 /*
25 * To consider voltage drop between PMIC and SoC,
26 * tolerance value is reduced to 2% from 4% and
27 * voltage value is increased as a precaution.
28 */
29 operating-points = <
30 /* kHz uV */
31 594000 1225000
32 294000 1125000
33 >;
34 voltage-tolerance = <2>; /* 2 percentage */
35 cpu0-supply = <&dcdc2_reg>;
36 };
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 back-button {
43 label = "Back Button";
44 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
45 linux,code = <KEY_BACK>;
46 debounce-interval = <1000>;
47 wakeup-source;
48 };
49
50 front-button {
51 label = "Front Button";
52 gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_FRONT>;
54 debounce-interval = <1000>;
55 wakeup-source;
56 };
57 };
58
59 leds {
60 pinctrl-names = "default";
61 pinctrl-0 = <&user_leds_s0>;
62
63 compatible = "gpio-leds";
64
65 led1 {
66 label = "shc:power:red";
67 gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
69 };
70
71 led2 {
72 label = "shc:power:bl";
73 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
74 linux,default-trigger = "timer";
75 default-state = "on";
76 };
77
78 led3 {
79 label = "shc:lan:red";
80 gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
81 default-state = "off";
82 };
83
84 led4 {
85 label = "shc:lan:bl";
86 gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
87 default-state = "off";
88 };
89
90 led5 {
91 label = "shc:cloud:red";
92 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
93 default-state = "off";
94 };
95
96 led6 {
97 label = "shc:cloud:bl";
98 gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
99 default-state = "off";
100 };
101 };
102
103 memory@80000000 {
104 device_type = "memory";
105 reg = <0x80000000 0x20000000>; /* 512 MB */
106 };
107
108 vmmcsd_fixed: fixedregulator0 {
109 compatible = "regulator-fixed";
110 regulator-name = "vmmcsd_fixed";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 };
114 };
115
116 &aes {
117 status = "okay";
118 };
119
120 &epwmss1 {
121 status = "okay";
122
123 ehrpwm1: pwm@200 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&ehrpwm1_pins>;
126 status = "okay";
127 };
128 };
129
130 &gpio1 {
131 hmtc-rst-hog {
132 gpio-hog;
133 gpios = <24 GPIO_ACTIVE_LOW>;
134 output-high;
135 line-name = "homematic_reset";
136 };
137
138 hmtc-prog-hog {
139 gpio-hog;
140 gpios = <27 GPIO_ACTIVE_LOW>;
141 output-high;
142 line-name = "homematic_program";
143 };
144 };
145
146 &gpio3 {
147 zgb-rst-hog {
148 gpio-hog;
149 gpios = <18 GPIO_ACTIVE_LOW>;
150 output-low;
151 line-name = "zigbee_reset";
152 };
153
154 zgb-boot-hog {
155 gpio-hog;
156 gpios = <19 GPIO_ACTIVE_HIGH>;
157 output-high;
158 line-name = "zigbee_boot";
159 };
160 };
161
162 &i2c0 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c0_pins>;
165 status = "okay";
166 clock-frequency = <400000>;
167
168 tps: tps@24 {
169 reg = <0x24>;
170 };
171
172 at24@50 {
173 compatible = "atmel,24c32";
174 pagesize = <32>;
175 reg = <0x50>;
176 };
177
178 pcf8563@51 {
179 compatible = "nxp,pcf8563";
180 reg = <0x51>;
181 };
182 };
183
184 &mac_sw {
185 pinctrl-names = "default", "sleep";
186 pinctrl-0 = <&cpsw_default>;
187 pinctrl-1 = <&cpsw_sleep>;
188 status = "okay";
189 };
190
191 &cpsw_port1 {
192 phy-mode = "mii";
193 phy-handle = <ðernetphy0>;
194 ti,dual-emac-pvid = <1>;
195 };
196
197 &cpsw_port2 {
198 status = "disabled";
199 };
200
201 &davinci_mdio_sw {
202 pinctrl-names = "default", "sleep";
203 pinctrl-0 = <&davinci_mdio_default>;
204 pinctrl-1 = <&davinci_mdio_sleep>;
205
206 ethernetphy0: ethernet-phy@0 {
207 reg = <0>;
208 smsc,disable-energy-detect;
209 };
210 };
211
212 &mmc1 {
213 pinctrl-names = "default";
214 pinctrl-0 = <&mmc1_pins>;
215 bus-width = <0x4>;
216 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
217 cd-inverted;
218 max-frequency = <26000000>;
219 vmmc-supply = <&vmmcsd_fixed>;
220 status = "okay";
221 };
222
223 &mmc2 {
224 pinctrl-names = "default";
225 pinctrl-0 = <&emmc_pins>;
226 bus-width = <8>;
227 max-frequency = <26000000>;
228 sd-uhs-sdr25;
229 vmmc-supply = <&vmmcsd_fixed>;
230 status = "okay";
231 };
232
233 &mmc3 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&mmc3_pins>;
236 bus-width = <4>;
237 cap-power-off-card;
238 max-frequency = <26000000>;
239 sd-uhs-sdr25;
240 vmmc-supply = <&vmmcsd_fixed>;
241 status = "okay";
242 };
243
244 &rtc {
245 ti,no-init;
246 };
247
248 &sham {
249 status = "okay";
250 };
251
252 &tps {
253 compatible = "ti,tps65217";
254 ti,pmic-shutdown-controller;
255
256 regulators {
257 #address-cells = <1>;
258 #size-cells = <0>;
259
260 dcdc1_reg: regulator@0 {
261 reg = <0>;
262 regulator-name = "vdds_dpr";
263 regulator-compatible = "dcdc1";
264 regulator-min-microvolt = <1300000>;
265 regulator-max-microvolt = <1450000>;
266 regulator-boot-on;
267 regulator-always-on;
268 };
269
270 dcdc2_reg: regulator@1 {
271 reg = <1>;
272 /*
273 * VDD_MPU voltage limits 0.95V - 1.26V with
274 * +/-4% tolerance
275 */
276 regulator-compatible = "dcdc2";
277 regulator-name = "vdd_mpu";
278 regulator-min-microvolt = <925000>;
279 regulator-max-microvolt = <1375000>;
280 regulator-boot-on;
281 regulator-always-on;
282 regulator-ramp-delay = <70000>;
283 };
284
285 dcdc3_reg: regulator@2 {
286 reg = <2>;
287 /*
288 * VDD_CORE voltage limits 0.95V - 1.1V with
289 * +/-4% tolerance
290 */
291 regulator-name = "vdd_core";
292 regulator-compatible = "dcdc3";
293 regulator-min-microvolt = <925000>;
294 regulator-max-microvolt = <1125000>;
295 regulator-boot-on;
296 regulator-always-on;
297 };
298
299 ldo1_reg: regulator@3 {
300 reg = <3>;
301 regulator-name = "vio,vrtc,vdds";
302 regulator-compatible = "ldo1";
303 regulator-min-microvolt = <1000000>;
304 regulator-max-microvolt = <1800000>;
305 regulator-always-on;
306 };
307
308 ldo2_reg: regulator@4 {
309 reg = <4>;
310 regulator-name = "vdd_3v3aux";
311 regulator-compatible = "ldo2";
312 regulator-min-microvolt = <900000>;
313 regulator-max-microvolt = <3300000>;
314 regulator-always-on;
315 };
316
317 ldo3_reg: regulator@5 {
318 reg = <5>;
319 regulator-name = "vdd_1v8";
320 regulator-compatible = "ldo3";
321 regulator-min-microvolt = <900000>;
322 regulator-max-microvolt = <1800000>;
323 regulator-always-on;
324 };
325
326 ldo4_reg: regulator@6 {
327 reg = <6>;
328 regulator-name = "vdd_3v3a";
329 regulator-compatible = "ldo4";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <3300000>;
332 regulator-always-on;
333 };
334 };
335 };
336
337 &uart0 {
338 pinctrl-names = "default";
339 pinctrl-0 = <&uart0_pins>;
340 status = "okay";
341 };
342
343 &uart1 {
344 pinctrl-names = "default";
345 pinctrl-0 = <&uart1_pins>;
346 status = "okay";
347 };
348
349 &uart2 {
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart2_pins>;
352 status = "okay";
353 };
354
355 &uart4 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&uart4_pins>;
358 status = "okay";
359 };
360
361 &usb1 {
362 dr_mode = "host";
363 };
364
365 &am33xx_pinmux {
366 pinctrl-names = "default";
367 pinctrl-0 = <&clkout2_pin>;
368
369 clkout2_pin: clkout2-pins {
370 pinctrl-single,pins = <
371 /* xdma_event_intr1.clkout2 */
372 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)
373 >;
374 };
375
376 cpsw_default: cpsw-default-pins {
377 pinctrl-single,pins = <
378 /* Slave 1 */
379 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)
380 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
381 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)
382 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
383 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
384 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
385 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
386 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
387 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
388 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)
389 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)
390 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)
391 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)
392 >;
393 };
394
395 cpsw_sleep: cpsw-sleep-pins {
396 pinctrl-single,pins = <
397 /* Slave 1 reset value */
398 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
399 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
400 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
401 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
402 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
403 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
404 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
405 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
406 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
407 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
408 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
409 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
410 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
411 >;
412 };
413
414 davinci_mdio_default: davinci-mdio-default-pins {
415 pinctrl-single,pins = <
416 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
417 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
418 >;
419 };
420
421 davinci_mdio_sleep: davinci-mdio-sleep-pins {
422 pinctrl-single,pins = <
423 /* MDIO reset value */
424 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
425 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
426 >;
427 };
428
429 ehrpwm1_pins: ehrpwm1-pins {
430 pinctrl-single,pins = <
431 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */
432 >;
433 };
434
435 emmc_pins: emmc-pins {
436 pinctrl-single,pins = <
437 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)
438 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)
439 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)
440 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)
441 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)
442 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)
443 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)
444 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)
445 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)
446 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)
447 >;
448 };
449
450 i2c0_pins: i2c0-pins {
451 pinctrl-single,pins = <
452 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
453 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
454 >;
455 };
456
457 mmc1_pins: mmc1-pins {
458 pinctrl-single,pins = <
459 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)
460 >;
461 };
462
463 mmc3_pins: mmc3-pins {
464 pinctrl-single,pins = <
465 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)
466 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)
467 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)
468 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)
469 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)
470 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)
471 >;
472 };
473
474 uart0_pins: uart0-pins {
475 pinctrl-single,pins = <
476 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
477 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)
478 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)
479 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
480 >;
481 };
482
483 uart1_pins: uart1-pins {
484 pinctrl-single,pins = <
485 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
486 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)
487 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
488 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
489 >;
490 };
491
492 uart2_pins: uart2-pins {
493 pinctrl-single,pins = <
494 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)
495 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)
496 >;
497 };
498
499 uart4_pins: uart4-pins {
500 pinctrl-single,pins = <
501 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)
502 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)
503 >;
504 };
505
506 user_leds_s0: user-leds-s0-pins {
507 pinctrl-single,pins = <
508 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)
509 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)
510 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)
511 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)
512 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)
513 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)
514 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)
515 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
516 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)
517 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)
518 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)
519 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)
520 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)
521 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)
522 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)
523 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)
524 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)
525 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)
526 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)
527 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)
528 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)
529 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)
530 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)
531 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)
532 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)
533 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)
534 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)
535 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)
536 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)
537 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)
538 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)
539 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)
540 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)
541 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)
542 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)
543 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)
544 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)
545 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)
546 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)
547 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)
548 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)
549 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
550 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)
551 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)
552 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)
553 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
554 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)
555 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
556 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)
557 >;
558 };
559 };
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