1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2011 - 2014 Xilinx
4 * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
5 */
6 /dts-v1/;
7 /include/ "zynq-7000.dtsi"
8
9 / {
10 model = "Avnet MicroZed board";
11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";
12
13 aliases {
14 ethernet0 = &gem0;
15 serial0 = &uart1;
16 };
17
18 memory@0 {
19 device_type = "memory";
20 reg = <0x0 0x40000000>;
21 };
22
23 chosen {
24 bootargs = "earlycon";
25 stdout-path = "serial0:115200n8";
26 };
27
28 usb_phy0: phy0 {
29 compatible = "usb-nop-xceiv";
30 #phy-cells = <0>;
31 };
32 };
33
34 &clkc {
35 ps-clk-frequency = <33333333>;
36 };
37
38 &gem0 {
39 status = "okay";
40 phy-mode = "rgmii-id";
41 phy-handle = <ðernet_phy>;
42
43 ethernet_phy: ethernet-phy@0 {
44 reg = <0>;
45 };
46 };
47
48 &sdhci0 {
49 status = "okay";
50 };
51
52 &uart1 {
53 status = "okay";
54 };
55
56 &usb0 {
57 status = "okay";
58 dr_mode = "host";
59 usb-phy = <&usb_phy0>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_usb0_default>;
62 };
63
64 &pinctrl0 {
65 pinctrl_usb0_default: usb0-default {
66 mux {
67 groups = "usb0_0_grp";
68 function = "usb0";
69 };
70
71 conf {
72 groups = "usb0_0_grp";
73 slew-rate = <0>;
74 io-standard = <1>;
75 };
76
77 conf-rx {
78 pins = "MIO29", "MIO31", "MIO36";
79 bias-high-impedance;
80 };
81
82 conf-tx {
83 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
84 "MIO35", "MIO37", "MIO38", "MIO39";
85 bias-disable;
86 };
87 };
88 };
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