1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ARM_HW_BREAKPOINT_H
3 #define _ARM_HW_BREAKPOINT_H
4
5 #ifdef __KERNEL__
6
7 struct task_struct;
8
9 #ifdef CONFIG_HAVE_HW_BREAKPOINT
10
11 struct arch_hw_breakpoint_ctrl {
12 u32 __reserved : 9,
13 mismatch : 1,
14 : 9,
15 len : 8,
16 type : 2,
17 privilege : 2,
18 enabled : 1;
19 };
20
21 struct arch_hw_breakpoint {
22 u32 address;
23 u32 trigger;
24 struct arch_hw_breakpoint_ctrl step_ctrl;
25 struct arch_hw_breakpoint_ctrl ctrl;
26 };
27
28 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
29 {
30 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
31 (ctrl.privilege << 1) | ctrl.enabled;
32 }
33
34 static inline void decode_ctrl_reg(u32 reg,
35 struct arch_hw_breakpoint_ctrl *ctrl)
36 {
37 ctrl->enabled = reg & 0x1;
38 reg >>= 1;
39 ctrl->privilege = reg & 0x3;
40 reg >>= 2;
41 ctrl->type = reg & 0x3;
42 reg >>= 2;
43 ctrl->len = reg & 0xff;
44 reg >>= 17;
45 ctrl->mismatch = reg & 0x1;
46 }
47
48 /* Debug architecture numbers. */
49 #define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
50 #define ARM_DEBUG_ARCH_V6 1
51 #define ARM_DEBUG_ARCH_V6_1 2
52 #define ARM_DEBUG_ARCH_V7_ECP14 3
53 #define ARM_DEBUG_ARCH_V7_MM 4
54 #define ARM_DEBUG_ARCH_V7_1 5
55 #define ARM_DEBUG_ARCH_V8 6
56 #define ARM_DEBUG_ARCH_V8_1 7
57 #define ARM_DEBUG_ARCH_V8_2 8
58 #define ARM_DEBUG_ARCH_V8_4 9
59
60 /* Breakpoint */
61 #define ARM_BREAKPOINT_EXECUTE 0
62
63 /* Watchpoints */
64 #define ARM_BREAKPOINT_LOAD 1
65 #define ARM_BREAKPOINT_STORE 2
66 #define ARM_FSR_ACCESS_MASK (1 << 11)
67
68 /* Privilege Levels */
69 #define ARM_BREAKPOINT_PRIV 1
70 #define ARM_BREAKPOINT_USER 2
71
72 /* Lengths */
73 #define ARM_BREAKPOINT_LEN_1 0x1
74 #define ARM_BREAKPOINT_LEN_2 0x3
75 #define ARM_BREAKPOINT_LEN_4 0xf
76 #define ARM_BREAKPOINT_LEN_8 0xff
77
78 /* Limits */
79 #define ARM_MAX_BRP 16
80 #define ARM_MAX_WRP 16
81 #define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
82
83 /* DSCR method of entry bits. */
84 #define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
85 #define ARM_ENTRY_BREAKPOINT 0x1
86 #define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
87 #define ARM_ENTRY_CFI_BREAKPOINT 0x3
88 #define ARM_ENTRY_SYNC_WATCHPOINT 0xa
89
90 /* DSCR monitor/halting bits. */
91 #define ARM_DSCR_HDBGEN (1 << 14)
92 #define ARM_DSCR_MDBGEN (1 << 15)
93
94 /* OSLSR os lock model bits */
95 #define ARM_OSLSR_OSLM0 (1 << 0)
96
97 /* opcode2 numbers for the co-processor instructions. */
98 #define ARM_OP2_BVR 4
99 #define ARM_OP2_BCR 5
100 #define ARM_OP2_WVR 6
101 #define ARM_OP2_WCR 7
102
103 /* Base register numbers for the debug registers. */
104 #define ARM_BASE_BVR 64
105 #define ARM_BASE_BCR 80
106 #define ARM_BASE_WVR 96
107 #define ARM_BASE_WCR 112
108
109 /* Accessor macros for the debug registers. */
110 #define ARM_DBG_READ(N, M, OP2, VAL) do {\
111 asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\
112 } while (0)
113
114 #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\
115 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
116 } while (0)
117
118 struct perf_event_attr;
119 struct notifier_block;
120 struct perf_event;
121 struct pmu;
122
123 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
124 int *gen_len, int *gen_type);
125 extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
126 extern int hw_breakpoint_arch_parse(struct perf_event *bp,
127 const struct perf_event_attr *attr,
128 struct arch_hw_breakpoint *hw);
129 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
130 unsigned long val, void *data);
131
132 extern u8 arch_get_debug_arch(void);
133 extern u8 arch_get_max_wp_len(void);
134 extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
135
136 int arch_install_hw_breakpoint(struct perf_event *bp);
137 void arch_uninstall_hw_breakpoint(struct perf_event *bp);
138 void hw_breakpoint_pmu_read(struct perf_event *bp);
139 int hw_breakpoint_slots(int type);
140
141 #else
142 static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
143
144 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
145 #endif /* __KERNEL__ */
146 #endif /* _ARM_HW_BREAKPOINT_H */
147
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