1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * Modifications:
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
9 * constant addresses and variable addresses.
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
16 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
17 */
18 #ifndef __ASM_ARM_IO_H
19 #define __ASM_ARM_IO_H
20
21 #ifdef __KERNEL__
22
23 #include <linux/string.h>
24 #include <linux/types.h>
25 #include <asm/byteorder.h>
26 #include <asm/page.h>
27 #include <asm-generic/pci_iomap.h>
28
29 /*
30 * ISA I/O bus memory addresses are 1:1 with the physical address.
31 */
32 #define isa_virt_to_bus virt_to_phys
33 #define isa_bus_to_virt phys_to_virt
34
35 /*
36 * Atomic MMIO-wide IO modify
37 */
38 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
39 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
40
41 /*
42 * Generic IO read/write. These perform native-endian accesses. Note
43 * that some architectures will want to re-define __raw_{read,write}w.
44 */
45 void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
46 void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
47 void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
48
49 void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
50 void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
51 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
52
53 #if __LINUX_ARM_ARCH__ < 6
54 /*
55 * Half-word accesses are problematic with RiscPC due to limitations of
56 * the bus. Rather than special-case the machine, just let the compiler
57 * generate the access for CPUs prior to ARMv6.
58 */
59 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
60 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
61 #else
62 /*
63 * When running under a hypervisor, we want to avoid I/O accesses with
64 * writeback addressing modes as these incur a significant performance
65 * overhead (the address generation must be emulated in software).
66 */
67 #define __raw_writew __raw_writew
68 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
69 {
70 asm volatile("strh %1, %0"
71 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
72 }
73
74 #define __raw_readw __raw_readw
75 static inline u16 __raw_readw(const volatile void __iomem *addr)
76 {
77 u16 val;
78 asm volatile("ldrh %0, %1"
79 : "=r" (val)
80 : "Q" (*(volatile u16 __force *)addr));
81 return val;
82 }
83 #endif
84
85 #define __raw_writeb __raw_writeb
86 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
87 {
88 asm volatile("strb %1, %0"
89 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
90 }
91
92 #define __raw_writel __raw_writel
93 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
94 {
95 asm volatile("str %1, %0"
96 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
97 }
98
99 #define __raw_readb __raw_readb
100 static inline u8 __raw_readb(const volatile void __iomem *addr)
101 {
102 u8 val;
103 asm volatile("ldrb %0, %1"
104 : "=r" (val)
105 : "Qo" (*(volatile u8 __force *)addr));
106 return val;
107 }
108
109 #define __raw_readl __raw_readl
110 static inline u32 __raw_readl(const volatile void __iomem *addr)
111 {
112 u32 val;
113 asm volatile("ldr %0, %1"
114 : "=r" (val)
115 : "Qo" (*(volatile u32 __force *)addr));
116 return val;
117 }
118
119 /*
120 * Architecture ioremap implementation.
121 */
122 #define MT_DEVICE 0
123 #define MT_DEVICE_NONSHARED 1
124 #define MT_DEVICE_CACHED 2
125 #define MT_DEVICE_WC 3
126 /*
127 * types 4 onwards can be found in asm/mach/map.h and are undefined
128 * for ioremap
129 */
130
131 /*
132 * __arm_ioremap takes CPU physical address.
133 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
134 * The _caller variety takes a __builtin_return_address(0) value for
135 * /proc/vmalloc to use - and should only be used in non-inline functions.
136 */
137 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
138 void *);
139 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
140 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
141 void __arm_iomem_set_ro(void __iomem *ptr, size_t size);
142
143 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
144 unsigned int, void *);
145
146 /*
147 * Bad read/write accesses...
148 */
149 extern void __readwrite_bug(const char *fn);
150
151 /*
152 * A typesafe __io() helper
153 */
154 static inline void __iomem *__typesafe_io(unsigned long addr)
155 {
156 return (void __iomem *)addr;
157 }
158
159 #define IOMEM(x) ((void __force __iomem *)(x))
160
161 /* IO barriers */
162 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
163 #include <asm/barrier.h>
164 #define __iormb() rmb()
165 #define __iowmb() wmb()
166 #else
167 #define __iormb() do { } while (0)
168 #define __iowmb() do { } while (0)
169 #endif
170
171 /* PCI fixed i/o mapping */
172 #define PCI_IO_VIRT_BASE 0xfee00000
173 #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
174
175 #if defined(CONFIG_PCI) || IS_ENABLED(CONFIG_PCMCIA)
176 void pci_ioremap_set_mem_type(int mem_type);
177 #else
178 static inline void pci_ioremap_set_mem_type(int mem_type) {}
179 #endif
180
181 struct resource;
182
183 #define pci_remap_iospace pci_remap_iospace
184 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
185
186 /*
187 * PCI configuration space mapping function.
188 *
189 * The PCI specification does not allow configuration write
190 * transactions to be posted. Add an arch specific
191 * pci_remap_cfgspace() definition that is implemented
192 * through strongly ordered memory mappings.
193 */
194 #define pci_remap_cfgspace pci_remap_cfgspace
195 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
196 /*
197 * Now, pick up the machine-defined IO definitions
198 */
199 #ifdef CONFIG_NEED_MACH_IO_H
200 #include <mach/io.h>
201 #else
202 #if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
203 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
204 #else
205 #define IO_SPACE_LIMIT ((resource_size_t)0)
206 #endif
207 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
208 #endif
209
210 /*
211 * IO port access primitives
212 * -------------------------
213 *
214 * The ARM doesn't have special IO access instructions; all IO is memory
215 * mapped. Note that these are defined to perform little endian accesses
216 * only. Their primary purpose is to access PCI and ISA peripherals.
217 *
218 * Note that for a big endian machine, this implies that the following
219 * big endian mode connectivity is in place, as described by numerous
220 * ARM documents:
221 *
222 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
223 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
224 *
225 * The machine specific io.h include defines __io to translate an "IO"
226 * address to a memory address.
227 *
228 * Note that we prevent GCC re-ordering or caching values in expressions
229 * by introducing sequence points into the in*() definitions. Note that
230 * __raw_* do not guarantee this behaviour.
231 *
232 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
233 */
234 #ifdef __io
235 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
236 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
237 cpu_to_le16(v),__io(p)); })
238 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
239 cpu_to_le32(v),__io(p)); })
240
241 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
242 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
243 __raw_readw(__io(p))); __iormb(); __v; })
244 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
245 __raw_readl(__io(p))); __iormb(); __v; })
246
247 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
248 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
249 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
250
251 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
252 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
253 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
254 #endif
255
256 /*
257 * String version of IO memory access ops:
258 */
259 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
260 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
261 extern void _memset_io(volatile void __iomem *, int, size_t);
262
263 /*
264 * Memory access primitives
265 * ------------------------
266 *
267 * These perform PCI memory accesses via an ioremap region. They don't
268 * take an address as such, but a cookie.
269 *
270 * Again, these are defined to perform little endian accesses. See the
271 * IO port primitives for more information.
272 */
273 #ifndef readl
274 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
275 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
276 __raw_readw(c)); __r; })
277 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
278 __raw_readl(c)); __r; })
279
280 #define writeb_relaxed(v,c) __raw_writeb(v,c)
281 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
282 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
283
284 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
285 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
286 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
287
288 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
289 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
290 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
291
292 #define readsb(p,d,l) __raw_readsb(p,d,l)
293 #define readsw(p,d,l) __raw_readsw(p,d,l)
294 #define readsl(p,d,l) __raw_readsl(p,d,l)
295
296 #define writesb(p,d,l) __raw_writesb(p,d,l)
297 #define writesw(p,d,l) __raw_writesw(p,d,l)
298 #define writesl(p,d,l) __raw_writesl(p,d,l)
299
300 #ifndef __ARMBE__
301 static inline void memset_io(volatile void __iomem *dst, unsigned c,
302 size_t count)
303 {
304 extern void mmioset(void *, unsigned int, size_t);
305 mmioset((void __force *)dst, c, count);
306 }
307 #define memset_io(dst,c,count) memset_io(dst,c,count)
308
309 static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
310 size_t count)
311 {
312 extern void mmiocpy(void *, const void *, size_t);
313 mmiocpy(to, (const void __force *)from, count);
314 }
315 #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
316
317 static inline void memcpy_toio(volatile void __iomem *to, const void *from,
318 size_t count)
319 {
320 extern void mmiocpy(void *, const void *, size_t);
321 mmiocpy((void __force *)to, from, count);
322 }
323 #define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
324
325 #else
326 #define memset_io(c,v,l) _memset_io(c,(v),(l))
327 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
328 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
329 #endif
330
331 #endif /* readl */
332
333 /*
334 * ioremap() and friends.
335 *
336 * ioremap() takes a resource address, and size. Due to the ARM memory
337 * types, it is important to use the correct ioremap() function as each
338 * mapping has specific properties.
339 *
340 * Function Memory type Cacheability Cache hint
341 * ioremap() Device n/a n/a
342 * ioremap_cache() Normal Writeback Read allocate
343 * ioremap_wc() Normal Non-cacheable n/a
344 * ioremap_wt() Normal Non-cacheable n/a
345 *
346 * All device mappings have the following properties:
347 * - no access speculation
348 * - no repetition (eg, on return from an exception)
349 * - number, order and size of accesses are maintained
350 * - unaligned accesses are "unpredictable"
351 * - writes may be delayed before they hit the endpoint device
352 *
353 * All normal memory mappings have the following properties:
354 * - reads can be repeated with no side effects
355 * - repeated reads return the last value written
356 * - reads can fetch additional locations without side effects
357 * - writes can be repeated (in certain cases) with no side effects
358 * - writes can be merged before accessing the target
359 * - unaligned accesses can be supported
360 * - ordering is not guaranteed without explicit dependencies or barrier
361 * instructions
362 * - writes may be delayed before they hit the endpoint memory
363 *
364 * The cache hint is only a performance hint: CPUs may alias these hints.
365 * Eg, a CPU not implementing read allocate but implementing write allocate
366 * will provide a write allocate mapping instead.
367 */
368 void __iomem *ioremap(resource_size_t res_cookie, size_t size);
369 #define ioremap ioremap
370
371 /*
372 * Do not use ioremap_cache for mapping memory. Use memremap instead.
373 */
374 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
375 #define ioremap_cache ioremap_cache
376
377 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
378 #define ioremap_wc ioremap_wc
379 #define ioremap_wt ioremap_wc
380
381 void iounmap(volatile void __iomem *io_addr);
382 #define iounmap iounmap
383
384 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
385 #define arch_memremap_wb arch_memremap_wb
386
387 /*
388 * io{read,write}{16,32}be() macros
389 */
390 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
391 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
392
393 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
394 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
395
396 #ifndef ioport_map
397 #define ioport_map ioport_map
398 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
399 #endif
400 #ifndef ioport_unmap
401 #define ioport_unmap ioport_unmap
402 extern void ioport_unmap(void __iomem *addr);
403 #endif
404
405 struct pci_dev;
406
407 #define pci_iounmap pci_iounmap
408 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
409
410 #include <asm-generic/io.h>
411
412 #ifdef CONFIG_MMU
413 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
414 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
415 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
416 extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
417 unsigned long flags);
418 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
419 #endif
420
421 /*
422 * Register ISA memory and port locations for glibc iopl/inb/outb
423 * emulation.
424 */
425 extern void register_isa_ports(unsigned int mmio, unsigned int io,
426 unsigned int io_shift);
427
428 #endif /* __KERNEL__ */
429 #endif /* __ASM_ARM_IO_H */
430
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