1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/debug/icedcc.S 4 * 5 * Copyright (C) 1994-1999 Russell King 6 */ 7 8 @@ debug using ARM EmbeddedICE DCC channel 9 10 .macro addruart, rp, rv, tmp 11 .endm 12 13 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) 14 15 .macro senduart, rd, rx 16 mcr p14, 0, \rd, c0, c5, 0 17 .endm 18 19 .macro busyuart, rd, rx 20 1001: 21 mrc p14, 0, \rx, c0, c1, 0 22 tst \rx, #0x20000000 23 beq 1001b 24 .endm 25 26 .macro waituartcts, rd, rx 27 .endm 28 29 .macro waituarttxrdy, rd, rx 30 mov \rd, #0x2000000 31 1001: 32 subs \rd, \rd, #1 33 bmi 1002f 34 mrc p14, 0, \rx, c0, c1, 0 35 tst \rx, #0x20000000 36 bne 1001b 37 1002: 38 .endm 39 40 #elif defined(CONFIG_CPU_XSCALE) 41 42 .macro senduart, rd, rx 43 mcr p14, 0, \rd, c8, c0, 0 44 .endm 45 46 .macro busyuart, rd, rx 47 1001: 48 mrc p14, 0, \rx, c14, c0, 0 49 tst \rx, #0x10000000 50 beq 1001b 51 .endm 52 53 .macro waituartcts, rd, rx 54 .endm 55 56 .macro waituarttxrdy, rd, rx 57 mov \rd, #0x10000000 58 1001: 59 subs \rd, \rd, #1 60 bmi 1002f 61 mrc p14, 0, \rx, c14, c0, 0 62 tst \rx, #0x10000000 63 bne 1001b 64 1002: 65 .endm 66 67 #else 68 69 .macro senduart, rd, rx 70 mcr p14, 0, \rd, c1, c0, 0 71 .endm 72 73 .macro busyuart, rd, rx 74 1001: 75 mrc p14, 0, \rx, c0, c0, 0 76 tst \rx, #2 77 beq 1001b 78 79 .endm 80 81 .macro waituartcts, rd, rx 82 .endm 83 84 .macro waituarttxrdy, rd, rx 85 mov \rd, #0x2000000 86 1001: 87 subs \rd, \rd, #1 88 bmi 1002f 89 mrc p14, 0, \rx, c0, c0, 0 90 tst \rx, #2 91 bne 1001b 92 1002: 93 .endm 94 95 #endif /* CONFIG_CPU_V6 */
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