1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Mbus-L to Mbus Bridge Registers */ 3 4 #ifndef __ASM_ARCH_BRIDGE_REGS_H 5 #define __ASM_ARCH_BRIDGE_REGS_H 6 7 #include "dove.h" 8 9 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) 10 11 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 12 #define CPU_CTRL_PCIE0_LINK 0x00000001 13 #define CPU_RESET 0x00000002 14 #define CPU_CTRL_PCIE1_LINK 0x00000008 15 16 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 17 #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) 18 #define SOFT_RESET_OUT_EN 0x00000004 19 20 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 21 #define SOFT_RESET 0x00000001 22 23 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) 24 #define BRIDGE_INT_TIMER1_CLR (~0x0004) 25 26 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 27 #define IRQ_CAUSE_LOW_OFF 0x0000 28 #define IRQ_MASK_LOW_OFF 0x0004 29 #define FIQ_MASK_LOW_OFF 0x0008 30 #define ENDPOINT_MASK_LOW_OFF 0x000c 31 #define IRQ_CAUSE_HIGH_OFF 0x0010 32 #define IRQ_MASK_HIGH_OFF 0x0014 33 #define FIQ_MASK_HIGH_OFF 0x0018 34 #define ENDPOINT_MASK_HIGH_OFF 0x001c 35 #define PCIE_INTERRUPT_MASK_OFF 0x0020 36 37 #define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) 38 #define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) 39 #define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) 40 #define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) 41 #define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) 42 #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 43 #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 44 45 #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) 46 47 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 48 #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) 49 50 #endif 51
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