1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __ASM_ARCH_PM_H 4 #define __ASM_ARCH_PM_H 5 6 #include <asm/errno.h> 7 #include "irqs.h" 8 9 #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) 10 #define CLOCK_GATING_BIT_USB0 0 11 #define CLOCK_GATING_BIT_USB1 1 12 #define CLOCK_GATING_BIT_GBE 2 13 #define CLOCK_GATING_BIT_SATA 3 14 #define CLOCK_GATING_BIT_PCIE0 4 15 #define CLOCK_GATING_BIT_PCIE1 5 16 #define CLOCK_GATING_BIT_SDIO0 8 17 #define CLOCK_GATING_BIT_SDIO1 9 18 #define CLOCK_GATING_BIT_NAND 10 19 #define CLOCK_GATING_BIT_CAMERA 11 20 #define CLOCK_GATING_BIT_I2S0 12 21 #define CLOCK_GATING_BIT_I2S1 13 22 #define CLOCK_GATING_BIT_CRYPTO 15 23 #define CLOCK_GATING_BIT_AC97 21 24 #define CLOCK_GATING_BIT_PDMA 22 25 #define CLOCK_GATING_BIT_XOR0 23 26 #define CLOCK_GATING_BIT_XOR1 24 27 #define CLOCK_GATING_BIT_GIGA_PHY 30 28 #define CLOCK_GATING_USB0_MASK (1 << CLOCK_GATING_BIT_USB0) 29 #define CLOCK_GATING_USB1_MASK (1 << CLOCK_GATING_BIT_USB1) 30 #define CLOCK_GATING_GBE_MASK (1 << CLOCK_GATING_BIT_GBE) 31 #define CLOCK_GATING_SATA_MASK (1 << CLOCK_GATING_BIT_SATA) 32 #define CLOCK_GATING_PCIE0_MASK (1 << CLOCK_GATING_BIT_PCIE0) 33 #define CLOCK_GATING_PCIE1_MASK (1 << CLOCK_GATING_BIT_PCIE1) 34 #define CLOCK_GATING_SDIO0_MASK (1 << CLOCK_GATING_BIT_SDIO0) 35 #define CLOCK_GATING_SDIO1_MASK (1 << CLOCK_GATING_BIT_SDIO1) 36 #define CLOCK_GATING_NAND_MASK (1 << CLOCK_GATING_BIT_NAND) 37 #define CLOCK_GATING_CAMERA_MASK (1 << CLOCK_GATING_BIT_CAMERA) 38 #define CLOCK_GATING_I2S0_MASK (1 << CLOCK_GATING_BIT_I2S0) 39 #define CLOCK_GATING_I2S1_MASK (1 << CLOCK_GATING_BIT_I2S1) 40 #define CLOCK_GATING_CRYPTO_MASK (1 << CLOCK_GATING_BIT_CRYPTO) 41 #define CLOCK_GATING_AC97_MASK (1 << CLOCK_GATING_BIT_AC97) 42 #define CLOCK_GATING_PDMA_MASK (1 << CLOCK_GATING_BIT_PDMA) 43 #define CLOCK_GATING_XOR0_MASK (1 << CLOCK_GATING_BIT_XOR0) 44 #define CLOCK_GATING_XOR1_MASK (1 << CLOCK_GATING_BIT_XOR1) 45 #define CLOCK_GATING_GIGA_PHY_MASK (1 << CLOCK_GATING_BIT_GIGA_PHY) 46 47 #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) 48 49 #define PMU_SW_RST_VIDEO_MASK BIT(16) 50 #define PMU_SW_RST_GPU_MASK BIT(18) 51 52 #define PMU_PWR_GPU_PWR_DWN_MASK BIT(2) 53 #define PMU_PWR_VPU_PWR_DWN_MASK BIT(3) 54 55 #define PMU_ISO_VIDEO_MASK BIT(0) 56 #define PMU_ISO_GPU_MASK BIT(1) 57 58 #endif 59
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