1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * arch/arm/mach-ep93xx/soc.h
4 *
5 * Copyright (C) 2012 Open Kernel Labs <www.ok-labs.com>
6 * Copyright (C) 2012 Ryan Mallon <rmallon@gmail.com>
7 */
8
9 #ifndef _EP93XX_SOC_H
10 #define _EP93XX_SOC_H
11
12 #include "ep93xx-regs.h"
13 #include "irqs.h"
14
15 /*
16 * EP93xx Physical Memory Map:
17 *
18 * The ASDO pin is sampled at system reset to select a synchronous or
19 * asynchronous boot configuration. When ASDO is "1" (i.e. pulled-up)
20 * the synchronous boot mode is selected. When ASDO is "" (i.e
21 * pulled-down) the asynchronous boot mode is selected.
22 *
23 * In synchronous boot mode nSDCE3 is decoded starting at physical address
24 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26 * decoded at 0xf0000000.
27 *
28 * There is known errata for the EP93xx dealing with External Memory
29 * Configurations. Please refer to "AN273: EP93xx Silicon Rev E Design
30 * Guidelines" for more information. This document can be found at:
31 *
32 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
33 */
34
35 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37 #define EP93XX_CS1_PHYS_BASE 0x10000000
38 #define EP93XX_CS2_PHYS_BASE 0x20000000
39 #define EP93XX_CS3_PHYS_BASE 0x30000000
40 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
41 #define EP93XX_CS6_PHYS_BASE 0x60000000
42 #define EP93XX_CS7_PHYS_BASE 0x70000000
43 #define EP93XX_SDCE0_PHYS_BASE 0xc0000000
44 #define EP93XX_SDCE1_PHYS_BASE 0xd0000000
45 #define EP93XX_SDCE2_PHYS_BASE 0xe0000000
46 #define EP93XX_SDCE3_PHYS_BASE_ASYNC 0xf0000000 /* ASDO Pin = 0 */
47 #define EP93XX_CS0_PHYS_BASE_SYNC 0xf0000000 /* ASDO Pin = 1 */
48
49 /* AHB peripherals */
50 #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
51
52 #define EP93XX_ETHERNET_PHYS_BASE EP93XX_AHB_PHYS(0x00010000)
53 #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
54
55 #define EP93XX_USB_PHYS_BASE EP93XX_AHB_PHYS(0x00020000)
56 #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
57
58 #define EP93XX_RASTER_PHYS_BASE EP93XX_AHB_PHYS(0x00030000)
59 #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
60
61 #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
62
63 #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
64
65 #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
66
67 #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
68
69 #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000)
70 #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
71
72 #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
73
74 #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
75
76 /* APB peripherals */
77 #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
78
79 #define EP93XX_I2S_PHYS_BASE EP93XX_APB_PHYS(0x00020000)
80 #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
81
82 #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
83
84 #define EP93XX_AAC_PHYS_BASE EP93XX_APB_PHYS(0x00080000)
85 #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
86
87 #define EP93XX_SPI_PHYS_BASE EP93XX_APB_PHYS(0x000a0000)
88 #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
89
90 #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
91
92 #define EP93XX_KEY_MATRIX_PHYS_BASE EP93XX_APB_PHYS(0x000f0000)
93 #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
94
95 #define EP93XX_ADC_PHYS_BASE EP93XX_APB_PHYS(0x00100000)
96 #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
97 #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
98
99 #define EP93XX_PWM_PHYS_BASE EP93XX_APB_PHYS(0x00110000)
100 #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
101
102 #define EP93XX_RTC_PHYS_BASE EP93XX_APB_PHYS(0x00120000)
103 #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
104
105 #define EP93XX_WATCHDOG_PHYS_BASE EP93XX_APB_PHYS(0x00140000)
106 #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
107
108 /* System controller */
109 #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
110 #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
111 #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
112 #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
113 #define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
114 #define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
115 #define EP93XX_SYSCON_PWRCNT_USH_EN 28
116 #define EP93XX_SYSCON_PWRCNT_DMA_M2M1 27
117 #define EP93XX_SYSCON_PWRCNT_DMA_M2M0 26
118 #define EP93XX_SYSCON_PWRCNT_DMA_M2P8 25
119 #define EP93XX_SYSCON_PWRCNT_DMA_M2P9 24
120 #define EP93XX_SYSCON_PWRCNT_DMA_M2P6 23
121 #define EP93XX_SYSCON_PWRCNT_DMA_M2P7 22
122 #define EP93XX_SYSCON_PWRCNT_DMA_M2P4 21
123 #define EP93XX_SYSCON_PWRCNT_DMA_M2P5 20
124 #define EP93XX_SYSCON_PWRCNT_DMA_M2P2 19
125 #define EP93XX_SYSCON_PWRCNT_DMA_M2P3 18
126 #define EP93XX_SYSCON_PWRCNT_DMA_M2P0 17
127 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1 16
128 #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
129 #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
130 #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
131 #define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
132 #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
133 #define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
134 #define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
135 #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
136 #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
137 #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
138 #define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
139 #define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
140 #define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
141 #define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
142 #define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
143 #define EP93XX_SYSCON_DEVCFG_U3EN 24
144 #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
145 #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
146 #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
147 #define EP93XX_SYSCON_DEVCFG_U2EN 20
148 #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
149 #define EP93XX_SYSCON_DEVCFG_U1EN 18
150 #define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
151 #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
152 #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
153 #define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
154 #define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
155 #define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
156 #define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
157 #define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
158 #define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
159 #define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
160 #define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
161 #define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
162 #define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
163 #define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
164 #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
165 #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
166 #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
167 #define EP93XX_SYSCON_CLKDIV_ENABLE 15
168 #define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
169 #define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
170 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
171 #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
172 #define EP93XX_SYSCON_I2SCLKDIV_SENA 31
173 #define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
174 #define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
175 #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
176 #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
177 #define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
178 #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
179 #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
180 #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
181 #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN 31
182 #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV 16
183 #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN 15
184 #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
185 #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
186 #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
187 #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
188 #define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
189 #define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
190 #define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
191 #define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
192 #define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
193 #define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
194 #define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
195 #define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
196 #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
197
198 /* EP93xx System Controller software locked register write */
199 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
200 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
201
202 static inline void ep93xx_devcfg_set_bits(unsigned int bits)
203 {
204 ep93xx_devcfg_set_clear(bits, 0x00);
205 }
206
207 static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
208 {
209 ep93xx_devcfg_set_clear(0x00, bits);
210 }
211
212 #endif /* _EP93XX_SOC_H */
213
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