1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Copyright 2011 Linaro Ltd.
5 */
6
7 #include <linux/init.h>
8 #include <linux/of_address.h>
9 #include <linux/of.h>
10 #include <linux/smp.h>
11
12 #include <asm/cacheflush.h>
13 #include <asm/page.h>
14 #include <asm/smp_scu.h>
15 #include <asm/mach/map.h>
16
17 #include "common.h"
18 #include "hardware.h"
19
20 u32 g_diag_reg;
21 static void __iomem *scu_base;
22
23 static struct map_desc scu_io_desc __initdata = {
24 /* .virtual and .pfn are run-time assigned */
25 .length = SZ_4K,
26 .type = MT_DEVICE,
27 };
28
29 void __init imx_scu_map_io(void)
30 {
31 unsigned long base;
32
33 /* Get SCU base */
34 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
35
36 scu_io_desc.virtual = IMX_IO_P2V(base);
37 scu_io_desc.pfn = __phys_to_pfn(base);
38 iotable_init(&scu_io_desc, 1);
39
40 scu_base = IMX_IO_ADDRESS(base);
41 }
42
43 static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
44 {
45 imx_set_cpu_jump(cpu, v7_secondary_startup);
46 imx_enable_cpu(cpu, true);
47 return 0;
48 }
49
50 /*
51 * Initialise the CPU possible map early - this describes the CPUs
52 * which may be present or become present in the system.
53 */
54 static void __init imx_smp_init_cpus(void)
55 {
56 int i, ncores;
57
58 ncores = scu_get_core_count(scu_base);
59
60 for (i = ncores; i < NR_CPUS; i++)
61 set_cpu_possible(i, false);
62 }
63
64 void imx_smp_prepare(void)
65 {
66 scu_enable(scu_base);
67 }
68
69 static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
70 {
71 imx_smp_prepare();
72
73 /*
74 * The diagnostic register holds the errata bits. Mostly bootloader
75 * does not bring up secondary cores, so that when errata bits are set
76 * in bootloader, they are set only for boot cpu. But on a SMP
77 * configuration, it should be equally done on every single core.
78 * Read the register from boot cpu here, and will replicate it into
79 * secondary cores when booting them.
80 */
81 asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
82 sync_cache_w(&g_diag_reg);
83 }
84
85 const struct smp_operations imx_smp_ops __initconst = {
86 .smp_init_cpus = imx_smp_init_cpus,
87 .smp_prepare_cpus = imx_smp_prepare_cpus,
88 .smp_boot_secondary = imx_boot_secondary,
89 #ifdef CONFIG_HOTPLUG_CPU
90 .cpu_die = imx_cpu_die,
91 .cpu_kill = imx_cpu_kill,
92 #endif
93 };
94
95 /*
96 * Initialise the CPU possible map early - this describes the CPUs
97 * which may be present or become present in the system.
98 */
99 static void __init imx7_smp_init_cpus(void)
100 {
101 struct device_node *np;
102 int i, ncores = 0;
103
104 /* The iMX7D SCU does not report core count, get it from DT */
105 for_each_of_cpu_node(np)
106 ncores++;
107
108 for (i = ncores; i < NR_CPUS; i++)
109 set_cpu_possible(i, false);
110 }
111
112 const struct smp_operations imx7_smp_ops __initconst = {
113 .smp_init_cpus = imx7_smp_init_cpus,
114 .smp_boot_secondary = imx_boot_secondary,
115 #ifdef CONFIG_HOTPLUG_CPU
116 .cpu_die = imx_cpu_die,
117 .cpu_kill = imx_cpu_kill,
118 #endif
119 };
120
121 #define DCFG_CCSR_SCRATCHRW1 0x200
122
123 static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
124 {
125 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
126
127 return 0;
128 }
129
130 static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
131 {
132 struct device_node *np;
133 void __iomem *dcfg_base;
134 unsigned long paddr;
135
136 np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
137 dcfg_base = of_iomap(np, 0);
138 of_node_put(np);
139 BUG_ON(!dcfg_base);
140
141 paddr = __pa_symbol(secondary_startup);
142 writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
143
144 iounmap(dcfg_base);
145 }
146
147 const struct smp_operations ls1021a_smp_ops __initconst = {
148 .smp_prepare_cpus = ls1021a_smp_prepare_cpus,
149 .smp_boot_secondary = ls1021a_boot_secondary,
150 };
151
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