1 /*
2 * Hardware definitions for TI OMAP processors and boards
3 *
4 * NOTE: Please put device driver specific defines into a separate header
5 * file for each driver.
6 *
7 * Copyright (C) 2001 RidgeRun, Inc.
8 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
9 *
10 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
11 * and Dirk Behme <dirk.behme@de.bosch.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
35 #define __ASM_ARCH_OMAP_HARDWARE_H
36
37 #include <linux/sizes.h>
38 #include <linux/soc/ti/omap1-io.h>
39 #ifndef __ASSEMBLER__
40 #include <asm/types.h>
41 #include <linux/soc/ti/omap1-soc.h>
42
43 #include "tc.h"
44
45 /* Almost all documentation for chip and board memory maps assumes
46 * BM is clear. Most devel boards have a switch to control booting
47 * from NOR flash (using external chipselect 3) rather than mask ROM,
48 * which uses BM to interchange the physical CS0 and CS3 addresses.
49 */
50 static inline u32 omap_cs0m_phys(void)
51 {
52 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
53 ? OMAP_CS3_PHYS : 0;
54 }
55
56 static inline u32 omap_cs3_phys(void)
57 {
58 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
59 ? 0 : OMAP_CS3_PHYS;
60 }
61
62 #endif /* ifndef __ASSEMBLER__ */
63
64 #define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
65 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
66
67 #include "serial.h"
68
69 /*
70 * ---------------------------------------------------------------------------
71 * Common definitions for all OMAP processors
72 * NOTE: Put all processor or board specific parts to the special header
73 * files.
74 * ---------------------------------------------------------------------------
75 */
76
77 /*
78 * ----------------------------------------------------------------------------
79 * Timers
80 * ----------------------------------------------------------------------------
81 */
82 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
83 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
84 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
85 #define MPU_TIMER_FREE (1 << 6)
86 #define MPU_TIMER_CLOCK_ENABLE (1 << 5)
87 #define MPU_TIMER_AR (1 << 1)
88 #define MPU_TIMER_ST (1 << 0)
89
90 /*
91 * ---------------------------------------------------------------------------
92 * Watchdog timer
93 * ---------------------------------------------------------------------------
94 */
95
96 /* Watchdog timer within the OMAP3.2 gigacell */
97 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
98 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
99 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
100 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
101 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
102
103 /*
104 * ---------------------------------------------------------------------------
105 * Interrupts
106 * ---------------------------------------------------------------------------
107 */
108 #ifdef CONFIG_ARCH_OMAP1
109
110 /*
111 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
112 * or something similar.. -- PFM.
113 */
114
115 #define OMAP_IH1_BASE 0xfffecb00
116 #define OMAP_IH2_BASE 0xfffe0000
117 #define OMAP_IH2_0_BASE (0xfffe0000)
118 #define OMAP_IH2_1_BASE (0xfffe0100)
119 #define OMAP_IH2_2_BASE (0xfffe0200)
120 #define OMAP_IH2_3_BASE (0xfffe0300)
121
122 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
123 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
124 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
125 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
126 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
127 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
128 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
129
130 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
131 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
132 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
133 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
134 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
135 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
136 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
137
138 #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
139 #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
140 #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
141 #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
142 #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
143 #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
144 #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
145
146 #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
147 #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
148 #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
149 #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
150 #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
151 #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
152 #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
153
154 #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
155 #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
156 #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
157 #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
158 #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
159 #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
160 #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
161
162 #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
163 #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
164 #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
165 #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
166 #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
167 #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
168 #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
169
170 #define IRQ_ITR_REG_OFFSET 0x00
171 #define IRQ_MIR_REG_OFFSET 0x04
172 #define IRQ_SIR_IRQ_REG_OFFSET 0x10
173 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
174 #define IRQ_CONTROL_REG_OFFSET 0x18
175 #define IRQ_ISR_REG_OFFSET 0x9c
176 #define IRQ_ILR0_REG_OFFSET 0x1c
177 #define IRQ_GMR_REG_OFFSET 0xa0
178
179 #endif
180
181 /* Timer32K for 1610 and 1710*/
182 #define OMAP_TIMER32K_BASE 0xFFFBC400
183
184 /*
185 * ---------------------------------------------------------------------------
186 * TIPB bus interface
187 * ---------------------------------------------------------------------------
188 */
189 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
190 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
191 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
192 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
193
194 /*
195 * ----------------------------------------------------------------------------
196 * MPUI interface
197 * ----------------------------------------------------------------------------
198 */
199 #define MPUI_BASE (0xfffec900)
200 #define MPUI_CTRL (MPUI_BASE + 0x0)
201 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
202 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
203 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
204 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
205 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
206 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
207 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
208
209 /*
210 * ----------------------------------------------------------------------------
211 * LED Pulse Generator
212 * ----------------------------------------------------------------------------
213 */
214 #define OMAP_LPG1_BASE 0xfffbd000
215 #define OMAP_LPG2_BASE 0xfffbd800
216 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
217 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
218 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
219 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
220
221 /*
222 * ---------------------------------------------------------------------------
223 * DSP
224 * ---------------------------------------------------------------------------
225 */
226
227 #define OMAP1_DSP_BASE 0xE0000000
228 #define OMAP1_DSP_SIZE 0x28000
229 #define OMAP1_DSP_START 0xE0000000
230
231 #define OMAP1_DSPREG_BASE 0xE1000000
232 #define OMAP1_DSPREG_SIZE SZ_128K
233 #define OMAP1_DSPREG_START 0xE1000000
234
235 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */
236
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