1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * linux/arch/arm/mach-omap1/mux.c
4 *
5 * OMAP1 pin multiplexing configurations
6 *
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 */
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/spinlock.h>
15 #include <linux/soc/ti/omap1-io.h>
16
17 #include "hardware.h"
18 #include "mux.h"
19
20 #ifdef CONFIG_OMAP_MUX
21
22 static struct omap_mux_cfg arch_mux_cfg;
23
24 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
25 static struct pin_config omap1xxx_pins[] = {
26 /*
27 * description mux mode mux pull pull pull pu_pd pu dbg
28 * reg offset mode reg bit ena reg
29 */
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
32
33 /* UART2 (COM_UART_GATING), conflicts with USB2 */
34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
38
39 /* UART3 (GIGA_UART_GATING) */
40 MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
41 MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
42 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
43 MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
44 MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
45 MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
46 MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
47
48 /* PWT & PWL, conflicts with UART3 */
49 MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
50 MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
51
52 /* USB internal master generic */
53 MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
54 MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
55 /* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
56 MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
57 MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
58 MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
59 MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
60
61 /* USB1 master */
62 MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
63 MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
64 MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
65 MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
66 MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
67 MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
68 MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
69 MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
70 MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
71 MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
72 MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
73
74 /* USB2 master */
75 MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
76 MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
77 MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
78 MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
79 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
80 MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
81 MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
82
83 /* OMAP-1510 GPIO */
84 MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
85 MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
86 MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
87
88 /* OMAP1610 GPIO */
89 MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
90 MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
91
92 /* OMAP-1710 GPIO */
93 MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
94 MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
95 MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
96 MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
97
98 /* MPUIO */
99 MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
100 MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
101 MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
102 MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
103
104 MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
105 MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
106 MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
107 MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
108 MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
109 MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
110 MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
111 MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
112 MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
113
114 /* MCBSP2 */
115 MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
116 MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
117 MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
118 MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
119 MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
120 MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
121
122 /* MCBSP3 NOTE: Mode must 1 for clock */
123 MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
124
125 /* Misc ballouts */
126 MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
127 MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
128
129 /* OMAP-1610 MMC2 */
130 MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
131 MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
132 MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
133 MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
134 MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
135 MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
136 MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
137 MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
138 MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
139 MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
140
141 /* OMAP-1610 External Trace Interface */
142 MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
143 MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
144 MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
145 MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
146 MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
147 MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
148
149 /* OMAP16XX GPIO */
150 MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
151 MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
152 MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
153 MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
154 MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
155 MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
156 MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
157 MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
158 MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
159 MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
160 MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
161 MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
162 MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
163
164 /* OMAP-1610 uWire */
165 MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
166 MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
167 MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
168 MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
169 MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
170 MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
171
172 /* OMAP-1610 SPI */
173 MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
174 MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
175 MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
176 MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
177 MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
178 MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
179 MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
180 MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
181 MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
182
183 /* OMAP-1610 Flash */
184 MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
185 MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
186
187 /* First MMC interface, same on 1510, 1610 and 1710 */
188 MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
189 MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
190 MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
191 MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
192 MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
193 MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
194 MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
195 MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
196 MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
197
198 /* OMAP-1610 USB0 alternate configuration */
199 MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
200 MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
201 MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
202 MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
203 MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
204 MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
205 MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
206 MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
207
208 /* USB2 interface */
209 MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
210 MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
211 MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
212 MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
213 MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
214 MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
215
216 /* 16XX UART */
217 MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
218 MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
219 MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
220 MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
221 MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
222 MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
223
224 /* I2C interface */
225 MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
226 MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
227
228 /* Keypad */
229 MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
230 MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
231 MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
232 MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
233 MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
234 MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
235 MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
236 MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
237 MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
238 MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
239 MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
240
241 /* Power management */
242 MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
243
244 /* MCLK Settings */
245 MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
246 MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
247 MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
248 MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
249
250 /* CompactFlash controller, conflicts with MMC1 */
251 MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
252 MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
253 MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
254 MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
255 MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
256
257 /* parallel camera */
258 MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
259 MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
260 MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
261 MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
262 MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
263 MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
264 MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
265 MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
266 MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
267 MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
268 MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
269 MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
270 MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0)
271
272 /* serial camera */
273 MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
274 /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
275 MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
276 MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
277 MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
278 MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
279 };
280 #define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
281 #else
282 #define omap1xxx_pins NULL
283 #define OMAP1XXX_PINS_SZ 0
284 #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
285
286 static int omap1_cfg_reg(const struct pin_config *cfg)
287 {
288 static DEFINE_SPINLOCK(mux_spin_lock);
289 unsigned long flags;
290 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
291 pull_orig = 0, pull = 0;
292 unsigned int mask, warn = 0;
293
294 /* Check the mux register in question */
295 if (cfg->mux_reg) {
296 unsigned tmp1, tmp2;
297
298 spin_lock_irqsave(&mux_spin_lock, flags);
299 reg_orig = omap_readl(cfg->mux_reg);
300
301 /* The mux registers always seem to be 3 bits long */
302 mask = (0x7 << cfg->mask_offset);
303 tmp1 = reg_orig & mask;
304 reg = reg_orig & ~mask;
305
306 tmp2 = (cfg->mask << cfg->mask_offset);
307 reg |= tmp2;
308
309 if (tmp1 != tmp2)
310 warn = 1;
311
312 omap_writel(reg, cfg->mux_reg);
313 spin_unlock_irqrestore(&mux_spin_lock, flags);
314 }
315
316 /* Check for pull up or pull down selection on 1610 */
317 if (!cpu_is_omap15xx()) {
318 if (cfg->pu_pd_reg && cfg->pull_val) {
319 spin_lock_irqsave(&mux_spin_lock, flags);
320 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
321 mask = 1 << cfg->pull_bit;
322
323 if (cfg->pu_pd_val) {
324 if (!(pu_pd_orig & mask))
325 warn = 1;
326 /* Use pull up */
327 pu_pd = pu_pd_orig | mask;
328 } else {
329 if (pu_pd_orig & mask)
330 warn = 1;
331 /* Use pull down */
332 pu_pd = pu_pd_orig & ~mask;
333 }
334 omap_writel(pu_pd, cfg->pu_pd_reg);
335 spin_unlock_irqrestore(&mux_spin_lock, flags);
336 }
337 }
338
339 /* Check for an associated pull down register */
340 if (cfg->pull_reg) {
341 spin_lock_irqsave(&mux_spin_lock, flags);
342 pull_orig = omap_readl(cfg->pull_reg);
343 mask = 1 << cfg->pull_bit;
344
345 if (cfg->pull_val) {
346 if (pull_orig & mask)
347 warn = 1;
348 /* Low bit = pull enabled */
349 pull = pull_orig & ~mask;
350 } else {
351 if (!(pull_orig & mask))
352 warn = 1;
353 /* High bit = pull disabled */
354 pull = pull_orig | mask;
355 }
356
357 omap_writel(pull, cfg->pull_reg);
358 spin_unlock_irqrestore(&mux_spin_lock, flags);
359 }
360
361 if (warn) {
362 #ifdef CONFIG_OMAP_MUX_WARNINGS
363 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
364 #endif
365 }
366
367 #ifdef CONFIG_OMAP_MUX_DEBUG
368 if (cfg->debug || warn) {
369 printk("MUX: Setting register %s\n", cfg->name);
370 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
371 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
372
373 if (!cpu_is_omap15xx()) {
374 if (cfg->pu_pd_reg && cfg->pull_val) {
375 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
376 cfg->pu_pd_name, cfg->pu_pd_reg,
377 pu_pd_orig, pu_pd);
378 }
379 }
380
381 if (cfg->pull_reg)
382 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
383 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
384 }
385 #endif
386
387 #ifdef CONFIG_OMAP_MUX_WARNINGS
388 return warn ? -ETXTBSY : 0;
389 #else
390 return 0;
391 #endif
392 }
393
394 static struct omap_mux_cfg *mux_cfg;
395
396 int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
397 {
398 if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
399 || !arch_mux_cfg->cfg_reg) {
400 printk(KERN_ERR "Invalid pin table\n");
401 return -EINVAL;
402 }
403
404 mux_cfg = arch_mux_cfg;
405
406 return 0;
407 }
408
409 /*
410 * Sets the Omap MUX and PULL_DWN registers based on the table
411 */
412 int omap_cfg_reg(const unsigned long index)
413 {
414 struct pin_config *reg;
415
416 if (!cpu_class_is_omap1()) {
417 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
418 index);
419 WARN_ON(1);
420 return -EINVAL;
421 }
422
423 if (mux_cfg == NULL) {
424 printk(KERN_ERR "Pin mux table not initialized\n");
425 return -ENODEV;
426 }
427
428 if (index >= mux_cfg->size) {
429 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
430 index, mux_cfg->size);
431 dump_stack();
432 return -ENODEV;
433 }
434
435 reg = &mux_cfg->pins[index];
436
437 if (!mux_cfg->cfg_reg)
438 return -ENODEV;
439
440 return mux_cfg->cfg_reg(reg);
441 }
442 EXPORT_SYMBOL(omap_cfg_reg);
443
444 int __init omap1_mux_init(void)
445 {
446 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
447 arch_mux_cfg.pins = omap1xxx_pins;
448 arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
449 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
450 }
451
452 return omap_mux_register(&arch_mux_cfg);
453 }
454
455 #else
456 #define omap_mux_init() do {} while(0)
457 #define omap_cfg_reg(x) do {} while(0)
458 #endif /* CONFIG_OMAP_MUX */
459
460
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