1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * OMAP2xxx Clock Management (CM) register definitions
4 *
5 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
6 * Copyright (C) 2007-2010 Nokia Corporation
7 * Paul Walmsley
8 *
9 * The CM hardware modules on the OMAP2/3 are quite similar to each
10 * other. The CM modules/instances on OMAP4 are quite different, so
11 * they are handled in a separate file.
12 */
13 #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_H
14 #define __ARCH_ASM_MACH_OMAP2_CM2XXX_H
15
16 #include "prcm-common.h"
17 #include "cm2xxx_3xxx.h"
18
19 #define OMAP2420_CM_REGADDR(module, reg) \
20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
21 #define OMAP2430_CM_REGADDR(module, reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
23
24 /*
25 * Module specific CM register offsets from CM_BASE + domain offset
26 * Use cm_{read,write}_mod_reg() with these registers.
27 * These register offsets generally appear in more than one PRCM submodule.
28 */
29
30 /* OMAP2-specific register offsets */
31
32 #define OMAP24XX_CM_FCLKEN2 0x0004
33 #define OMAP24XX_CM_ICLKEN4 0x001c
34 #define OMAP24XX_CM_AUTOIDLE4 0x003c
35 #define OMAP24XX_CM_IDLEST4 0x002c
36
37 /* CM_IDLEST bit field values to indicate deasserted IdleReq */
38
39 #define OMAP24XX_CM_IDLEST_VAL 0
40
41
42 /* Clock management domain register get/set */
43
44 #ifndef __ASSEMBLER__
45
46 extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
47 extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
48
49 extern int omap2xxx_cm_fclks_active(void);
50 extern int omap2xxx_cm_mpu_retention_allowed(void);
51 extern u32 omap2xxx_cm_get_core_clk_src(void);
52 extern u32 omap2xxx_cm_get_core_pll_config(void);
53 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
54 u32 mdm);
55
56 int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
57
58 #endif
59
60 #endif
61
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