1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP4 specific common source file.
4 *
5 * Copyright (C) 2010 Texas Instruments, Inc.
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/memblock.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/export.h>
19 #include <linux/irqchip/arm-gic.h>
20 #include <linux/of_address.h>
21 #include <linux/reboot.h>
22 #include <linux/genalloc.h>
23
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
26 #include <asm/memblock.h>
27 #include <asm/smp_twd.h>
28
29 #include "omap-wakeupgen.h"
30 #include "soc.h"
31 #include "iomap.h"
32 #include "common.h"
33 #include "prminst44xx.h"
34 #include "prcm_mpu44xx.h"
35 #include "omap4-sar-layout.h"
36 #include "omap-secure.h"
37 #include "sram.h"
38
39 #ifdef CONFIG_CACHE_L2X0
40 static void __iomem *l2cache_base;
41 #endif
42
43 static void __iomem *sar_ram_base;
44 static void __iomem *gic_dist_base_addr;
45 static void __iomem *twd_base;
46
47 #define IRQ_LOCALTIMER 29
48
49 #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
50
51 /* Used to implement memory barrier on DRAM path */
52 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
53
54 static void __iomem *dram_sync, *sram_sync;
55 static phys_addr_t dram_sync_paddr;
56 static u32 dram_sync_size;
57
58 /*
59 * The OMAP4 bus structure contains asynchronous bridges which can buffer
60 * data writes from the MPU. These asynchronous bridges can be found on
61 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
62 *
63 * We need to be careful about re-ordering which can happen as a result
64 * of different accesses being performed via different paths, and
65 * therefore different asynchronous bridges.
66 */
67
68 /*
69 * OMAP4 interconnect barrier which is called for each mb() and wmb().
70 * This is to ensure that normal paths to DRAM (normal memory, cacheable
71 * accesses) are properly synchronised with writes to DMA coherent memory
72 * (normal memory, uncacheable) and device writes.
73 *
74 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
75 * path, as we need to ensure that data is visible to other system
76 * masters prior to writes to those system masters being seen.
77 *
78 * Note: the SRAM path is not synchronised via mb() and wmb().
79 */
80 static void omap4_mb(void)
81 {
82 if (dram_sync)
83 writel_relaxed(0, dram_sync);
84 }
85
86 /*
87 * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
88 *
89 * If a data is stalled inside asynchronous bridge because of back
90 * pressure, it may be accepted multiple times, creating pointer
91 * misalignment that will corrupt next transfers on that data path until
92 * next reset of the system. No recovery procedure once the issue is hit,
93 * the path remains consistently broken.
94 *
95 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
96 * interconnects.
97 *
98 * This situation can happen only when the idle is initiated by a Master
99 * Request Disconnection (which is trigged by software when executing WFI
100 * on the CPU).
101 *
102 * The work-around for this errata needs all the initiators connected
103 * through an async bridge to ensure that data path is properly drained
104 * before issuing WFI. This condition will be met if one Strongly ordered
105 * access is performed to the target right before executing the WFI.
106 *
107 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
108 * IO barrier ensure that there is no synchronisation loss on initiators
109 * operating on both interconnect port simultaneously.
110 *
111 * This is a stronger version of the OMAP4 memory barrier below, and
112 * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
113 * as well, and is necessary prior to executing a WFI.
114 */
115 void omap_interconnect_sync(void)
116 {
117 if (dram_sync && sram_sync) {
118 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
119 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
120 isb();
121 }
122 }
123
124 static int __init omap4_sram_init(void)
125 {
126 struct device_node *np;
127 struct gen_pool *sram_pool;
128
129 if (!soc_is_omap44xx() && !soc_is_omap54xx())
130 return 0;
131
132 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
133 if (!np)
134 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
135 __func__);
136 sram_pool = of_gen_pool_get(np, "sram", 0);
137 if (!sram_pool)
138 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
139 __func__);
140 else
141 sram_sync = (void __iomem *)gen_pool_alloc(sram_pool, PAGE_SIZE);
142 of_node_put(np);
143
144 return 0;
145 }
146 omap_arch_initcall(omap4_sram_init);
147
148 /* Steal one page physical memory for barrier implementation */
149 void __init omap_barrier_reserve_memblock(void)
150 {
151 dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
152 dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
153 }
154
155 void __init omap_barriers_init(void)
156 {
157 struct map_desc dram_io_desc[1];
158
159 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
160 dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
161 dram_io_desc[0].length = dram_sync_size;
162 dram_io_desc[0].type = MT_MEMORY_RW_SO;
163 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
164 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
165
166 pr_info("OMAP4: Map %pa to %p for dram barrier\n",
167 &dram_sync_paddr, dram_sync);
168
169 soc_mb = omap4_mb;
170 }
171
172 #endif
173
174 void gic_dist_disable(void)
175 {
176 if (gic_dist_base_addr)
177 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
178 }
179
180 void gic_dist_enable(void)
181 {
182 if (gic_dist_base_addr)
183 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
184 }
185
186 bool gic_dist_disabled(void)
187 {
188 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
189 }
190
191 void gic_timer_retrigger(void)
192 {
193 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
194 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
195 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
196
197 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
198 /*
199 * The local timer interrupt got lost while the distributor was
200 * disabled. Ack the pending interrupt, and retrigger it.
201 */
202 pr_warn("%s: lost localtimer interrupt\n", __func__);
203 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
204 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
205 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
206 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
207 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
208 }
209 }
210 }
211
212 #ifdef CONFIG_CACHE_L2X0
213
214 void __iomem *omap4_get_l2cache_base(void)
215 {
216 return l2cache_base;
217 }
218
219 void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
220 {
221 unsigned smc_op;
222
223 switch (reg) {
224 case L2X0_CTRL:
225 smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
226 break;
227
228 case L2X0_AUX_CTRL:
229 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
230 break;
231
232 case L2X0_DEBUG_CTRL:
233 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
234 break;
235
236 case L310_PREFETCH_CTRL:
237 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
238 break;
239
240 case L310_POWER_CTRL:
241 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
242 return;
243
244 default:
245 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
246 return;
247 }
248
249 omap_smc1(smc_op, val);
250 }
251
252 int __init omap_l2_cache_init(void)
253 {
254 /* Static mapping, never released */
255 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
256 if (WARN_ON(!l2cache_base))
257 return -ENOMEM;
258 return 0;
259 }
260 #endif
261
262 void __iomem *omap4_get_sar_ram_base(void)
263 {
264 return sar_ram_base;
265 }
266
267 /*
268 * SAR RAM used to save and restore the HW context in low power modes.
269 * Note that we need to initialize this very early for kexec. See
270 * omap4_mpuss_early_init().
271 */
272 void __init omap4_sar_ram_init(void)
273 {
274 unsigned long sar_base;
275
276 /*
277 * To avoid code running on other OMAPs in
278 * multi-omap builds
279 */
280 if (cpu_is_omap44xx())
281 sar_base = OMAP44XX_SAR_RAM_BASE;
282 else if (soc_is_omap54xx())
283 sar_base = OMAP54XX_SAR_RAM_BASE;
284 else
285 return;
286
287 /* Static mapping, never released */
288 sar_ram_base = ioremap(sar_base, SZ_16K);
289 if (WARN_ON(!sar_ram_base))
290 return;
291 }
292
293 static const struct of_device_id intc_match[] = {
294 { .compatible = "ti,omap4-wugen-mpu", },
295 { .compatible = "ti,omap5-wugen-mpu", },
296 { },
297 };
298
299 static struct device_node *intc_node;
300
301 void __init omap_gic_of_init(void)
302 {
303 struct device_node *np;
304
305 intc_node = of_find_matching_node(NULL, intc_match);
306 if (WARN_ON(!intc_node)) {
307 pr_err("No WUGEN found in DT, system will misbehave.\n");
308 pr_err("UPDATE YOUR DEVICE TREE!\n");
309 }
310
311 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
312 if (!cpu_is_omap446x())
313 goto skip_errata_init;
314
315 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
316 gic_dist_base_addr = of_iomap(np, 0);
317 of_node_put(np);
318 WARN_ON(!gic_dist_base_addr);
319
320 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
321 twd_base = of_iomap(np, 0);
322 of_node_put(np);
323 WARN_ON(!twd_base);
324
325 skip_errata_init:
326 irqchip_init();
327 }
328
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