1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * OMAP4 Voltage Controller (VC) data
4 *
5 * Copyright (C) 2007, 2010 Texas Instruments, Inc.
6 * Rajendra Nayak <rnayak@ti.com>
7 * Lesly A M <x0080970@ti.com>
8 * Thara Gopinath <thara@ti.com>
9 *
10 * Copyright (C) 2008, 2011 Nokia Corporation
11 * Kalle Jokiniemi
12 * Paul Walmsley
13 */
14 #include <linux/io.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17
18 #include "common.h"
19
20 #include "prm44xx.h"
21 #include "prm-regbits-44xx.h"
22 #include "voltage.h"
23
24 #include "vc.h"
25
26 /*
27 * VC data common to 44xx chips
28 * XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
29 */
30 static const struct omap_vc_common omap4_vc_common = {
31 .bypass_val_reg = OMAP4_PRM_VC_VAL_BYPASS_OFFSET,
32 .data_shift = OMAP4430_DATA_SHIFT,
33 .slaveaddr_shift = OMAP4430_SLAVEADDR_SHIFT,
34 .regaddr_shift = OMAP4430_REGADDR_SHIFT,
35 .valid = OMAP4430_VALID_MASK,
36 .cmd_on_shift = OMAP4430_ON_SHIFT,
37 .cmd_on_mask = OMAP4430_ON_MASK,
38 .cmd_onlp_shift = OMAP4430_ONLP_SHIFT,
39 .cmd_ret_shift = OMAP4430_RET_SHIFT,
40 .cmd_off_shift = OMAP4430_OFF_SHIFT,
41 .i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
42 .i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
43 .i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
44 .i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
45 };
46
47 /* VC instance data for each controllable voltage line */
48 struct omap_vc_channel omap4_vc_mpu = {
49 .flags = OMAP_VC_CHANNEL_DEFAULT | OMAP_VC_CHANNEL_CFG_MUTANT,
50 .common = &omap4_vc_common,
51 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
52 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
53 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
54 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
55 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET,
56 .smps_sa_mask = OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK,
57 .smps_volra_mask = OMAP4430_VOLRA_VDD_MPU_L_MASK,
58 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_MPU_L_MASK,
59 .cfg_channel_sa_shift = OMAP4430_SA_VDD_MPU_L_SHIFT,
60 };
61
62 struct omap_vc_channel omap4_vc_iva = {
63 .common = &omap4_vc_common,
64 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
65 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
66 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
67 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
68 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET,
69 .smps_sa_mask = OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK,
70 .smps_volra_mask = OMAP4430_VOLRA_VDD_IVA_L_MASK,
71 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_IVA_L_MASK,
72 .cfg_channel_sa_shift = OMAP4430_SA_VDD_IVA_L_SHIFT,
73 };
74
75 struct omap_vc_channel omap4_vc_core = {
76 .common = &omap4_vc_common,
77 .smps_sa_reg = OMAP4_PRM_VC_SMPS_SA_OFFSET,
78 .smps_volra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET,
79 .smps_cmdra_reg = OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET,
80 .cfg_channel_reg = OMAP4_PRM_VC_CFG_CHANNEL_OFFSET,
81 .cmdval_reg = OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET,
82 .smps_sa_mask = OMAP4430_SA_VDD_CORE_L_0_6_MASK,
83 .smps_volra_mask = OMAP4430_VOLRA_VDD_CORE_L_MASK,
84 .smps_cmdra_mask = OMAP4430_CMDRA_VDD_CORE_L_MASK,
85 .cfg_channel_sa_shift = OMAP4430_SA_VDD_CORE_L_SHIFT,
86 };
87
88 /*
89 * Voltage levels for different operating modes: on, sleep, retention and off
90 */
91 #define OMAP4_ON_VOLTAGE_UV 1375000
92 #define OMAP4_ONLP_VOLTAGE_UV 1375000
93 #define OMAP4_RET_VOLTAGE_UV 837500
94 #define OMAP4_OFF_VOLTAGE_UV 0
95
96 struct omap_vc_param omap4_mpu_vc_data = {
97 .on = OMAP4_ON_VOLTAGE_UV,
98 .onlp = OMAP4_ONLP_VOLTAGE_UV,
99 .ret = OMAP4_RET_VOLTAGE_UV,
100 .off = OMAP4_OFF_VOLTAGE_UV,
101 };
102
103 struct omap_vc_param omap4_iva_vc_data = {
104 .on = OMAP4_ON_VOLTAGE_UV,
105 .onlp = OMAP4_ONLP_VOLTAGE_UV,
106 .ret = OMAP4_RET_VOLTAGE_UV,
107 .off = OMAP4_OFF_VOLTAGE_UV,
108 };
109
110 struct omap_vc_param omap4_core_vc_data = {
111 .on = OMAP4_ON_VOLTAGE_UV,
112 .onlp = OMAP4_ONLP_VOLTAGE_UV,
113 .ret = OMAP4_RET_VOLTAGE_UV,
114 .off = OMAP4_OFF_VOLTAGE_UV,
115 };
116
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