1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Hardware specific definitions for SL-Cx000 series of PDAs 4 * 5 * Copyright (c) 2005 Alexander Wykes 6 * Copyright (c) 2005 Richard Purdie 7 * 8 * Based on Sharp's 2.4 kernel patches 9 */ 10 #ifndef __ASM_ARCH_SPITZ_H 11 #define __ASM_ARCH_SPITZ_H 1 12 #endif 13 14 #include "irqs.h" /* PXA_NR_BUILTIN_GPIO, PXA_GPIO_TO_IRQ */ 15 #include <linux/fb.h> 16 17 /* Spitz/Akita GPIOs */ 18 19 #define SPITZ_GPIO_KEY_INT (0) /* Key Interrupt */ 20 #define SPITZ_GPIO_RESET (1) 21 #define SPITZ_GPIO_nSD_DETECT (9) 22 #define SPITZ_GPIO_TP_INT (11) /* Touch Panel interrupt */ 23 #define SPITZ_GPIO_AK_INT (13) /* Remote Control */ 24 #define SPITZ_GPIO_ADS7846_CS (14) 25 #define SPITZ_GPIO_SYNC (16) 26 #define SPITZ_GPIO_MAX1111_CS (20) 27 #define SPITZ_GPIO_FATAL_BAT (21) 28 #define SPITZ_GPIO_HSYNC (22) 29 #define SPITZ_GPIO_nSD_CLK (32) 30 #define SPITZ_GPIO_USB_DEVICE (35) 31 #define SPITZ_GPIO_USB_HOST (37) 32 #define SPITZ_GPIO_USB_CONNECT (41) 33 #define SPITZ_GPIO_LCDCON_CS (53) 34 #define SPITZ_GPIO_nPCE (54) 35 #define SPITZ_GPIO_nSD_WP (81) 36 #define SPITZ_GPIO_ON_RESET (89) 37 #define SPITZ_GPIO_BAT_COVER (90) 38 #define SPITZ_GPIO_CF_CD (94) 39 #define SPITZ_GPIO_ON_KEY (95) 40 #define SPITZ_GPIO_SWA (97) 41 #define SPITZ_GPIO_SWB (96) 42 #define SPITZ_GPIO_CHRG_FULL (101) 43 #define SPITZ_GPIO_CO (101) 44 #define SPITZ_GPIO_CF_IRQ (105) 45 #define SPITZ_GPIO_AC_IN (115) 46 #define SPITZ_GPIO_HP_IN (116) 47 48 /* Spitz Only GPIOs */ 49 50 #define SPITZ_GPIO_CF2_IRQ (106) /* CF slot1 Ready */ 51 #define SPITZ_GPIO_CF2_CD (93) 52 53 54 /* Spitz/Akita Keyboard Definitions */ 55 56 #define SPITZ_KEY_STROBE_NUM (11) 57 #define SPITZ_KEY_SENSE_NUM (7) 58 #define SPITZ_GPIO_G0_STROBE_BIT 0x0f800000 59 #define SPITZ_GPIO_G1_STROBE_BIT 0x00100000 60 #define SPITZ_GPIO_G2_STROBE_BIT 0x01000000 61 #define SPITZ_GPIO_G3_STROBE_BIT 0x00041880 62 #define SPITZ_GPIO_G0_SENSE_BIT 0x00021000 63 #define SPITZ_GPIO_G1_SENSE_BIT 0x000000d4 64 #define SPITZ_GPIO_G2_SENSE_BIT 0x08000000 65 #define SPITZ_GPIO_G3_SENSE_BIT 0x00000000 66 67 #define SPITZ_GPIO_KEY_STROBE0 88 68 #define SPITZ_GPIO_KEY_STROBE1 23 69 #define SPITZ_GPIO_KEY_STROBE2 24 70 #define SPITZ_GPIO_KEY_STROBE3 25 71 #define SPITZ_GPIO_KEY_STROBE4 26 72 #define SPITZ_GPIO_KEY_STROBE5 27 73 #define SPITZ_GPIO_KEY_STROBE6 52 74 #define SPITZ_GPIO_KEY_STROBE7 103 75 #define SPITZ_GPIO_KEY_STROBE8 107 76 #define SPITZ_GPIO_KEY_STROBE9 108 77 #define SPITZ_GPIO_KEY_STROBE10 114 78 79 #define SPITZ_GPIO_KEY_SENSE0 12 80 #define SPITZ_GPIO_KEY_SENSE1 17 81 #define SPITZ_GPIO_KEY_SENSE2 91 82 #define SPITZ_GPIO_KEY_SENSE3 34 83 #define SPITZ_GPIO_KEY_SENSE4 36 84 #define SPITZ_GPIO_KEY_SENSE5 38 85 #define SPITZ_GPIO_KEY_SENSE6 39 86 87 88 /* Spitz Scoop Device (No. 1) GPIOs */ 89 /* Suspend States in comments */ 90 #define SPITZ_SCP_LED_GREEN SCOOP_GPCR_PA11 /* Keep */ 91 #define SPITZ_SCP_JK_B SCOOP_GPCR_PA12 /* Keep */ 92 #define SPITZ_SCP_CHRG_ON SCOOP_GPCR_PA13 /* Keep */ 93 #define SPITZ_SCP_MUTE_L SCOOP_GPCR_PA14 /* Low */ 94 #define SPITZ_SCP_MUTE_R SCOOP_GPCR_PA15 /* Low */ 95 #define SPITZ_SCP_CF_POWER SCOOP_GPCR_PA16 /* Keep */ 96 #define SPITZ_SCP_LED_ORANGE SCOOP_GPCR_PA17 /* Keep */ 97 #define SPITZ_SCP_JK_A SCOOP_GPCR_PA18 /* Low */ 98 #define SPITZ_SCP_ADC_TEMP_ON SCOOP_GPCR_PA19 /* Low */ 99 100 #define SPITZ_SCP_IO_DIR (SPITZ_SCP_JK_B | SPITZ_SCP_CHRG_ON | \ 101 SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | \ 102 SPITZ_SCP_CF_POWER | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 103 #define SPITZ_SCP_IO_OUT (SPITZ_SCP_CHRG_ON | SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R) 104 #define SPITZ_SCP_SUS_CLR (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON) 105 #define SPITZ_SCP_SUS_SET 0 106 107 #define SPITZ_SCP_GPIO_BASE (PXA_NR_BUILTIN_GPIO) 108 #define SPITZ_GPIO_LED_GREEN (SPITZ_SCP_GPIO_BASE + 0) 109 #define SPITZ_GPIO_JK_B (SPITZ_SCP_GPIO_BASE + 1) 110 #define SPITZ_GPIO_CHRG_ON (SPITZ_SCP_GPIO_BASE + 2) 111 #define SPITZ_GPIO_MUTE_L (SPITZ_SCP_GPIO_BASE + 3) 112 #define SPITZ_GPIO_MUTE_R (SPITZ_SCP_GPIO_BASE + 4) 113 #define SPITZ_GPIO_CF_POWER (SPITZ_SCP_GPIO_BASE + 5) 114 #define SPITZ_GPIO_LED_ORANGE (SPITZ_SCP_GPIO_BASE + 6) 115 #define SPITZ_GPIO_JK_A (SPITZ_SCP_GPIO_BASE + 7) 116 #define SPITZ_GPIO_ADC_TEMP_ON (SPITZ_SCP_GPIO_BASE + 8) 117 118 /* Spitz Scoop Device (No. 2) GPIOs */ 119 /* Suspend States in comments */ 120 #define SPITZ_SCP2_IR_ON SCOOP_GPCR_PA11 /* High */ 121 #define SPITZ_SCP2_AKIN_PULLUP SCOOP_GPCR_PA12 /* Keep */ 122 #define SPITZ_SCP2_RESERVED_1 SCOOP_GPCR_PA13 /* High */ 123 #define SPITZ_SCP2_RESERVED_2 SCOOP_GPCR_PA14 /* Low */ 124 #define SPITZ_SCP2_RESERVED_3 SCOOP_GPCR_PA15 /* Low */ 125 #define SPITZ_SCP2_RESERVED_4 SCOOP_GPCR_PA16 /* Low */ 126 #define SPITZ_SCP2_BACKLIGHT_CONT SCOOP_GPCR_PA17 /* Low */ 127 #define SPITZ_SCP2_BACKLIGHT_ON SCOOP_GPCR_PA18 /* Low */ 128 #define SPITZ_SCP2_MIC_BIAS SCOOP_GPCR_PA19 /* Low */ 129 130 #define SPITZ_SCP2_IO_DIR (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1 | \ 131 SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 132 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 133 134 #define SPITZ_SCP2_IO_OUT (SPITZ_SCP2_AKIN_PULLUP | SPITZ_SCP2_RESERVED_1) 135 #define SPITZ_SCP2_SUS_CLR (SPITZ_SCP2_RESERVED_2 | SPITZ_SCP2_RESERVED_3 | SPITZ_SCP2_RESERVED_4 | \ 136 SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS) 137 #define SPITZ_SCP2_SUS_SET (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1) 138 139 #define SPITZ_SCP2_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) 140 #define SPITZ_GPIO_IR_ON (SPITZ_SCP2_GPIO_BASE + 0) 141 #define SPITZ_GPIO_AKIN_PULLUP (SPITZ_SCP2_GPIO_BASE + 1) 142 #define SPITZ_GPIO_RESERVED_1 (SPITZ_SCP2_GPIO_BASE + 2) 143 #define SPITZ_GPIO_RESERVED_2 (SPITZ_SCP2_GPIO_BASE + 3) 144 #define SPITZ_GPIO_RESERVED_3 (SPITZ_SCP2_GPIO_BASE + 4) 145 #define SPITZ_GPIO_RESERVED_4 (SPITZ_SCP2_GPIO_BASE + 5) 146 #define SPITZ_GPIO_BACKLIGHT_CONT (SPITZ_SCP2_GPIO_BASE + 6) 147 #define SPITZ_GPIO_BACKLIGHT_ON (SPITZ_SCP2_GPIO_BASE + 7) 148 #define SPITZ_GPIO_MIC_BIAS (SPITZ_SCP2_GPIO_BASE + 8) 149 150 /* Akita IO Expander GPIOs */ 151 #define AKITA_IOEXP_GPIO_BASE (PXA_NR_BUILTIN_GPIO + 12) 152 #define AKITA_GPIO_RESERVED_0 (AKITA_IOEXP_GPIO_BASE + 0) 153 #define AKITA_GPIO_RESERVED_1 (AKITA_IOEXP_GPIO_BASE + 1) 154 #define AKITA_GPIO_MIC_BIAS (AKITA_IOEXP_GPIO_BASE + 2) 155 #define AKITA_GPIO_BACKLIGHT_ON (AKITA_IOEXP_GPIO_BASE + 3) 156 #define AKITA_GPIO_BACKLIGHT_CONT (AKITA_IOEXP_GPIO_BASE + 4) 157 #define AKITA_GPIO_AKIN_PULLUP (AKITA_IOEXP_GPIO_BASE + 5) 158 #define AKITA_GPIO_IR_ON (AKITA_IOEXP_GPIO_BASE + 6) 159 #define AKITA_GPIO_RESERVED_7 (AKITA_IOEXP_GPIO_BASE + 7) 160 161 /* Spitz IRQ Definitions */ 162 163 #define SPITZ_IRQ_GPIO_KEY_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT) 164 #define SPITZ_IRQ_GPIO_AC_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN) 165 #define SPITZ_IRQ_GPIO_AK_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT) 166 #define SPITZ_IRQ_GPIO_HP_IN PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN) 167 #define SPITZ_IRQ_GPIO_TP_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT) 168 #define SPITZ_IRQ_GPIO_SYNC PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC) 169 #define SPITZ_IRQ_GPIO_ON_KEY PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY) 170 #define SPITZ_IRQ_GPIO_SWA PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA) 171 #define SPITZ_IRQ_GPIO_SWB PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB) 172 #define SPITZ_IRQ_GPIO_BAT_COVER PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER) 173 #define SPITZ_IRQ_GPIO_FATAL_BAT PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT) 174 #define SPITZ_IRQ_GPIO_CO PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO) 175 #define SPITZ_IRQ_GPIO_CF_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ) 176 #define SPITZ_IRQ_GPIO_CF_CD PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD) 177 #define SPITZ_IRQ_GPIO_CF2_IRQ PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ) 178 #define SPITZ_IRQ_GPIO_nSD_INT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT) 179 #define SPITZ_IRQ_GPIO_nSD_DETECT PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT) 180 181 /* 182 * Shared data structures 183 */ 184 extern struct platform_device spitzssp_device; 185 extern struct sharpsl_charger_machinfo spitz_pm_machinfo; 186
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