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TOMOYO Linux Cross Reference
Linux/arch/arm/mach-s3c/map-s3c64xx.h

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  1 /* SPDX-License-Identifier: GPL-2.0 */
  2 /*
  3  * Copyright 2008 Openmoko, Inc.
  4  * Copyright 2008 Simtec Electronics
  5  *      http://armlinux.simtec.co.uk/
  6  *      Ben Dooks <ben@simtec.co.uk>
  7  *
  8  * S3C64XX - Memory map definitions
  9  */
 10 
 11 #ifndef __ASM_ARCH_MAP_H
 12 #define __ASM_ARCH_MAP_H __FILE__
 13 
 14 #include "map-base.h"
 15 #include "map-s3c.h"
 16 
 17 /*
 18  * Post-mux Chip Select Regions Xm0CSn_
 19  * These may be used by SROM, NAND or CF depending on settings
 20  */
 21 
 22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
 23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
 24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
 25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
 26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
 27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
 28 
 29 /* HSMMC units */
 30 #define S3C64XX_PA_HSMMC(x)     (0x7C200000 + ((x) * 0x100000))
 31 #define S3C64XX_PA_HSMMC0       S3C64XX_PA_HSMMC(0)
 32 #define S3C64XX_PA_HSMMC1       S3C64XX_PA_HSMMC(1)
 33 #define S3C64XX_PA_HSMMC2       S3C64XX_PA_HSMMC(2)
 34 
 35 #define S3C_PA_UART             (0x7F005000)
 36 #define S3C_PA_UART0            (S3C_PA_UART + 0x00)
 37 #define S3C_PA_UART1            (S3C_PA_UART + 0x400)
 38 #define S3C_PA_UART2            (S3C_PA_UART + 0x800)
 39 #define S3C_PA_UART3            (S3C_PA_UART + 0xC00)
 40 #define S3C_UART_OFFSET         (0x400)
 41 
 42 /* See notes on UART VA mapping in debug-macro.S */
 43 #define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
 44 
 45 #define S3C_VA_UART0            S3C_VA_UARTx(0)
 46 #define S3C_VA_UART1            S3C_VA_UARTx(1)
 47 #define S3C_VA_UART2            S3C_VA_UARTx(2)
 48 #define S3C_VA_UART3            S3C_VA_UARTx(3)
 49 
 50 #define S3C64XX_PA_SROM         (0x70000000)
 51 
 52 #define S3C64XX_PA_ONENAND0     (0x70100000)
 53 #define S3C64XX_PA_ONENAND0_BUF (0x20000000)
 54 #define S3C64XX_SZ_ONENAND0_BUF (SZ_64M)
 55 
 56 /* NAND and OneNAND1 controllers occupy the same register region
 57    (depending on SoC POP version) */
 58 #define S3C64XX_PA_ONENAND1     (0x70200000)
 59 #define S3C64XX_PA_ONENAND1_BUF (0x28000000)
 60 #define S3C64XX_SZ_ONENAND1_BUF (SZ_64M)
 61 
 62 #define S3C64XX_PA_NAND         (0x70200000)
 63 #define S3C64XX_PA_FB           (0x77100000)
 64 #define S3C64XX_PA_USB_HSOTG    (0x7C000000)
 65 #define S3C64XX_PA_WATCHDOG     (0x7E004000)
 66 #define S3C64XX_PA_RTC          (0x7E005000)
 67 #define S3C64XX_PA_KEYPAD       (0x7E00A000)
 68 #define S3C64XX_PA_ADC          (0x7E00B000)
 69 #define S3C64XX_PA_SYSCON       (0x7E00F000)
 70 #define S3C64XX_PA_AC97         (0x7F001000)
 71 #define S3C64XX_PA_IIS0         (0x7F002000)
 72 #define S3C64XX_PA_IIS1         (0x7F003000)
 73 #define S3C64XX_PA_TIMER        (0x7F006000)
 74 #define S3C64XX_PA_IIC0         (0x7F004000)
 75 #define S3C64XX_PA_SPI0         (0x7F00B000)
 76 #define S3C64XX_PA_SPI1         (0x7F00C000)
 77 #define S3C64XX_PA_PCM0         (0x7F009000)
 78 #define S3C64XX_PA_PCM1         (0x7F00A000)
 79 #define S3C64XX_PA_IISV4        (0x7F00D000)
 80 #define S3C64XX_PA_IIC1         (0x7F00F000)
 81 
 82 #define S3C64XX_PA_GPIO         (0x7F008000)
 83 #define S3C64XX_SZ_GPIO         SZ_4K
 84 
 85 #define S3C64XX_PA_SDRAM        (0x50000000)
 86 
 87 #define S3C64XX_PA_CFCON        (0x70300000)
 88 
 89 #define S3C64XX_PA_VIC0         (0x71200000)
 90 #define S3C64XX_PA_VIC1         (0x71300000)
 91 
 92 #define S3C64XX_PA_MODEM        (0x74108000)
 93 
 94 #define S3C64XX_PA_USBHOST      (0x74300000)
 95 
 96 #define S3C64XX_PA_USB_HSPHY    (0x7C100000)
 97 
 98 /* compatibility defines. */
 99 #define S3C_PA_TIMER            S3C64XX_PA_TIMER
100 #define S3C_PA_HSMMC0           S3C64XX_PA_HSMMC0
101 #define S3C_PA_HSMMC1           S3C64XX_PA_HSMMC1
102 #define S3C_PA_HSMMC2           S3C64XX_PA_HSMMC2
103 #define S3C_PA_IIC              S3C64XX_PA_IIC0
104 #define S3C_PA_IIC1             S3C64XX_PA_IIC1
105 #define S3C_PA_NAND             S3C64XX_PA_NAND
106 #define S3C_PA_ONENAND          S3C64XX_PA_ONENAND0
107 #define S3C_PA_ONENAND_BUF      S3C64XX_PA_ONENAND0_BUF
108 #define S3C_SZ_ONENAND_BUF      S3C64XX_SZ_ONENAND0_BUF
109 #define S3C_PA_FB               S3C64XX_PA_FB
110 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
111 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
112 #define S3C_PA_RTC              S3C64XX_PA_RTC
113 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
114 #define S3C_PA_SPI0             S3C64XX_PA_SPI0
115 #define S3C_PA_SPI1             S3C64XX_PA_SPI1
116 
117 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
118 #define SAMSUNG_PA_CFCON        S3C64XX_PA_CFCON
119 #define SAMSUNG_PA_KEYPAD       S3C64XX_PA_KEYPAD
120 #define SAMSUNG_PA_TIMER        S3C64XX_PA_TIMER
121 
122 #endif /* __ASM_ARCH_6400_MAP_H */
123 

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