1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2008 Openmoko, Inc. 4 * Copyright 2008 Simtec Electronics 5 * http://armlinux.simtec.co.uk/ 6 * Ben Dooks <ben@simtec.co.uk> 7 * 8 * S3C - USB2.0 Highspeed/OtG device PHY registers 9 */ 10 11 /* Note, this is a separate header file as some of the clock framework 12 * needs to touch this if the clk_48m is used as the USB OHCI or other 13 * peripheral source. 14 */ 15 16 #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H 17 #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ 18 19 /* S3C64XX_PA_USB_HSPHY */ 20 21 #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 22 23 #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 24 #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 25 #define S3C_PHYPWR_OTG_DISABLE (1 << 4) 26 #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 27 #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 28 29 #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) 30 #define S3C_PHYCLK_MODE_USB11 (1 << 6) 31 #define S3C_PHYCLK_EXT_OSC (1 << 5) 32 #define S3C_PHYCLK_CLK_FORCE (1 << 4) 33 #define S3C_PHYCLK_ID_PULL (1 << 2) 34 #define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) 35 #define S3C_PHYCLK_CLKSEL_SHIFT (0) 36 #define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) 37 #define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) 38 #define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) 39 40 #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 41 #define S3C_RSTCON_PHYCLK (1 << 2) 42 #define S3C_RSTCON_HCLK (1 << 1) 43 #define S3C_RSTCON_PHY (1 << 0) 44 45 #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) 46 47 #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ 48
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