1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * This file contains the hardware definitions of the Integrator. 4 * 5 * Copyright (C) 1998-1999 ARM Limited. 6 */ 7 #ifndef INTEGRATOR_HARDWARE_H 8 #define INTEGRATOR_HARDWARE_H 9 10 /* 11 * Where in virtual memory the IO devices (timers, system controllers 12 * and so on) 13 */ 14 #define IO_BASE 0xF0000000 // VA of IO 15 #define IO_SIZE 0x0B000000 // How much? 16 #define IO_START INTEGRATOR_HDR_BASE // PA of IO 17 18 /* macro to get at IO space when running virtually */ 19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) 20 #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) 21 22 /* 23 * Integrator memory map 24 */ 25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000 26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000 27 #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ 28 #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K 29 30 /* 31 * New Core Modules have different amounts of SSRAM, the amount of SSRAM 32 * fitted can be found in HDR_STAT. 33 * 34 * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to 35 * the minimum amount of SSRAM fitted on any core module. 36 * 37 * New Core Modules also alias the SSRAM. 38 * 39 */ 40 #define INTEGRATOR_SSRAM_BASE 0x00000000 41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 42 #define INTEGRATOR_SSRAM_SIZE SZ_256K 43 44 #define INTEGRATOR_FLASH_BASE 0x24000000 45 #define INTEGRATOR_FLASH_SIZE SZ_32M 46 47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 48 #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K 49 50 /* 51 * SDRAM is a SIMM therefore the size is not known. 52 */ 53 #define INTEGRATOR_SDRAM_BASE 0x00040000 54 55 #define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000 56 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 57 #define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000 58 #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 59 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 60 61 /* 62 * Logic expansion modules 63 * 64 */ 65 #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 66 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 67 #define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000 68 #define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000 69 #define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000 70 71 /* 72 * Integrator header card registers 73 */ 74 #define INTEGRATOR_HDR_ID_OFFSET 0x00 75 #define INTEGRATOR_HDR_PROC_OFFSET 0x04 76 #define INTEGRATOR_HDR_OSC_OFFSET 0x08 77 #define INTEGRATOR_HDR_CTRL_OFFSET 0x0C 78 #define INTEGRATOR_HDR_STAT_OFFSET 0x10 79 #define INTEGRATOR_HDR_LOCK_OFFSET 0x14 80 #define INTEGRATOR_HDR_SDRAM_OFFSET 0x20 81 #define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */ 82 #define INTEGRATOR_HDR_IC_OFFSET 0x40 83 #define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100 84 #define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200 85 86 #define INTEGRATOR_HDR_BASE 0x10000000 87 #define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET) 88 #define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET) 89 #define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET) 90 #define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET) 91 #define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET) 92 #define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET) 93 #define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET) 94 #define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET) 95 #define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET) 96 #define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET) 97 #define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET) 98 99 #define INTEGRATOR_HDR_CTRL_LED 0x01 100 #define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02 101 #define INTEGRATOR_HDR_CTRL_REMAP 0x04 102 #define INTEGRATOR_HDR_CTRL_RESET 0x08 103 #define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10 104 #define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20 105 #define INTEGRATOR_HDR_CTRL_FASTBUS 0x40 106 #define INTEGRATOR_HDR_CTRL_SYNC 0x80 107 108 #define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102 109 #define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107 110 #define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C 111 #define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111 112 #define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116 113 #define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B 114 #define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120 115 #define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125 116 #define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A 117 #define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F 118 #define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134 119 #define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139 120 #define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E 121 #define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143 122 #define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148 123 #define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D 124 #define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152 125 #define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157 126 #define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C 127 #define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161 128 #define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166 129 #define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B 130 #define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170 131 #define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175 132 #define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A 133 #define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F 134 #define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184 135 #define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189 136 #define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E 137 #define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193 138 #define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198 139 #define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF 140 141 #define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000 142 #define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000 143 #define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000 144 #define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000 145 #define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000 146 #define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000 147 #define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000 148 #define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000 149 #define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000 150 #define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000 151 #define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000 152 153 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0 154 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000 155 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000 156 #define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000 157 #define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000 158 159 #define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5) 160 161 /* 162 * Integrator system registers 163 */ 164 165 /* 166 * System Controller 167 */ 168 #define INTEGRATOR_SC_ID_OFFSET 0x00 169 #define INTEGRATOR_SC_OSC_OFFSET 0x04 170 #define INTEGRATOR_SC_CTRLS_OFFSET 0x08 171 #define INTEGRATOR_SC_CTRLC_OFFSET 0x0C 172 #define INTEGRATOR_SC_DEC_OFFSET 0x10 173 #define INTEGRATOR_SC_ARB_OFFSET 0x14 174 #define INTEGRATOR_SC_LOCK_OFFSET 0x1C 175 176 #define INTEGRATOR_SC_BASE 0x11000000 177 #define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET) 178 #define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET) 179 #define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET) 180 #define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET) 181 #define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET) 182 #define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET) 183 #define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) 184 #define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET) 185 186 #define INTEGRATOR_SC_OSC_SYS_10MHz 0x20 187 #define INTEGRATOR_SC_OSC_SYS_15MHz 0x34 188 #define INTEGRATOR_SC_OSC_SYS_20MHz 0x48 189 #define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C 190 #define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C 191 #define INTEGRATOR_SC_OSC_SYS_MASK 0xFF 192 193 #define INTEGRATOR_SC_OSC_PCI_25MHz 0x100 194 #define INTEGRATOR_SC_OSC_PCI_33MHz 0x0 195 #define INTEGRATOR_SC_OSC_PCI_MASK 0x100 196 197 #define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0) 198 #define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1) 199 #define INTEGRATOR_SC_CTRL_nFLWP (1 << 2) 200 #define INTEGRATOR_SC_CTRL_URTS0 (1 << 4) 201 #define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5) 202 #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) 203 #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) 204 205 /* 206 * External Bus Interface 207 */ 208 #define INTEGRATOR_EBI_BASE 0x12000000 209 210 #define INTEGRATOR_EBI_CSR0_OFFSET 0x00 211 #define INTEGRATOR_EBI_CSR1_OFFSET 0x04 212 #define INTEGRATOR_EBI_CSR2_OFFSET 0x08 213 #define INTEGRATOR_EBI_CSR3_OFFSET 0x0C 214 #define INTEGRATOR_EBI_LOCK_OFFSET 0x20 215 216 #define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET) 217 #define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 218 #define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET) 219 #define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET) 220 #define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 221 222 #define INTEGRATOR_EBI_8_BIT 0x00 223 #define INTEGRATOR_EBI_16_BIT 0x01 224 #define INTEGRATOR_EBI_32_BIT 0x02 225 #define INTEGRATOR_EBI_WRITE_ENABLE 0x04 226 #define INTEGRATOR_EBI_SYNC 0x08 227 #define INTEGRATOR_EBI_WS_2 0x00 228 #define INTEGRATOR_EBI_WS_3 0x10 229 #define INTEGRATOR_EBI_WS_4 0x20 230 #define INTEGRATOR_EBI_WS_5 0x30 231 #define INTEGRATOR_EBI_WS_6 0x40 232 #define INTEGRATOR_EBI_WS_7 0x50 233 #define INTEGRATOR_EBI_WS_8 0x60 234 #define INTEGRATOR_EBI_WS_9 0x70 235 #define INTEGRATOR_EBI_WS_10 0x80 236 #define INTEGRATOR_EBI_WS_11 0x90 237 #define INTEGRATOR_EBI_WS_12 0xA0 238 #define INTEGRATOR_EBI_WS_13 0xB0 239 #define INTEGRATOR_EBI_WS_14 0xC0 240 #define INTEGRATOR_EBI_WS_15 0xD0 241 #define INTEGRATOR_EBI_WS_16 0xE0 242 #define INTEGRATOR_EBI_WS_17 0xF0 243 244 245 #define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */ 246 #define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */ 247 #define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */ 248 #define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */ 249 #define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */ 250 #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ 251 #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ 252 253 /* 254 * LED's & Switches 255 */ 256 #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 257 #define INTEGRATOR_DBG_LEDS_OFFSET 0x04 258 #define INTEGRATOR_DBG_SWITCH_OFFSET 0x08 259 260 #define INTEGRATOR_DBG_BASE 0x1A000000 261 #define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET) 262 #define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) 263 #define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) 264 265 #define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */ 266 267 #define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */ 268 #define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */ 269 #define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */ 270 #define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */ 271 #define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */ 272 #define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */ 273 274 /* PS2 Keyboard interface */ 275 #define KMI0_BASE INTEGRATOR_KBD_BASE 276 277 /* PS2 Mouse interface */ 278 #define KMI1_BASE INTEGRATOR_MOUSE_BASE 279 280 /* 281 * Integrator Interrupt Controllers 282 * 283 * 284 * Offsets from interrupt controller base 285 * 286 * System Controller interrupt controller base is 287 * 288 * INTEGRATOR_IC_BASE + (header_number << 6) 289 * 290 * Core Module interrupt controller base is 291 * 292 * INTEGRATOR_HDR_IC 293 */ 294 #define IRQ_STATUS 0 295 #define IRQ_RAW_STATUS 0x04 296 #define IRQ_ENABLE 0x08 297 #define IRQ_ENABLE_SET 0x08 298 #define IRQ_ENABLE_CLEAR 0x0C 299 300 #define INT_SOFT_SET 0x10 301 #define INT_SOFT_CLEAR 0x14 302 303 #define FIQ_STATUS 0x20 304 #define FIQ_RAW_STATUS 0x24 305 #define FIQ_ENABLE 0x28 306 #define FIQ_ENABLE_SET 0x28 307 #define FIQ_ENABLE_CLEAR 0x2C 308 309 310 /* 311 * LED's 312 */ 313 #define GREEN_LED 0x01 314 #define YELLOW_LED 0x02 315 #define RED_LED 0x04 316 #define GREEN_LED_2 0x08 317 #define ALL_LEDS 0x0F 318 319 #define LED_BANK INTEGRATOR_DBG_LEDS 320 321 /* 322 * Timer definitions 323 * 324 * Only use timer 1 & 2 325 * (both run at 24MHz and will need the clock divider set to 16). 326 * 327 * Timer 0 runs at bus frequency 328 */ 329 #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 330 #define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 331 #define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 332 333 #define INTEGRATOR_CSR_BASE 0x10000000 334 #define INTEGRATOR_CSR_SIZE 0x10000000 335 336 #endif /* INTEGRATOR_HARDWARE_H */ 337
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