1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
4 *
5 * Copyright (C) 2000 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 *
9 * These are the low level assembler for performing cache and TLB
10 * functions on the ARM1026EJ-S.
11 */
12 #include <linux/linkage.h>
13 #include <linux/init.h>
14 #include <linux/cfi_types.h>
15 #include <linux/pgtable.h>
16 #include <asm/assembler.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/hwcap.h>
19 #include <asm/pgtable-hwdef.h>
20 #include <asm/ptrace.h>
21
22 #include "proc-macros.S"
23
24 /*
25 * This is the maximum size of an area which will be invalidated
26 * using the single invalidate entry instructions. Anything larger
27 * than this, and we go for the whole cache.
28 *
29 * This value should be chosen such that we choose the cheapest
30 * alternative.
31 */
32 #define MAX_AREA_SIZE 32768
33
34 /*
35 * The size of one data cache line.
36 */
37 #define CACHE_DLINESIZE 32
38
39 /*
40 * The number of data cache segments.
41 */
42 #define CACHE_DSEGMENTS 16
43
44 /*
45 * The number of lines in a cache segment.
46 */
47 #define CACHE_DENTRIES 64
48
49 /*
50 * This is the size at which it becomes more efficient to
51 * clean the whole cache, rather than using the individual
52 * cache line maintenance instructions.
53 */
54 #define CACHE_DLIMIT 32768
55
56 .text
57 /*
58 * cpu_arm1026_proc_init()
59 */
60 SYM_TYPED_FUNC_START(cpu_arm1026_proc_init)
61 ret lr
62 SYM_FUNC_END(cpu_arm1026_proc_init)
63
64 /*
65 * cpu_arm1026_proc_fin()
66 */
67 SYM_TYPED_FUNC_START(cpu_arm1026_proc_fin)
68 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
69 bic r0, r0, #0x1000 @ ...i............
70 bic r0, r0, #0x000e @ ............wca.
71 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ret lr
73 SYM_FUNC_END(cpu_arm1026_proc_fin)
74
75 /*
76 * cpu_arm1026_reset(loc)
77 *
78 * Perform a soft reset of the system. Put the CPU into the
79 * same state as it would be if it had been reset, and branch
80 * to what would be the reset vector.
81 *
82 * loc: location to jump to for soft reset
83 */
84 .align 5
85 .pushsection .idmap.text, "ax"
86 SYM_TYPED_FUNC_START(cpu_arm1026_reset)
87 mov ip, #0
88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
89 mcr p15, 0, ip, c7, c10, 4 @ drain WB
90 #ifdef CONFIG_MMU
91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
92 #endif
93 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
94 bic ip, ip, #0x000f @ ............wcam
95 bic ip, ip, #0x1100 @ ...i...s........
96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
97 ret r0
98 SYM_FUNC_END(cpu_arm1026_reset)
99 .popsection
100
101 /*
102 * cpu_arm1026_do_idle()
103 */
104 .align 5
105 SYM_TYPED_FUNC_START(cpu_arm1026_do_idle)
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
107 ret lr
108 SYM_FUNC_END(cpu_arm1026_do_idle)
109
110 /* ================================= CACHE ================================ */
111
112 .align 5
113
114 /*
115 * flush_icache_all()
116 *
117 * Unconditionally clean and invalidate the entire icache.
118 */
119 SYM_TYPED_FUNC_START(arm1026_flush_icache_all)
120 #ifndef CONFIG_CPU_ICACHE_DISABLE
121 mov r0, #0
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123 #endif
124 ret lr
125 SYM_FUNC_END(arm1026_flush_icache_all)
126
127 /*
128 * flush_user_cache_all()
129 *
130 * Invalidate all cache entries in a particular address
131 * space.
132 */
133 SYM_FUNC_ALIAS(arm1026_flush_user_cache_all, arm1026_flush_kern_cache_all)
134
135 /*
136 * flush_kern_cache_all()
137 *
138 * Clean and invalidate the entire cache.
139 */
140 SYM_TYPED_FUNC_START(arm1026_flush_kern_cache_all)
141 mov r2, #VM_EXEC
142 mov ip, #0
143 __flush_whole_cache:
144 #ifndef CONFIG_CPU_DCACHE_DISABLE
145 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
146 bne 1b
147 #endif
148 tst r2, #VM_EXEC
149 #ifndef CONFIG_CPU_ICACHE_DISABLE
150 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
151 #endif
152 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
153 ret lr
154 SYM_FUNC_END(arm1026_flush_kern_cache_all)
155
156 /*
157 * flush_user_cache_range(start, end, flags)
158 *
159 * Invalidate a range of cache entries in the specified
160 * address space.
161 *
162 * - start - start address (inclusive)
163 * - end - end address (exclusive)
164 * - flags - vm_flags for this space
165 */
166 SYM_TYPED_FUNC_START(arm1026_flush_user_cache_range)
167 mov ip, #0
168 sub r3, r1, r0 @ calculate total size
169 cmp r3, #CACHE_DLIMIT
170 bhs __flush_whole_cache
171
172 #ifndef CONFIG_CPU_DCACHE_DISABLE
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 add r0, r0, #CACHE_DLINESIZE
175 cmp r0, r1
176 blo 1b
177 #endif
178 tst r2, #VM_EXEC
179 #ifndef CONFIG_CPU_ICACHE_DISABLE
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 #endif
182 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
183 ret lr
184 SYM_FUNC_END(arm1026_flush_user_cache_range)
185
186 /*
187 * coherent_kern_range(start, end)
188 *
189 * Ensure coherency between the Icache and the Dcache in the
190 * region described by start. If you have non-snooping
191 * Harvard caches, you need to implement this function.
192 *
193 * - start - virtual start address
194 * - end - virtual end address
195 */
196 SYM_TYPED_FUNC_START(arm1026_coherent_kern_range)
197 #ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
198 b arm1026_coherent_user_range
199 #endif
200 SYM_FUNC_END(arm1026_coherent_kern_range)
201
202 /*
203 * coherent_user_range(start, end)
204 *
205 * Ensure coherency between the Icache and the Dcache in the
206 * region described by start. If you have non-snooping
207 * Harvard caches, you need to implement this function.
208 *
209 * - start - virtual start address
210 * - end - virtual end address
211 */
212 SYM_TYPED_FUNC_START(arm1026_coherent_user_range)
213 mov ip, #0
214 bic r0, r0, #CACHE_DLINESIZE - 1
215 1:
216 #ifndef CONFIG_CPU_DCACHE_DISABLE
217 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
218 #endif
219 #ifndef CONFIG_CPU_ICACHE_DISABLE
220 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 #endif
222 add r0, r0, #CACHE_DLINESIZE
223 cmp r0, r1
224 blo 1b
225 mcr p15, 0, ip, c7, c10, 4 @ drain WB
226 mov r0, #0
227 ret lr
228 SYM_FUNC_END(arm1026_coherent_user_range)
229
230 /*
231 * flush_kern_dcache_area(void *addr, size_t size)
232 *
233 * Ensure no D cache aliasing occurs, either with itself or
234 * the I cache
235 *
236 * - addr - kernel address
237 * - size - region size
238 */
239 SYM_TYPED_FUNC_START(arm1026_flush_kern_dcache_area)
240 mov ip, #0
241 #ifndef CONFIG_CPU_DCACHE_DISABLE
242 add r1, r0, r1
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
244 add r0, r0, #CACHE_DLINESIZE
245 cmp r0, r1
246 blo 1b
247 #endif
248 mcr p15, 0, ip, c7, c10, 4 @ drain WB
249 ret lr
250 SYM_FUNC_END(arm1026_flush_kern_dcache_area)
251
252 /*
253 * dma_inv_range(start, end)
254 *
255 * Invalidate (discard) the specified virtual address range.
256 * May not write back any entries. If 'start' or 'end'
257 * are not cache line aligned, those lines must be written
258 * back.
259 *
260 * - start - virtual start address
261 * - end - virtual end address
262 *
263 * (same as v4wb)
264 */
265 arm1026_dma_inv_range:
266 mov ip, #0
267 #ifndef CONFIG_CPU_DCACHE_DISABLE
268 tst r0, #CACHE_DLINESIZE - 1
269 bic r0, r0, #CACHE_DLINESIZE - 1
270 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
271 tst r1, #CACHE_DLINESIZE - 1
272 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
273 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
274 add r0, r0, #CACHE_DLINESIZE
275 cmp r0, r1
276 blo 1b
277 #endif
278 mcr p15, 0, ip, c7, c10, 4 @ drain WB
279 ret lr
280
281 /*
282 * dma_clean_range(start, end)
283 *
284 * Clean the specified virtual address range.
285 *
286 * - start - virtual start address
287 * - end - virtual end address
288 *
289 * (same as v4wb)
290 */
291 arm1026_dma_clean_range:
292 mov ip, #0
293 #ifndef CONFIG_CPU_DCACHE_DISABLE
294 bic r0, r0, #CACHE_DLINESIZE - 1
295 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
296 add r0, r0, #CACHE_DLINESIZE
297 cmp r0, r1
298 blo 1b
299 #endif
300 mcr p15, 0, ip, c7, c10, 4 @ drain WB
301 ret lr
302
303 /*
304 * dma_flush_range(start, end)
305 *
306 * Clean and invalidate the specified virtual address range.
307 *
308 * - start - virtual start address
309 * - end - virtual end address
310 */
311 SYM_TYPED_FUNC_START(arm1026_dma_flush_range)
312 mov ip, #0
313 #ifndef CONFIG_CPU_DCACHE_DISABLE
314 bic r0, r0, #CACHE_DLINESIZE - 1
315 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
316 add r0, r0, #CACHE_DLINESIZE
317 cmp r0, r1
318 blo 1b
319 #endif
320 mcr p15, 0, ip, c7, c10, 4 @ drain WB
321 ret lr
322 SYM_FUNC_END(arm1026_dma_flush_range)
323
324 /*
325 * dma_map_area(start, size, dir)
326 * - start - kernel virtual start address
327 * - size - size of region
328 * - dir - DMA direction
329 */
330 SYM_TYPED_FUNC_START(arm1026_dma_map_area)
331 add r1, r1, r0
332 cmp r2, #DMA_TO_DEVICE
333 beq arm1026_dma_clean_range
334 bcs arm1026_dma_inv_range
335 b arm1026_dma_flush_range
336 SYM_FUNC_END(arm1026_dma_map_area)
337
338 /*
339 * dma_unmap_area(start, size, dir)
340 * - start - kernel virtual start address
341 * - size - size of region
342 * - dir - DMA direction
343 */
344 SYM_TYPED_FUNC_START(arm1026_dma_unmap_area)
345 ret lr
346 SYM_FUNC_END(arm1026_dma_unmap_area)
347
348 .align 5
349 SYM_TYPED_FUNC_START(cpu_arm1026_dcache_clean_area)
350 #ifndef CONFIG_CPU_DCACHE_DISABLE
351 mov ip, #0
352 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
355 bhi 1b
356 #endif
357 ret lr
358 SYM_FUNC_END(cpu_arm1026_dcache_clean_area)
359
360 /* =============================== PageTable ============================== */
361
362 /*
363 * cpu_arm1026_switch_mm(pgd)
364 *
365 * Set the translation base pointer to be as described by pgd.
366 *
367 * pgd: new page tables
368 */
369 .align 5
370 SYM_TYPED_FUNC_START(cpu_arm1026_switch_mm)
371 #ifdef CONFIG_MMU
372 mov r1, #0
373 #ifndef CONFIG_CPU_DCACHE_DISABLE
374 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
375 bne 1b
376 #endif
377 #ifndef CONFIG_CPU_ICACHE_DISABLE
378 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
379 #endif
380 mcr p15, 0, r1, c7, c10, 4 @ drain WB
381 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
382 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
383 #endif
384 ret lr
385 SYM_FUNC_END(cpu_arm1026_switch_mm)
386
387 /*
388 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
389 *
390 * Set a PTE and flush it out
391 */
392 .align 5
393 SYM_TYPED_FUNC_START(cpu_arm1026_set_pte_ext)
394 #ifdef CONFIG_MMU
395 armv3_set_pte_ext
396 mov r0, r0
397 #ifndef CONFIG_CPU_DCACHE_DISABLE
398 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399 #endif
400 #endif /* CONFIG_MMU */
401 ret lr
402 SYM_FUNC_END(cpu_arm1026_set_pte_ext)
403
404 .type __arm1026_setup, #function
405 __arm1026_setup:
406 mov r0, #0
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
408 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
409 #ifdef CONFIG_MMU
410 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
411 mcr p15, 0, r4, c2, c0 @ load page table pointer
412 #endif
413 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
414 mov r0, #4 @ explicitly disable writeback
415 mcr p15, 7, r0, c15, c0, 0
416 #endif
417 adr r5, arm1026_crval
418 ldmia r5, {r5, r6}
419 mrc p15, 0, r0, c1, c0 @ get control register v4
420 bic r0, r0, r5
421 orr r0, r0, r6
422 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
423 orr r0, r0, #0x4000 @ .R.. .... .... ....
424 #endif
425 ret lr
426 .size __arm1026_setup, . - __arm1026_setup
427
428 /*
429 * R
430 * .RVI ZFRS BLDP WCAM
431 * .011 1001 ..11 0101
432 *
433 */
434 .type arm1026_crval, #object
435 arm1026_crval:
436 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
437
438 __INITDATA
439 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
440 define_processor_functions arm1026, dabort=v5t_early_abort, pabort=legacy_pabort
441
442 .section .rodata
443
444 string cpu_arch_name, "armv5tej"
445 string cpu_elf_name, "v5"
446 .align
447 string cpu_arm1026_name, "ARM1026EJ-S"
448 .align
449
450 .section ".proc.info.init", "a"
451
452 .type __arm1026_proc_info,#object
453 __arm1026_proc_info:
454 .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
455 .long 0xff0ffff0
456 .long PMD_TYPE_SECT | \
457 PMD_BIT4 | \
458 PMD_SECT_AP_WRITE | \
459 PMD_SECT_AP_READ
460 .long PMD_TYPE_SECT | \
461 PMD_BIT4 | \
462 PMD_SECT_AP_WRITE | \
463 PMD_SECT_AP_READ
464 initfn __arm1026_setup, __arm1026_proc_info
465 .long cpu_arch_name
466 .long cpu_elf_name
467 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
468 .long cpu_arm1026_name
469 .long arm1026_processor_functions
470 .long v4wbi_tlb_fns
471 .long v4wb_user_fns
472 .long arm1026_cache_fns
473 .size __arm1026_proc_info, . - __arm1026_proc_info
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