1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * linux/arch/arm/mm/proc-v6.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Modified by Catalin Marinas for noMMU support
7 *
8 * This is the "shell" of the ARMv6 processor support.
9 */
10 #include <linux/init.h>
11 #include <linux/cfi_types.h>
12 #include <linux/linkage.h>
13 #include <linux/pgtable.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18
19 #include "proc-macros.S"
20
21 #define D_CACHE_LINE_SIZE 32
22
23 #define TTB_C (1 << 0)
24 #define TTB_S (1 << 1)
25 #define TTB_IMP (1 << 2)
26 #define TTB_RGN_NC (0 << 3)
27 #define TTB_RGN_WBWA (1 << 3)
28 #define TTB_RGN_WT (2 << 3)
29 #define TTB_RGN_WB (3 << 3)
30
31 #define TTB_FLAGS_UP TTB_RGN_WBWA
32 #define PMD_FLAGS_UP PMD_SECT_WB
33 #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
34 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
35
36 .arch armv6
37
38 SYM_TYPED_FUNC_START(cpu_v6_proc_init)
39 ret lr
40 SYM_FUNC_END(cpu_v6_proc_init)
41
42 SYM_TYPED_FUNC_START(cpu_v6_proc_fin)
43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x1000 @ ...i............
45 bic r0, r0, #0x0006 @ .............ca.
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
47 ret lr
48 SYM_FUNC_END(cpu_v6_proc_fin)
49
50 /*
51 * cpu_v6_reset(loc)
52 *
53 * Perform a soft reset of the system. Put the CPU into the
54 * same state as it would be if it had been reset, and branch
55 * to what would be the reset vector.
56 *
57 * - loc - location to jump to for soft reset
58 */
59 .align 5
60 .pushsection .idmap.text, "ax"
61 SYM_TYPED_FUNC_START(cpu_v6_reset)
62 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
63 bic r1, r1, #0x1 @ ...............m
64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
65 mov r1, #0
66 mcr p15, 0, r1, c7, c5, 4 @ ISB
67 ret r0
68 SYM_FUNC_END(cpu_v6_reset)
69 .popsection
70
71 /*
72 * cpu_v6_do_idle()
73 *
74 * Idle the processor (eg, wait for interrupt).
75 *
76 * IRQs are already disabled.
77 */
78 SYM_TYPED_FUNC_START(cpu_v6_do_idle)
79 mov r1, #0
80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
82 ret lr
83 SYM_FUNC_END(cpu_v6_do_idle)
84
85 SYM_TYPED_FUNC_START(cpu_v6_dcache_clean_area)
86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 add r0, r0, #D_CACHE_LINE_SIZE
88 subs r1, r1, #D_CACHE_LINE_SIZE
89 bhi 1b
90 ret lr
91 SYM_FUNC_END(cpu_v6_dcache_clean_area)
92
93 /*
94 * cpu_v6_switch_mm(pgd_phys, tsk)
95 *
96 * Set the translation table base pointer to be pgd_phys
97 *
98 * - pgd_phys - physical address of new TTB
99 *
100 * It is assumed that:
101 * - we are not using split page tables
102 */
103 SYM_TYPED_FUNC_START(cpu_v6_switch_mm)
104 #ifdef CONFIG_MMU
105 mov r2, #0
106 mmid r1, r1 @ get mm->context.id
107 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
108 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
112 #ifdef CONFIG_PID_IN_CONTEXTIDR
113 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
114 bic r2, r2, #0xff @ extract the PID
115 and r1, r1, #0xff
116 orr r1, r1, r2 @ insert into new context ID
117 #endif
118 mcr p15, 0, r1, c13, c0, 1 @ set context ID
119 #endif
120 ret lr
121 SYM_FUNC_END(cpu_v6_switch_mm)
122
123 /*
124 * cpu_v6_set_pte_ext(ptep, pte, ext)
125 *
126 * Set a level 2 translation table entry.
127 *
128 * - ptep - pointer to level 2 translation table entry
129 * (hardware version is stored at -1024 bytes)
130 * - pte - PTE value to store
131 * - ext - value for extended PTE bits
132 */
133 armv6_mt_table cpu_v6
134
135 SYM_TYPED_FUNC_START(cpu_v6_set_pte_ext)
136 #ifdef CONFIG_MMU
137 armv6_set_pte_ext cpu_v6
138 #endif
139 ret lr
140 SYM_FUNC_END(cpu_v6_set_pte_ext)
141
142 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
143 .globl cpu_v6_suspend_size
144 .equ cpu_v6_suspend_size, 4 * 6
145 #ifdef CONFIG_ARM_CPU_SUSPEND
146 SYM_TYPED_FUNC_START(cpu_v6_do_suspend)
147 stmfd sp!, {r4 - r9, lr}
148 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
149 #ifdef CONFIG_MMU
150 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
151 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
152 #endif
153 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
154 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
155 mrc p15, 0, r9, c1, c0, 0 @ control register
156 stmia r0, {r4 - r9}
157 ldmfd sp!, {r4- r9, pc}
158 SYM_FUNC_END(cpu_v6_do_suspend)
159
160 SYM_TYPED_FUNC_START(cpu_v6_do_resume)
161 mov ip, #0
162 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
163 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
164 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
165 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
166 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
167 ldmia r0, {r4 - r9}
168 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
169 #ifdef CONFIG_MMU
170 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
171 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
172 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
173 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
174 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
175 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
176 #endif
177 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
178 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
179 mcr p15, 0, ip, c7, c5, 4 @ ISB
180 mov r0, r9 @ control register
181 b cpu_resume_mmu
182 SYM_FUNC_END(cpu_v6_do_resume)
183 #endif
184
185 string cpu_v6_name, "ARMv6-compatible processor"
186
187 .align
188
189 /*
190 * __v6_setup
191 *
192 * Initialise TLB, Caches, and MMU state ready to switch the MMU
193 * on. Return in r0 the new CP15 C1 control register setting.
194 *
195 * We automatically detect if we have a Harvard cache, and use the
196 * Harvard cache control instructions insead of the unified cache
197 * control instructions.
198 *
199 * This should be able to cover all ARMv6 cores.
200 *
201 * It is assumed that:
202 * - cache type register is implemented
203 */
204 __v6_setup:
205 #ifdef CONFIG_SMP
206 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
207 ALT_UP(nop)
208 orr r0, r0, #0x20
209 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
210 ALT_UP(nop)
211 #endif
212
213 mov r0, #0
214 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
217 #ifdef CONFIG_MMU
218 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
219 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
220 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
221 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
222 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
223 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
224 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
225 #endif /* CONFIG_MMU */
226 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
227 @ complete invalidations
228 adr r5, v6_crval
229 ldmia r5, {r5, r6}
230 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
231 mrc p15, 0, r0, c1, c0, 0 @ read control register
232 bic r0, r0, r5 @ clear bits them
233 orr r0, r0, r6 @ set them
234 #ifdef CONFIG_ARM_ERRATA_364296
235 /*
236 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
237 * corruption with hit-under-miss enabled). The conditional code below
238 * (setting the undocumented bit 31 in the auxiliary control register
239 * and the FI bit in the control register) disables hit-under-miss
240 * without putting the processor into full low interrupt latency mode.
241 */
242 ldr r6, =0x4107b362 @ id for ARM1136 r0p2
243 mrc p15, 0, r5, c0, c0, 0 @ get processor id
244 teq r5, r6 @ check for the faulty core
245 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
246 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
247 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
248 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
249 #endif
250 ret lr @ return to head.S:__ret
251
252 /*
253 * V X F I D LR
254 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
255 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
256 * 0 110 0011 1.00 .111 1101 < we want
257 */
258 .type v6_crval, #object
259 v6_crval:
260 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
261
262 __INITDATA
263
264 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
265 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
266
267 .section ".rodata"
268
269 string cpu_arch_name, "armv6"
270 string cpu_elf_name, "v6"
271 .align
272
273 .section ".proc.info.init", "a"
274
275 /*
276 * Match any ARMv6 processor core.
277 */
278 .type __v6_proc_info, #object
279 __v6_proc_info:
280 .long 0x0007b000
281 .long 0x0007f000
282 ALT_SMP(.long \
283 PMD_TYPE_SECT | \
284 PMD_SECT_AP_WRITE | \
285 PMD_SECT_AP_READ | \
286 PMD_FLAGS_SMP)
287 ALT_UP(.long \
288 PMD_TYPE_SECT | \
289 PMD_SECT_AP_WRITE | \
290 PMD_SECT_AP_READ | \
291 PMD_FLAGS_UP)
292 .long PMD_TYPE_SECT | \
293 PMD_SECT_XN | \
294 PMD_SECT_AP_WRITE | \
295 PMD_SECT_AP_READ
296 initfn __v6_setup, __v6_proc_info
297 .long cpu_arch_name
298 .long cpu_elf_name
299 /* See also feat_v6_fixup() for HWCAP_TLS */
300 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
301 .long cpu_v6_name
302 .long v6_processor_functions
303 .long v6wbi_tlb_fns
304 .long v6_user_fns
305 .long v6_cache_fns
306 .size __v6_proc_info, . - __v6_proc_info
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