1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 NetWinder Floating Point Emulator 4 (c) Rebel.com, 1998-1999 5 6 Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 7 8 */ 9 10 #ifndef __FPSR_H__ 11 #define __FPSR_H__ 12 13 /* 14 The FPSR is a 32 bit register consisting of 4 parts, each exactly 15 one byte. 16 17 SYSTEM ID 18 EXCEPTION TRAP ENABLE BYTE 19 SYSTEM CONTROL BYTE 20 CUMULATIVE EXCEPTION FLAGS BYTE 21 22 The FPCR is a 32 bit register consisting of bit flags. 23 */ 24 25 /* SYSTEM ID 26 ------------ 27 Note: the system id byte is read only */ 28 29 typedef unsigned int FPSR; /* type for floating point status register */ 30 typedef unsigned int FPCR; /* type for floating point control register */ 31 32 #define MASK_SYSID 0xff000000 33 #define BIT_HARDWARE 0x80000000 34 #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 35 #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 36 37 /* EXCEPTION TRAP ENABLE BYTE 38 ----------------------------- */ 39 40 #define MASK_TRAP_ENABLE 0x00ff0000 41 #define MASK_TRAP_ENABLE_STRICT 0x001f0000 42 #define BIT_IXE 0x00100000 /* inexact exception enable */ 43 #define BIT_UFE 0x00080000 /* underflow exception enable */ 44 #define BIT_OFE 0x00040000 /* overflow exception enable */ 45 #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 46 #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 47 48 /* SYSTEM CONTROL BYTE 49 ---------------------- */ 50 51 #define MASK_SYSTEM_CONTROL 0x0000ff00 52 #define MASK_TRAP_STRICT 0x00001f00 53 54 #define BIT_AC 0x00001000 /* use alternative C-flag definition 55 for compares */ 56 #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 57 #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 58 #define BIT_NE 0x00000200 /* NaN exception bit */ 59 #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 60 61 /* CUMULATIVE EXCEPTION FLAGS BYTE 62 ---------------------------------- */ 63 64 #define MASK_EXCEPTION_FLAGS 0x000000ff 65 #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 66 67 #define BIT_IXC 0x00000010 /* inexact exception flag */ 68 #define BIT_UFC 0x00000008 /* underflow exception flag */ 69 #define BIT_OFC 0x00000004 /* overfloat exception flag */ 70 #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 71 #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 72 73 /* Floating Point Control Register 74 ----------------------------------*/ 75 76 #define BIT_RU 0x80000000 /* rounded up bit */ 77 #define BIT_IE 0x10000000 /* inexact bit */ 78 #define BIT_MO 0x08000000 /* mantissa overflow bit */ 79 #define BIT_EO 0x04000000 /* exponent overflow bit */ 80 #define BIT_SB 0x00000800 /* store bounce */ 81 #define BIT_AB 0x00000400 /* arithmetic bounce */ 82 #define BIT_RE 0x00000200 /* rounding exception */ 83 #define BIT_DA 0x00000100 /* disable FPA */ 84 85 #define MASK_OP 0x00f08010 /* AU operation code */ 86 #define MASK_PR 0x00080080 /* AU precision */ 87 #define MASK_S1 0x00070000 /* AU source register 1 */ 88 #define MASK_S2 0x00000007 /* AU source register 2 */ 89 #define MASK_DS 0x00007000 /* AU destination register */ 90 #define MASK_RM 0x00000060 /* AU rounding mode */ 91 #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 92 #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 93 #define MASK_WFC MASK_RESET 94 #define MASK_RFC ~MASK_RESET 95 96 #endif 97
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