1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2017 Andreas Färber
4 */
5
6 #include <dt-bindings/clock/actions,s900-cmu.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/actions,s900-reset.h>
10
11 / {
12 compatible = "actions,s900";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <2>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a53";
24 reg = <0x0 0x0>;
25 enable-method = "psci";
26 };
27
28 cpu1: cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a53";
31 reg = <0x0 0x1>;
32 enable-method = "psci";
33 };
34
35 cpu2: cpu@2 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a53";
38 reg = <0x0 0x2>;
39 enable-method = "psci";
40 };
41
42 cpu3: cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53";
45 reg = <0x0 0x3>;
46 enable-method = "psci";
47 };
48 };
49
50 reserved-memory {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 ranges;
54
55 secmon@1f000000 {
56 reg = <0x0 0x1f000000 0x0 0x1000000>;
57 no-map;
58 };
59 };
60
61 psci {
62 compatible = "arm,psci-0.2";
63 method = "smc";
64 };
65
66 arm-pmu {
67 compatible = "arm,cortex-a53-pmu";
68 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
73 };
74
75 timer {
76 compatible = "arm,armv8-timer";
77 interrupts = <GIC_PPI 13
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
83 <GIC_PPI 10
84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
85 };
86
87 hosc: hosc {
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
90 #clock-cells = <0>;
91 };
92
93 losc: losc {
94 compatible = "fixed-clock";
95 clock-frequency = <32768>;
96 #clock-cells = <0>;
97 };
98
99 diff24M: diff24M {
100 compatible = "fixed-clock";
101 clock-frequency = <24000000>;
102 #clock-cells = <0>;
103 };
104
105 soc {
106 compatible = "simple-bus";
107 #address-cells = <2>;
108 #size-cells = <2>;
109 ranges;
110
111 gic: interrupt-controller@e00f1000 {
112 compatible = "arm,gic-400";
113 reg = <0x0 0xe00f1000 0x0 0x1000>,
114 <0x0 0xe00f2000 0x0 0x2000>,
115 <0x0 0xe00f4000 0x0 0x2000>,
116 <0x0 0xe00f6000 0x0 0x2000>;
117 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
118 interrupt-controller;
119 #interrupt-cells = <3>;
120 };
121
122 uart0: serial@e0120000 {
123 compatible = "actions,s900-uart", "actions,owl-uart";
124 reg = <0x0 0xe0120000 0x0 0x2000>;
125 clocks = <&cmu CLK_UART0>;
126 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
127 status = "disabled";
128 };
129
130 uart1: serial@e0122000 {
131 compatible = "actions,s900-uart", "actions,owl-uart";
132 reg = <0x0 0xe0122000 0x0 0x2000>;
133 clocks = <&cmu CLK_UART1>;
134 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
135 status = "disabled";
136 };
137
138 uart2: serial@e0124000 {
139 compatible = "actions,s900-uart", "actions,owl-uart";
140 reg = <0x0 0xe0124000 0x0 0x2000>;
141 clocks = <&cmu CLK_UART2>;
142 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled";
144 };
145
146 uart3: serial@e0126000 {
147 compatible = "actions,s900-uart", "actions,owl-uart";
148 reg = <0x0 0xe0126000 0x0 0x2000>;
149 clocks = <&cmu CLK_UART3>;
150 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
151 status = "disabled";
152 };
153
154 uart4: serial@e0128000 {
155 compatible = "actions,s900-uart", "actions,owl-uart";
156 reg = <0x0 0xe0128000 0x0 0x2000>;
157 clocks = <&cmu CLK_UART4>;
158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
159 status = "disabled";
160 };
161
162 uart5: serial@e012a000 {
163 compatible = "actions,s900-uart", "actions,owl-uart";
164 reg = <0x0 0xe012a000 0x0 0x2000>;
165 clocks = <&cmu CLK_UART5>;
166 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
167 status = "disabled";
168 };
169
170 uart6: serial@e012c000 {
171 compatible = "actions,s900-uart", "actions,owl-uart";
172 reg = <0x0 0xe012c000 0x0 0x2000>;
173 clocks = <&cmu CLK_UART6>;
174 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
175 status = "disabled";
176 };
177
178 sps: power-controller@e012e000 {
179 compatible = "actions,s900-sps";
180 reg = <0x0 0xe012e000 0x0 0x2000>;
181 #power-domain-cells = <1>;
182 };
183
184 cmu: clock-controller@e0160000 {
185 compatible = "actions,s900-cmu";
186 reg = <0x0 0xe0160000 0x0 0x1000>;
187 clocks = <&hosc>, <&losc>;
188 #clock-cells = <1>;
189 #reset-cells = <1>;
190 };
191
192 i2c0: i2c@e0170000 {
193 compatible = "actions,s900-i2c";
194 reg = <0 0xe0170000 0 0x1000>;
195 clocks = <&cmu CLK_I2C0>;
196 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 i2c1: i2c@e0172000 {
203 compatible = "actions,s900-i2c";
204 reg = <0 0xe0172000 0 0x1000>;
205 clocks = <&cmu CLK_I2C1>;
206 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 status = "disabled";
210 };
211
212 i2c2: i2c@e0174000 {
213 compatible = "actions,s900-i2c";
214 reg = <0 0xe0174000 0 0x1000>;
215 clocks = <&cmu CLK_I2C2>;
216 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 status = "disabled";
220 };
221
222 i2c3: i2c@e0176000 {
223 compatible = "actions,s900-i2c";
224 reg = <0 0xe0176000 0 0x1000>;
225 clocks = <&cmu CLK_I2C3>;
226 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 status = "disabled";
230 };
231
232 i2c4: i2c@e0178000 {
233 compatible = "actions,s900-i2c";
234 reg = <0 0xe0178000 0 0x1000>;
235 clocks = <&cmu CLK_I2C4>;
236 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 i2c5: i2c@e017a000 {
243 compatible = "actions,s900-i2c";
244 reg = <0 0xe017a000 0 0x1000>;
245 clocks = <&cmu CLK_I2C5>;
246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #address-cells = <1>;
248 #size-cells = <0>;
249 status = "disabled";
250 };
251
252 pinctrl: pinctrl@e01b0000 {
253 compatible = "actions,s900-pinctrl";
254 reg = <0x0 0xe01b0000 0x0 0x1000>;
255 clocks = <&cmu CLK_GPIO>;
256 gpio-controller;
257 gpio-ranges = <&pinctrl 0 0 146>;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
267 };
268
269 timer: timer@e0228000 {
270 compatible = "actions,s900-timer";
271 reg = <0x0 0xe0228000 0x0 0x8000>;
272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
273 interrupt-names = "timer1";
274 };
275
276 dma: dma-controller@e0260000 {
277 compatible = "actions,s900-dma";
278 reg = <0x0 0xe0260000 0x0 0x1000>;
279 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
283 #dma-cells = <1>;
284 dma-channels = <12>;
285 dma-requests = <46>;
286 clocks = <&cmu CLK_DMAC>;
287 };
288
289 mmc0: mmc@e0330000 {
290 compatible = "actions,owl-mmc";
291 reg = <0x0 0xe0330000 0x0 0x4000>;
292 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&cmu CLK_SD0>;
294 resets = <&cmu RESET_SD0>;
295 dmas = <&dma 2>;
296 dma-names = "mmc";
297 status = "disabled";
298 };
299
300 mmc1: mmc@e0334000 {
301 compatible = "actions,owl-mmc";
302 reg = <0x0 0xe0334000 0x0 0x4000>;
303 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cmu CLK_SD1>;
305 resets = <&cmu RESET_SD1>;
306 dmas = <&dma 3>;
307 dma-names = "mmc";
308 status = "disabled";
309 };
310
311 mmc2: mmc@e0338000 {
312 compatible = "actions,owl-mmc";
313 reg = <0x0 0xe0338000 0x0 0x4000>;
314 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cmu CLK_SD2>;
316 resets = <&cmu RESET_SD2>;
317 dmas = <&dma 4>;
318 dma-names = "mmc";
319 status = "disabled";
320 };
321
322 mmc3: mmc@e033c000 {
323 compatible = "actions,owl-mmc";
324 reg = <0x0 0xe033c000 0x0 0x4000>;
325 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&cmu CLK_SD3>;
327 resets = <&cmu RESET_SD3>;
328 dmas = <&dma 46>;
329 dma-names = "mmc";
330 status = "disabled";
331 };
332 };
333 };
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