1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2023 Martin Botka <martin@somainline.org>
3
4 / {
5 cpu_opp_table: opp-table-cpu {
6 compatible = "allwinner,sun50i-h616-operating-points";
7 nvmem-cells = <&cpu_speed_grade>;
8 opp-shared;
9
10 opp-480000000 {
11 opp-hz = /bits/ 64 <480000000>;
12 opp-microvolt = <900000>;
13 clock-latency-ns = <244144>; /* 8 32k periods */
14 opp-supported-hw = <0x3f>;
15 };
16
17 opp-600000000 {
18 opp-hz = /bits/ 64 <600000000>;
19 opp-microvolt = <900000>;
20 clock-latency-ns = <244144>; /* 8 32k periods */
21 opp-supported-hw = <0x12>;
22 };
23
24 opp-720000000 {
25 opp-hz = /bits/ 64 <720000000>;
26 opp-microvolt = <900000>;
27 clock-latency-ns = <244144>; /* 8 32k periods */
28 opp-supported-hw = <0x2d>;
29 };
30
31 opp-792000000 {
32 opp-hz = /bits/ 64 <792000000>;
33 opp-microvolt-speed1 = <900000>;
34 opp-microvolt-speed4 = <940000>;
35 clock-latency-ns = <244144>; /* 8 32k periods */
36 opp-supported-hw = <0x12>;
37 };
38
39 opp-936000000 {
40 opp-hz = /bits/ 64 <936000000>;
41 opp-microvolt = <900000>;
42 clock-latency-ns = <244144>; /* 8 32k periods */
43 opp-supported-hw = <0x0d>;
44 };
45
46 opp-1008000000 {
47 opp-hz = /bits/ 64 <1008000000>;
48 opp-microvolt-speed0 = <950000>;
49 opp-microvolt-speed1 = <940000>;
50 opp-microvolt-speed2 = <950000>;
51 opp-microvolt-speed3 = <950000>;
52 opp-microvolt-speed4 = <1020000>;
53 opp-microvolt-speed5 = <900000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
55 opp-supported-hw = <0x3f>;
56 };
57
58 opp-1032000000 {
59 opp-hz = /bits/ 64 <1032000000>;
60 opp-microvolt = <900000>;
61 clock-latency-ns = <244144>; /* 8 32k periods */
62 opp-supported-hw = <0x20>;
63 };
64
65 opp-1104000000 {
66 opp-hz = /bits/ 64 <1104000000>;
67 opp-microvolt-speed0 = <1000000>;
68 opp-microvolt-speed2 = <1000000>;
69 opp-microvolt-speed3 = <1000000>;
70 opp-microvolt-speed5 = <950000>;
71 clock-latency-ns = <244144>; /* 8 32k periods */
72 opp-supported-hw = <0x2d>;
73 };
74
75 opp-1200000000 {
76 opp-hz = /bits/ 64 <1200000000>;
77 opp-microvolt-speed0 = <1050000>;
78 opp-microvolt-speed1 = <1020000>;
79 opp-microvolt-speed2 = <1050000>;
80 opp-microvolt-speed3 = <1050000>;
81 opp-microvolt-speed4 = <1100000>;
82 opp-microvolt-speed5 = <1020000>;
83 clock-latency-ns = <244144>; /* 8 32k periods */
84 opp-supported-hw = <0x3f>;
85 };
86
87 opp-1320000000 {
88 opp-hz = /bits/ 64 <1320000000>;
89 opp-microvolt = <1100000>;
90 clock-latency-ns = <244144>; /* 8 32k periods */
91 opp-supported-hw = <0x1d>;
92 };
93
94 opp-1416000000 {
95 opp-hz = /bits/ 64 <1416000000>;
96 opp-microvolt = <1100000>;
97 clock-latency-ns = <244144>; /* 8 32k periods */
98 opp-supported-hw = <0x2d>;
99 };
100
101 opp-1512000000 {
102 opp-hz = /bits/ 64 <1512000000>;
103 opp-microvolt-speed1 = <1100000>;
104 opp-microvolt-speed3 = <1100000>;
105 opp-microvolt-speed5 = <1160000>;
106 clock-latency-ns = <244144>; /* 8 32k periods */
107 opp-supported-hw = <0x2a>;
108 };
109 };
110 };
111
112 &cpu0 {
113 operating-points-v2 = <&cpu_opp_table>;
114 };
115
116 &cpu1 {
117 operating-points-v2 = <&cpu_opp_table>;
118 };
119
120 &cpu2 {
121 operating-points-v2 = <&cpu_opp_table>;
122 };
123
124 &cpu3 {
125 operating-points-v2 = <&cpu_opp_table>;
126 };
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