1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022, Intel Corporation
4 */
5
6 #include "socfpga_stratix10.dtsi"
7
8 / {
9 model = "SOCFPGA Stratix 10 SWVP";
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
11
12 aliases {
13 serial0 = &uart0;
14 serial1 = &uart1;
15
16 timer0 = &timer0;
17 timer1 = &timer1;
18 timer2 = &timer2;
19 timer3 = &timer3;
20
21 ethernet0 = &gmac0;
22 ethernet1 = &gmac1;
23 ethernet2 = &gmac2;
24 };
25
26 chosen {
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
30 };
31
32 memory@80000000 {
33 device_type = "memory";
34 reg = <0x0 0x0 0x0 0x80000000>;
35 };
36 };
37
38 &cpu0 {
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
41 };
42
43 &cpu1 {
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
46 };
47
48 &cpu2 {
49 enable-method = "spin-table";
50 cpu-release-addr = <0x0 0x0000fff8>;
51 };
52
53 &cpu3 {
54 enable-method = "spin-table";
55 cpu-release-addr = <0x0 0x0000fff8>;
56 };
57
58 &osc1 {
59 clock-frequency = <25000000>;
60 };
61
62 &gmac0 {
63 status = "okay";
64 phy-mode = "rgmii";
65 phy-addr = <0xffffffff>;
66 snps,max-mtu = <0x0>;
67 };
68
69 &gmac1 {
70 status = "okay";
71 phy-mode = "rgmii";
72 phy-addr = <0xffffffff>;
73 };
74
75 &gmac2 {
76 status = "okay";
77 phy-mode = "rgmii";
78 phy-addr = <0xffffffff>;
79 };
80
81 &mmc {
82 status = "okay";
83 cap-sd-highspeed;
84 cap-mmc-highspeed;
85 broken-cd;
86 bus-width = <4>;
87 };
88
89 &uart0 {
90 status = "okay";
91 };
92
93 &uart1 {
94 status = "okay";
95 };
96
97 &usb0 {
98 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
99 status = "okay";
100 };
101
102 &usb1 {
103 clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
104 status = "okay";
105 };
106
107 &rst {
108 altr,modrst-offset = <0x20>;
109 };
110
111 &sysmgr {
112 reg = <0xffd12000 0x1000>;
113 interrupts = <0x0 0x10 0x4>;
114 cpu1-start-addr = <0xffd06230>;
115 };
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