1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
13
14 / {
15 compatible = "amlogic,meson-gxbb";
16
17 soc {
18 usb0_phy: phy@c0000000 {
19 compatible = "amlogic,meson-gxbb-usb2-phy";
20 #phy-cells = <0>;
21 reg = <0x0 0xc0000000 0x0 0x20>;
22 resets = <&reset RESET_USB_OTG>;
23 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
24 clock-names = "usb_general", "usb";
25 status = "disabled";
26 };
27
28 usb1_phy: phy@c0000020 {
29 compatible = "amlogic,meson-gxbb-usb2-phy";
30 #phy-cells = <0>;
31 reg = <0x0 0xc0000020 0x0 0x20>;
32 resets = <&reset RESET_USB_OTG>;
33 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
34 clock-names = "usb_general", "usb";
35 status = "disabled";
36 };
37
38 usb0: usb@c9000000 {
39 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
40 reg = <0x0 0xc9000000 0x0 0x40000>;
41 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
43 clock-names = "otg";
44 phys = <&usb0_phy>;
45 phy-names = "usb2-phy";
46 dr_mode = "host";
47 status = "disabled";
48 };
49
50 usb1: usb@c9100000 {
51 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
52 reg = <0x0 0xc9100000 0x0 0x40000>;
53 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
55 clock-names = "otg";
56 phys = <&usb1_phy>;
57 phy-names = "usb2-phy";
58 dr_mode = "host";
59 status = "disabled";
60 };
61 };
62 };
63
64 &aiu {
65 compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
66 clocks = <&clkc CLKID_AIU_GLUE>,
67 <&clkc CLKID_I2S_OUT>,
68 <&clkc CLKID_AOCLK_GATE>,
69 <&clkc CLKID_CTS_AMCLK>,
70 <&clkc CLKID_MIXER_IFACE>,
71 <&clkc CLKID_IEC958>,
72 <&clkc CLKID_IEC958_GATE>,
73 <&clkc CLKID_CTS_MCLK_I958>,
74 <&clkc CLKID_CTS_I958>;
75 clock-names = "pclk",
76 "i2s_pclk",
77 "i2s_aoclk",
78 "i2s_mclk",
79 "i2s_mixer",
80 "spdif_pclk",
81 "spdif_aoclk",
82 "spdif_mclk",
83 "spdif_mclk_sel";
84 resets = <&reset RESET_AIU>;
85 };
86
87 &aobus {
88 pinctrl_aobus: pinctrl@14 {
89 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
90 #address-cells = <2>;
91 #size-cells = <2>;
92 ranges;
93
94 gpio_ao: bank@14 {
95 reg = <0x0 0x00014 0x0 0x8>,
96 <0x0 0x0002c 0x0 0x4>,
97 <0x0 0x00024 0x0 0x8>;
98 reg-names = "mux", "pull", "gpio";
99 gpio-controller;
100 #gpio-cells = <2>;
101 gpio-ranges = <&pinctrl_aobus 0 0 14>;
102 };
103
104 uart_ao_a_pins: uart_ao_a {
105 mux {
106 groups = "uart_tx_ao_a", "uart_rx_ao_a";
107 function = "uart_ao";
108 bias-disable;
109 };
110 };
111
112 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
113 mux {
114 groups = "uart_cts_ao_a",
115 "uart_rts_ao_a";
116 function = "uart_ao";
117 bias-disable;
118 };
119 };
120
121 uart_ao_b_pins: uart_ao_b {
122 mux {
123 groups = "uart_tx_ao_b", "uart_rx_ao_b";
124 function = "uart_ao_b";
125 bias-disable;
126 };
127 };
128
129 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
130 mux {
131 groups = "uart_cts_ao_b",
132 "uart_rts_ao_b";
133 function = "uart_ao_b";
134 bias-disable;
135 };
136 };
137
138 remote_input_ao_pins: remote_input_ao {
139 mux {
140 groups = "remote_input_ao";
141 function = "remote_input_ao";
142 bias-disable;
143 };
144 };
145
146 i2c_ao_pins: i2c_ao {
147 mux {
148 groups = "i2c_sck_ao",
149 "i2c_sda_ao";
150 function = "i2c_ao";
151 bias-disable;
152 };
153 };
154
155 pwm_ao_a_3_pins: pwm_ao_a_3 {
156 mux {
157 groups = "pwm_ao_a_3";
158 function = "pwm_ao_a_3";
159 bias-disable;
160 };
161 };
162
163 pwm_ao_a_6_pins: pwm_ao_a_6 {
164 mux {
165 groups = "pwm_ao_a_6";
166 function = "pwm_ao_a_6";
167 bias-disable;
168 };
169 };
170
171 pwm_ao_a_12_pins: pwm_ao_a_12 {
172 mux {
173 groups = "pwm_ao_a_12";
174 function = "pwm_ao_a_12";
175 bias-disable;
176 };
177 };
178
179 pwm_ao_b_pins: pwm_ao_b {
180 mux {
181 groups = "pwm_ao_b";
182 function = "pwm_ao_b";
183 bias-disable;
184 };
185 };
186
187 i2s_am_clk_pins: i2s_am_clk {
188 mux {
189 groups = "i2s_am_clk";
190 function = "i2s_out_ao";
191 bias-disable;
192 };
193 };
194
195 i2s_out_ao_clk_pins: i2s_out_ao_clk {
196 mux {
197 groups = "i2s_out_ao_clk";
198 function = "i2s_out_ao";
199 bias-disable;
200 };
201 };
202
203 i2s_out_lr_clk_pins: i2s_out_lr_clk {
204 mux {
205 groups = "i2s_out_lr_clk";
206 function = "i2s_out_ao";
207 bias-disable;
208 };
209 };
210
211 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
212 mux {
213 groups = "i2s_out_ch01_ao";
214 function = "i2s_out_ao";
215 bias-disable;
216 };
217 };
218
219 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
220 mux {
221 groups = "i2s_out_ch23_ao";
222 function = "i2s_out_ao";
223 bias-disable;
224 };
225 };
226
227 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
228 mux {
229 groups = "i2s_out_ch45_ao";
230 function = "i2s_out_ao";
231 bias-disable;
232 };
233 };
234
235 spdif_out_ao_6_pins: spdif_out_ao_6 {
236 mux {
237 groups = "spdif_out_ao_6";
238 function = "spdif_out_ao";
239 };
240 };
241
242 spdif_out_ao_13_pins: spdif_out_ao_13 {
243 mux {
244 groups = "spdif_out_ao_13";
245 function = "spdif_out_ao";
246 bias-disable;
247 };
248 };
249
250 ao_cec_pins: ao_cec {
251 mux {
252 groups = "ao_cec";
253 function = "cec_ao";
254 bias-disable;
255 };
256 };
257
258 ee_cec_pins: ee_cec {
259 mux {
260 groups = "ee_cec";
261 function = "cec_ao";
262 bias-disable;
263 };
264 };
265 };
266 };
267
268 &cbus {
269 spifc: spi@8c80 {
270 compatible = "amlogic,meson-gxbb-spifc";
271 reg = <0x0 0x08c80 0x0 0x80>;
272 #address-cells = <1>;
273 #size-cells = <0>;
274 clocks = <&clkc CLKID_SPI>;
275 status = "disabled";
276 };
277 };
278
279 &cec_AO {
280 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
281 clock-names = "core";
282 };
283
284 &clkc_AO {
285 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
286 clocks = <&xtal>, <&clkc CLKID_CLK81>;
287 clock-names = "xtal", "mpeg-clk";
288 };
289
290 &efuse {
291 clocks = <&clkc CLKID_EFUSE>;
292 };
293
294 ðmac {
295 clocks = <&clkc CLKID_ETH>,
296 <&clkc CLKID_FCLK_DIV2>,
297 <&clkc CLKID_MPLL2>,
298 <&clkc CLKID_FCLK_DIV2>;
299 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
300 };
301
302 &gpio_intc {
303 compatible = "amlogic,meson-gxbb-gpio-intc",
304 "amlogic,meson-gpio-intc";
305 status = "okay";
306 };
307
308 &hdmi_tx {
309 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
310 resets = <&reset RESET_HDMITX_CAPB3>,
311 <&reset RESET_HDMI_SYSTEM_RESET>,
312 <&reset RESET_HDMI_TX>;
313 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
314 clocks = <&clkc CLKID_HDMI>,
315 <&clkc CLKID_HDMI_PCLK>,
316 <&clkc CLKID_GCLK_VENCI_INT0>;
317 clock-names = "isfr", "iahb", "venci";
318 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
319
320 assigned-clocks = <&clkc CLKID_HDMI_SEL>,
321 <&clkc CLKID_HDMI>;
322 assigned-clock-parents = <&xtal>, <0>;
323 assigned-clock-rates = <0>, <24000000>;
324 };
325
326 &sysctrl {
327 clkc: clock-controller {
328 compatible = "amlogic,gxbb-clkc";
329 #clock-cells = <1>;
330 clocks = <&xtal>;
331 clock-names = "xtal";
332 };
333 };
334
335 &hwrng {
336 clocks = <&clkc CLKID_RNG0>;
337 clock-names = "core";
338 };
339
340 &i2c_A {
341 clocks = <&clkc CLKID_I2C>;
342 };
343
344 &i2c_AO {
345 clocks = <&clkc CLKID_AO_I2C>;
346 };
347
348 &i2c_B {
349 clocks = <&clkc CLKID_I2C>;
350 };
351
352 &i2c_C {
353 clocks = <&clkc CLKID_I2C>;
354 };
355
356 &mali {
357 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
358
359 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
360 clock-names = "bus", "core";
361
362 assigned-clocks = <&clkc CLKID_GP0_PLL>;
363 assigned-clock-rates = <744000000>;
364 };
365
366 &periphs {
367 pinctrl_periphs: pinctrl@4b0 {
368 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
369 #address-cells = <2>;
370 #size-cells = <2>;
371 ranges;
372
373 gpio: bank@4b0 {
374 reg = <0x0 0x004b0 0x0 0x28>,
375 <0x0 0x004e8 0x0 0x14>,
376 <0x0 0x00520 0x0 0x14>,
377 <0x0 0x00430 0x0 0x40>;
378 reg-names = "mux", "pull", "pull-enable", "gpio";
379 gpio-controller;
380 #gpio-cells = <2>;
381 gpio-ranges = <&pinctrl_periphs 0 0 119>;
382 };
383
384 emmc_pins: emmc {
385 mux-0 {
386 groups = "emmc_nand_d07",
387 "emmc_cmd";
388 function = "emmc";
389 bias-pull-up;
390 };
391
392 mux-1 {
393 groups = "emmc_clk";
394 function = "emmc";
395 bias-disable;
396 };
397 };
398
399 emmc_ds_pins: emmc-ds {
400 mux {
401 groups = "emmc_ds";
402 function = "emmc";
403 bias-pull-down;
404 };
405 };
406
407 emmc_clk_gate_pins: emmc_clk_gate {
408 mux {
409 groups = "BOOT_8";
410 function = "gpio_periphs";
411 bias-pull-down;
412 };
413 };
414
415 nor_pins: nor {
416 mux {
417 groups = "nor_d",
418 "nor_q",
419 "nor_c",
420 "nor_cs";
421 function = "nor";
422 bias-disable;
423 };
424 };
425
426 spi_pins: spi-pins {
427 mux {
428 groups = "spi_miso",
429 "spi_mosi",
430 "spi_sclk";
431 function = "spi";
432 bias-disable;
433 };
434 };
435
436 spi_idle_high_pins: spi-idle-high-pins {
437 mux {
438 groups = "spi_sclk";
439 bias-pull-up;
440 };
441 };
442
443 spi_idle_low_pins: spi-idle-low-pins {
444 mux {
445 groups = "spi_sclk";
446 bias-pull-down;
447 };
448 };
449
450 spi_ss0_pins: spi-ss0 {
451 mux {
452 groups = "spi_ss0";
453 function = "spi";
454 bias-disable;
455 };
456 };
457
458 sdcard_pins: sdcard {
459 mux-0 {
460 groups = "sdcard_d0",
461 "sdcard_d1",
462 "sdcard_d2",
463 "sdcard_d3",
464 "sdcard_cmd";
465 function = "sdcard";
466 bias-pull-up;
467 };
468
469 mux-1 {
470 groups = "sdcard_clk";
471 function = "sdcard";
472 bias-disable;
473 };
474 };
475
476 sdcard_clk_gate_pins: sdcard_clk_gate {
477 mux {
478 groups = "CARD_2";
479 function = "gpio_periphs";
480 bias-pull-down;
481 };
482 };
483
484 sdio_pins: sdio {
485 mux-0 {
486 groups = "sdio_d0",
487 "sdio_d1",
488 "sdio_d2",
489 "sdio_d3",
490 "sdio_cmd";
491 function = "sdio";
492 bias-pull-up;
493 };
494
495 mux-1 {
496 groups = "sdio_clk";
497 function = "sdio";
498 bias-disable;
499 };
500 };
501
502 sdio_clk_gate_pins: sdio_clk_gate {
503 mux {
504 groups = "GPIOX_4";
505 function = "gpio_periphs";
506 bias-pull-down;
507 };
508 };
509
510 sdio_irq_pins: sdio_irq {
511 mux {
512 groups = "sdio_irq";
513 function = "sdio";
514 bias-disable;
515 };
516 };
517
518 uart_a_pins: uart_a {
519 mux {
520 groups = "uart_tx_a",
521 "uart_rx_a";
522 function = "uart_a";
523 bias-disable;
524 };
525 };
526
527 uart_a_cts_rts_pins: uart_a_cts_rts {
528 mux {
529 groups = "uart_cts_a",
530 "uart_rts_a";
531 function = "uart_a";
532 bias-disable;
533 };
534 };
535
536 uart_b_pins: uart_b {
537 mux {
538 groups = "uart_tx_b",
539 "uart_rx_b";
540 function = "uart_b";
541 bias-disable;
542 };
543 };
544
545 uart_b_cts_rts_pins: uart_b_cts_rts {
546 mux {
547 groups = "uart_cts_b",
548 "uart_rts_b";
549 function = "uart_b";
550 bias-disable;
551 };
552 };
553
554 uart_c_pins: uart_c {
555 mux {
556 groups = "uart_tx_c",
557 "uart_rx_c";
558 function = "uart_c";
559 bias-disable;
560 };
561 };
562
563 uart_c_cts_rts_pins: uart_c_cts_rts {
564 mux {
565 groups = "uart_cts_c",
566 "uart_rts_c";
567 function = "uart_c";
568 bias-disable;
569 };
570 };
571
572 i2c_a_pins: i2c_a {
573 mux {
574 groups = "i2c_sck_a",
575 "i2c_sda_a";
576 function = "i2c_a";
577 bias-disable;
578 };
579 };
580
581 i2c_b_pins: i2c_b {
582 mux {
583 groups = "i2c_sck_b",
584 "i2c_sda_b";
585 function = "i2c_b";
586 bias-disable;
587 };
588 };
589
590 i2c_c_pins: i2c_c {
591 mux {
592 groups = "i2c_sck_c",
593 "i2c_sda_c";
594 function = "i2c_c";
595 bias-disable;
596 };
597 };
598
599 eth_rgmii_pins: eth-rgmii {
600 mux {
601 groups = "eth_mdio",
602 "eth_mdc",
603 "eth_clk_rx_clk",
604 "eth_rx_dv",
605 "eth_rxd0",
606 "eth_rxd1",
607 "eth_rxd2",
608 "eth_rxd3",
609 "eth_rgmii_tx_clk",
610 "eth_tx_en",
611 "eth_txd0",
612 "eth_txd1",
613 "eth_txd2",
614 "eth_txd3";
615 function = "eth";
616 bias-disable;
617 };
618 };
619
620 eth_rmii_pins: eth-rmii {
621 mux {
622 groups = "eth_mdio",
623 "eth_mdc",
624 "eth_clk_rx_clk",
625 "eth_rx_dv",
626 "eth_rxd0",
627 "eth_rxd1",
628 "eth_tx_en",
629 "eth_txd0",
630 "eth_txd1";
631 function = "eth";
632 bias-disable;
633 };
634 };
635
636 pwm_a_x_pins: pwm_a_x {
637 mux {
638 groups = "pwm_a_x";
639 function = "pwm_a_x";
640 bias-disable;
641 };
642 };
643
644 pwm_a_y_pins: pwm_a_y {
645 mux {
646 groups = "pwm_a_y";
647 function = "pwm_a_y";
648 bias-disable;
649 };
650 };
651
652 pwm_b_pins: pwm_b {
653 mux {
654 groups = "pwm_b";
655 function = "pwm_b";
656 bias-disable;
657 };
658 };
659
660 pwm_d_pins: pwm_d {
661 mux {
662 groups = "pwm_d";
663 function = "pwm_d";
664 bias-disable;
665 };
666 };
667
668 pwm_e_pins: pwm_e {
669 mux {
670 groups = "pwm_e";
671 function = "pwm_e";
672 bias-disable;
673 };
674 };
675
676 pwm_f_x_pins: pwm_f_x {
677 mux {
678 groups = "pwm_f_x";
679 function = "pwm_f_x";
680 bias-disable;
681 };
682 };
683
684 pwm_f_y_pins: pwm_f_y {
685 mux {
686 groups = "pwm_f_y";
687 function = "pwm_f_y";
688 bias-disable;
689 };
690 };
691
692 hdmi_hpd_pins: hdmi_hpd {
693 mux {
694 groups = "hdmi_hpd";
695 function = "hdmi_hpd";
696 bias-disable;
697 };
698 };
699
700 hdmi_i2c_pins: hdmi_i2c {
701 mux {
702 groups = "hdmi_sda", "hdmi_scl";
703 function = "hdmi_i2c";
704 bias-disable;
705 };
706 };
707
708 i2sout_ch23_y_pins: i2sout_ch23_y {
709 mux {
710 groups = "i2sout_ch23_y";
711 function = "i2s_out";
712 bias-disable;
713 };
714 };
715
716 i2sout_ch45_y_pins: i2sout_ch45_y {
717 mux {
718 groups = "i2sout_ch45_y";
719 function = "i2s_out";
720 bias-disable;
721 };
722 };
723
724 i2sout_ch67_y_pins: i2sout_ch67_y {
725 mux {
726 groups = "i2sout_ch67_y";
727 function = "i2s_out";
728 bias-disable;
729 };
730 };
731
732 spdif_out_y_pins: spdif_out_y {
733 mux {
734 groups = "spdif_out_y";
735 function = "spdif_out";
736 bias-disable;
737 };
738 };
739 };
740 };
741
742 &pwrc {
743 resets = <&reset RESET_VIU>,
744 <&reset RESET_VENC>,
745 <&reset RESET_VCBUS>,
746 <&reset RESET_BT656>,
747 <&reset RESET_DVIN_RESET>,
748 <&reset RESET_RDMA>,
749 <&reset RESET_VENCI>,
750 <&reset RESET_VENCP>,
751 <&reset RESET_VDAC>,
752 <&reset RESET_VDI6>,
753 <&reset RESET_VENCL>,
754 <&reset RESET_VID_LOCK>;
755 reset-names = "viu", "venc", "vcbus", "bt656",
756 "dvin", "rdma", "venci", "vencp",
757 "vdac", "vdi6", "vencl", "vid_lock";
758 clocks = <&clkc CLKID_VPU>,
759 <&clkc CLKID_VAPB>;
760 clock-names = "vpu", "vapb";
761 /*
762 * VPU clocking is provided by two identical clock paths
763 * VPU_0 and VPU_1 muxed to a single clock by a glitch
764 * free mux to safely change frequency while running.
765 * Same for VAPB but with a final gate after the glitch free mux.
766 */
767 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
768 <&clkc CLKID_VPU_0>,
769 <&clkc CLKID_VPU>, /* Glitch free mux */
770 <&clkc CLKID_VAPB_0_SEL>,
771 <&clkc CLKID_VAPB_0>,
772 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
773 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
774 <0>, /* Do Nothing */
775 <&clkc CLKID_VPU_0>,
776 <&clkc CLKID_FCLK_DIV4>,
777 <0>, /* Do Nothing */
778 <&clkc CLKID_VAPB_0>;
779 assigned-clock-rates = <0>, /* Do Nothing */
780 <666666666>,
781 <0>, /* Do Nothing */
782 <0>, /* Do Nothing */
783 <250000000>,
784 <0>; /* Do Nothing */
785 };
786
787 &saradc {
788 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
789 clocks = <&xtal>,
790 <&clkc CLKID_SAR_ADC>,
791 <&clkc CLKID_SAR_ADC_CLK>,
792 <&clkc CLKID_SAR_ADC_SEL>;
793 clock-names = "clkin", "core", "adc_clk", "adc_sel";
794 };
795
796 &sd_emmc_a {
797 clocks = <&clkc CLKID_SD_EMMC_A>,
798 <&clkc CLKID_SD_EMMC_A_CLK0>,
799 <&clkc CLKID_FCLK_DIV2>;
800 clock-names = "core", "clkin0", "clkin1";
801 resets = <&reset RESET_SD_EMMC_A>;
802 };
803
804 &sd_emmc_b {
805 clocks = <&clkc CLKID_SD_EMMC_B>,
806 <&clkc CLKID_SD_EMMC_B_CLK0>,
807 <&clkc CLKID_FCLK_DIV2>;
808 clock-names = "core", "clkin0", "clkin1";
809 resets = <&reset RESET_SD_EMMC_B>;
810 };
811
812 &sd_emmc_c {
813 clocks = <&clkc CLKID_SD_EMMC_C>,
814 <&clkc CLKID_SD_EMMC_C_CLK0>,
815 <&clkc CLKID_FCLK_DIV2>;
816 clock-names = "core", "clkin0", "clkin1";
817 resets = <&reset RESET_SD_EMMC_C>;
818 };
819
820 &simplefb_hdmi {
821 clocks = <&clkc CLKID_HDMI_PCLK>,
822 <&clkc CLKID_CLK81>,
823 <&clkc CLKID_GCLK_VENCI_INT0>;
824 };
825
826 &spicc {
827 clocks = <&clkc CLKID_SPICC>;
828 clock-names = "core";
829 resets = <&reset RESET_PERIPHS_SPICC>;
830 num-cs = <1>;
831 };
832
833 &spifc {
834 clocks = <&clkc CLKID_SPI>;
835 };
836
837 &uart_A {
838 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
839 clock-names = "xtal", "pclk", "baud";
840 };
841
842 &uart_AO {
843 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
844 clock-names = "xtal", "pclk", "baud";
845 };
846
847 &uart_AO_B {
848 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
849 clock-names = "xtal", "pclk", "baud";
850 };
851
852 &uart_B {
853 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
854 clock-names = "xtal", "pclk", "baud";
855 };
856
857 &uart_C {
858 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
859 clock-names = "xtal", "pclk", "baud";
860 };
861
862 &vpu {
863 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
864 power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
865 };
866
867 &vdec {
868 compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
869 clocks = <&clkc CLKID_DOS_PARSER>,
870 <&clkc CLKID_DOS>,
871 <&clkc CLKID_VDEC_1>,
872 <&clkc CLKID_VDEC_HEVC>;
873 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
874 resets = <&reset RESET_PARSER>;
875 reset-names = "esparser";
876 };
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