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TOMOYO Linux Cross Reference
Linux/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

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  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*
  3  * Copyright (c) 2016 Endless Computers, Inc.
  4  * Author: Carlo Caione <carlo@endlessm.com>
  5  */
  6 
  7 #include "meson-gx.dtsi"
  8 #include <dt-bindings/clock/gxbb-clkc.h>
  9 #include <dt-bindings/clock/gxbb-aoclkc.h>
 10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
 11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
 12 
 13 / {
 14         compatible = "amlogic,meson-gxl";
 15 
 16         soc {
 17                 usb: usb@d0078080 {
 18                         compatible = "amlogic,meson-gxl-usb-ctrl";
 19                         reg = <0x0 0xd0078080 0x0 0x20>;
 20                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 21                         #address-cells = <2>;
 22                         #size-cells = <2>;
 23                         ranges;
 24 
 25                         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
 26                         clock-names = "usb_ctrl", "ddr";
 27                         resets = <&reset RESET_USB_OTG>;
 28 
 29                         dr_mode = "otg";
 30 
 31                         phys = <&usb2_phy0>, <&usb2_phy1>;
 32                         phy-names = "usb2-phy0", "usb2-phy1";
 33 
 34                         dwc2: usb@c9100000 {
 35                                 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
 36                                 reg = <0x0 0xc9100000 0x0 0x40000>;
 37                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 38                                 clocks = <&clkc CLKID_USB1>;
 39                                 clock-names = "otg";
 40                                 phys = <&usb2_phy1>;
 41                                 dr_mode = "peripheral";
 42                                 g-rx-fifo-size = <192>;
 43                                 g-np-tx-fifo-size = <128>;
 44                                 g-tx-fifo-size = <128 128 16 16 16>;
 45                         };
 46 
 47                         dwc3: usb@c9000000 {
 48                                 compatible = "snps,dwc3";
 49                                 reg = <0x0 0xc9000000 0x0 0x100000>;
 50                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 51                                 dr_mode = "host";
 52                                 maximum-speed = "high-speed";
 53                                 snps,dis_u2_susphy_quirk;
 54                         };
 55                 };
 56 
 57                 acodec: audio-controller@c8832000 {
 58                         compatible = "amlogic,t9015";
 59                         reg = <0x0 0xc8832000 0x0 0x14>;
 60                         #sound-dai-cells = <0>;
 61                         sound-name-prefix = "ACODEC";
 62                         clocks = <&clkc CLKID_ACODEC>;
 63                         clock-names = "pclk";
 64                         resets = <&reset RESET_ACODEC>;
 65                         status = "disabled";
 66                 };
 67 
 68                 crypto: crypto@c883e000 {
 69                         compatible = "amlogic,gxl-crypto";
 70                         reg = <0x0 0xc883e000 0x0 0x36>;
 71                         interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
 72                                      <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
 73                         clocks = <&clkc CLKID_BLKMV>;
 74                         clock-names = "blkmv";
 75                         status = "okay";
 76                 };
 77         };
 78 };
 79 
 80 &aiu {
 81         compatible = "amlogic,aiu-gxl", "amlogic,aiu";
 82         clocks = <&clkc CLKID_AIU_GLUE>,
 83                  <&clkc CLKID_I2S_OUT>,
 84                  <&clkc CLKID_AOCLK_GATE>,
 85                  <&clkc CLKID_CTS_AMCLK>,
 86                  <&clkc CLKID_MIXER_IFACE>,
 87                  <&clkc CLKID_IEC958>,
 88                  <&clkc CLKID_IEC958_GATE>,
 89                  <&clkc CLKID_CTS_MCLK_I958>,
 90                  <&clkc CLKID_CTS_I958>;
 91         clock-names = "pclk",
 92                       "i2s_pclk",
 93                       "i2s_aoclk",
 94                       "i2s_mclk",
 95                       "i2s_mixer",
 96                       "spdif_pclk",
 97                       "spdif_aoclk",
 98                       "spdif_mclk",
 99                       "spdif_mclk_sel";
100         resets = <&reset RESET_AIU>;
101 };
102 
103 &apb {
104         usb2_phy0: phy@78000 {
105                 compatible = "amlogic,meson-gxl-usb2-phy";
106                 #phy-cells = <0>;
107                 reg = <0x0 0x78000 0x0 0x20>;
108                 clocks = <&clkc CLKID_USB>;
109                 clock-names = "phy";
110                 resets = <&reset RESET_USB_OTG>;
111                 reset-names = "phy";
112                 status = "okay";
113         };
114 
115         usb2_phy1: phy@78020 {
116                 compatible = "amlogic,meson-gxl-usb2-phy";
117                 #phy-cells = <0>;
118                 reg = <0x0 0x78020 0x0 0x20>;
119                 clocks = <&clkc CLKID_USB>;
120                 clock-names = "phy";
121                 resets = <&reset RESET_USB_OTG>;
122                 reset-names = "phy";
123                 status = "okay";
124         };
125 };
126 
127 &efuse {
128         clocks = <&clkc CLKID_EFUSE>;
129 };
130 
131 &ethmac {
132         clocks = <&clkc CLKID_ETH>,
133                  <&clkc CLKID_FCLK_DIV2>,
134                  <&clkc CLKID_MPLL2>,
135                  <&clkc CLKID_FCLK_DIV2>;
136         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
137 
138         mdio0: mdio {
139                 #address-cells = <1>;
140                 #size-cells = <0>;
141                 compatible = "snps,dwmac-mdio";
142         };
143 };
144 
145 &aobus {
146         pinctrl_aobus: pinctrl@14 {
147                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
148                 #address-cells = <2>;
149                 #size-cells = <2>;
150                 ranges;
151 
152                 gpio_ao: bank@14 {
153                         reg = <0x0 0x00014 0x0 0x8>,
154                               <0x0 0x0002c 0x0 0x4>,
155                               <0x0 0x00024 0x0 0x8>;
156                         reg-names = "mux", "pull", "gpio";
157                         gpio-controller;
158                         #gpio-cells = <2>;
159                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
160                 };
161 
162                 uart_ao_a_pins: uart_ao_a {
163                         mux {
164                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
165                                 function = "uart_ao";
166                                 bias-disable;
167                         };
168                 };
169 
170                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
171                         mux {
172                                 groups = "uart_cts_ao_a",
173                                        "uart_rts_ao_a";
174                                 function = "uart_ao";
175                                 bias-disable;
176                         };
177                 };
178 
179                 uart_ao_b_pins: uart_ao_b {
180                         mux {
181                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
182                                 function = "uart_ao_b";
183                                 bias-disable;
184                         };
185                 };
186 
187                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
188                         mux {
189                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
190                                 function = "uart_ao_b";
191                                 bias-disable;
192                         };
193                 };
194 
195                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
196                         mux {
197                                 groups = "uart_cts_ao_b",
198                                        "uart_rts_ao_b";
199                                 function = "uart_ao_b";
200                                 bias-disable;
201                         };
202                 };
203 
204                 remote_input_ao_pins: remote_input_ao {
205                         mux {
206                                 groups = "remote_input_ao";
207                                 function = "remote_input_ao";
208                                 bias-disable;
209                         };
210                 };
211 
212                 i2c_ao_pins: i2c_ao {
213                         mux {
214                                 groups = "i2c_sck_ao",
215                                        "i2c_sda_ao";
216                                 function = "i2c_ao";
217                                 bias-disable;
218                         };
219                 };
220 
221                 pwm_ao_a_3_pins: pwm_ao_a_3 {
222                         mux {
223                                 groups = "pwm_ao_a_3";
224                                 function = "pwm_ao_a";
225                                 bias-disable;
226                         };
227                 };
228 
229                 pwm_ao_a_8_pins: pwm_ao_a_8 {
230                         mux {
231                                 groups = "pwm_ao_a_8";
232                                 function = "pwm_ao_a";
233                                 bias-disable;
234                         };
235                 };
236 
237                 pwm_ao_b_pins: pwm_ao_b {
238                         mux {
239                                 groups = "pwm_ao_b";
240                                 function = "pwm_ao_b";
241                                 bias-disable;
242                         };
243                 };
244 
245                 pwm_ao_b_6_pins: pwm_ao_b_6 {
246                         mux {
247                                 groups = "pwm_ao_b_6";
248                                 function = "pwm_ao_b";
249                                 bias-disable;
250                         };
251                 };
252 
253                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
254                         mux {
255                                 groups = "i2s_out_ch23_ao";
256                                 function = "i2s_out_ao";
257                                 bias-disable;
258                         };
259                 };
260 
261                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
262                         mux {
263                                 groups = "i2s_out_ch45_ao";
264                                 function = "i2s_out_ao";
265                                 bias-disable;
266                         };
267                 };
268 
269                 spdif_out_ao_6_pins: spdif_out_ao_6 {
270                         mux {
271                                 groups = "spdif_out_ao_6";
272                                 function = "spdif_out_ao";
273                                 bias-disable;
274                         };
275                 };
276 
277                 spdif_out_ao_9_pins: spdif_out_ao_9 {
278                         mux {
279                                 groups = "spdif_out_ao_9";
280                                 function = "spdif_out_ao";
281                                 bias-disable;
282                         };
283                 };
284 
285                 ao_cec_pins: ao_cec {
286                         mux {
287                                 groups = "ao_cec";
288                                 function = "cec_ao";
289                                 bias-disable;
290                         };
291                 };
292 
293                 ee_cec_pins: ee_cec {
294                         mux {
295                                 groups = "ee_cec";
296                                 function = "cec_ao";
297                                 bias-disable;
298                         };
299                 };
300         };
301 };
302 
303 &cec_AO {
304         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
305         clock-names = "core";
306 };
307 
308 &clkc_AO {
309         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
310         clocks = <&xtal>, <&clkc CLKID_CLK81>;
311         clock-names = "xtal", "mpeg-clk";
312 };
313 
314 &gpio_intc {
315         compatible = "amlogic,meson-gxl-gpio-intc",
316                      "amlogic,meson-gpio-intc";
317         status = "okay";
318 };
319 
320 &hdmi_tx {
321         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
322         resets = <&reset RESET_HDMITX_CAPB3>,
323                  <&reset RESET_HDMI_SYSTEM_RESET>,
324                  <&reset RESET_HDMI_TX>;
325         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
326         clocks = <&clkc CLKID_HDMI>,
327                  <&clkc CLKID_HDMI_PCLK>,
328                  <&clkc CLKID_GCLK_VENCI_INT0>;
329         clock-names = "isfr", "iahb", "venci";
330         power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
331 
332         assigned-clocks = <&clkc CLKID_HDMI_SEL>,
333                           <&clkc CLKID_HDMI>;
334         assigned-clock-parents = <&xtal>, <0>;
335         assigned-clock-rates = <0>, <24000000>;
336 };
337 
338 &sysctrl {
339         clkc: clock-controller {
340                 compatible = "amlogic,gxl-clkc";
341                 #clock-cells = <1>;
342                 clocks = <&xtal>;
343                 clock-names = "xtal";
344         };
345 };
346 
347 &hwrng {
348         clocks = <&clkc CLKID_RNG0>;
349         clock-names = "core";
350 };
351 
352 &i2c_A {
353         clocks = <&clkc CLKID_I2C>;
354 };
355 
356 &i2c_AO {
357         clocks = <&clkc CLKID_AO_I2C>;
358 };
359 
360 &i2c_B {
361         clocks = <&clkc CLKID_I2C>;
362 };
363 
364 &i2c_C {
365         clocks = <&clkc CLKID_I2C>;
366 };
367 
368 &periphs {
369         pinctrl_periphs: pinctrl@4b0 {
370                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
371                 #address-cells = <2>;
372                 #size-cells = <2>;
373                 ranges;
374 
375                 gpio: bank@4b0 {
376                         reg = <0x0 0x004b0 0x0 0x28>,
377                               <0x0 0x004e8 0x0 0x14>,
378                               <0x0 0x00520 0x0 0x14>,
379                               <0x0 0x00430 0x0 0x40>;
380                         reg-names = "mux", "pull", "pull-enable", "gpio";
381                         gpio-controller;
382                         #gpio-cells = <2>;
383                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
384                 };
385 
386                 emmc_pins: emmc {
387                         mux-0 {
388                                 groups = "emmc_nand_d07",
389                                        "emmc_cmd";
390                                 function = "emmc";
391                                 bias-pull-up;
392                         };
393 
394                         mux-1 {
395                                 groups = "emmc_clk";
396                                 function = "emmc";
397                                 bias-disable;
398                         };
399                 };
400 
401                 emmc_ds_pins: emmc-ds {
402                         mux {
403                                 groups = "emmc_ds";
404                                 function = "emmc";
405                                 bias-pull-down;
406                         };
407                 };
408 
409                 emmc_clk_gate_pins: emmc_clk_gate {
410                         mux {
411                                 groups = "BOOT_8";
412                                 function = "gpio_periphs";
413                                 bias-pull-down;
414                         };
415                 };
416 
417                 nor_pins: nor {
418                         mux {
419                                 groups = "nor_d",
420                                        "nor_q",
421                                        "nor_c",
422                                        "nor_cs";
423                                 function = "nor";
424                                 bias-disable;
425                         };
426                 };
427 
428                 spi_pins: spi-pins {
429                         mux {
430                                 groups = "spi_miso",
431                                         "spi_mosi",
432                                         "spi_sclk";
433                                 function = "spi";
434                                 bias-disable;
435                         };
436                 };
437 
438                 spi_idle_high_pins: spi-idle-high-pins {
439                         mux {
440                                 groups = "spi_sclk";
441                                 bias-pull-up;
442                         };
443                 };
444 
445                 spi_idle_low_pins: spi-idle-low-pins {
446                         mux {
447                                 groups = "spi_sclk";
448                                 bias-pull-down;
449                         };
450                 };
451 
452                 spi_ss0_pins: spi-ss0 {
453                         mux {
454                                 groups = "spi_ss0";
455                                 function = "spi";
456                                 bias-disable;
457                         };
458                 };
459 
460                 sdcard_pins: sdcard {
461                         mux-0 {
462                                 groups = "sdcard_d0",
463                                        "sdcard_d1",
464                                        "sdcard_d2",
465                                        "sdcard_d3",
466                                        "sdcard_cmd";
467                                 function = "sdcard";
468                                 bias-pull-up;
469                         };
470 
471                         mux-1 {
472                                 groups = "sdcard_clk";
473                                 function = "sdcard";
474                                 bias-disable;
475                         };
476                 };
477 
478                 sdcard_clk_gate_pins: sdcard_clk_gate {
479                         mux {
480                                 groups = "CARD_2";
481                                 function = "gpio_periphs";
482                                 bias-pull-down;
483                         };
484                 };
485 
486                 sdio_pins: sdio {
487                         mux-0 {
488                                 groups = "sdio_d0",
489                                        "sdio_d1",
490                                        "sdio_d2",
491                                        "sdio_d3",
492                                        "sdio_cmd";
493                                 function = "sdio";
494                                 bias-pull-up;
495                         };
496 
497                         mux-1 {
498                                 groups = "sdio_clk";
499                                 function = "sdio";
500                                 bias-disable;
501                         };
502                 };
503 
504                 sdio_clk_gate_pins: sdio_clk_gate {
505                         mux {
506                                 groups = "GPIOX_4";
507                                 function = "gpio_periphs";
508                                 bias-pull-down;
509                         };
510                 };
511 
512                 sdio_irq_pins: sdio_irq {
513                         mux {
514                                 groups = "sdio_irq";
515                                 function = "sdio";
516                                 bias-disable;
517                         };
518                 };
519 
520                 uart_a_pins: uart_a {
521                         mux {
522                                 groups = "uart_tx_a",
523                                        "uart_rx_a";
524                                 function = "uart_a";
525                                 bias-disable;
526                         };
527                 };
528 
529                 uart_a_cts_rts_pins: uart_a_cts_rts {
530                         mux {
531                                 groups = "uart_cts_a",
532                                        "uart_rts_a";
533                                 function = "uart_a";
534                                 bias-disable;
535                         };
536                 };
537 
538                 uart_b_pins: uart_b {
539                         mux {
540                                 groups = "uart_tx_b",
541                                        "uart_rx_b";
542                                 function = "uart_b";
543                                 bias-disable;
544                         };
545                 };
546 
547                 uart_b_cts_rts_pins: uart_b_cts_rts {
548                         mux {
549                                 groups = "uart_cts_b",
550                                        "uart_rts_b";
551                                 function = "uart_b";
552                                 bias-disable;
553                         };
554                 };
555 
556                 uart_c_pins: uart_c {
557                         mux {
558                                 groups = "uart_tx_c",
559                                        "uart_rx_c";
560                                 function = "uart_c";
561                                 bias-disable;
562                         };
563                 };
564 
565                 uart_c_cts_rts_pins: uart_c_cts_rts {
566                         mux {
567                                 groups = "uart_cts_c",
568                                        "uart_rts_c";
569                                 function = "uart_c";
570                                 bias-disable;
571                         };
572                 };
573 
574                 i2c_a_pins: i2c_a {
575                         mux {
576                                 groups = "i2c_sck_a",
577                                      "i2c_sda_a";
578                                 function = "i2c_a";
579                                 bias-disable;
580                         };
581                 };
582 
583                 i2c_b_pins: i2c_b {
584                         mux {
585                                 groups = "i2c_sck_b",
586                                       "i2c_sda_b";
587                                 function = "i2c_b";
588                                 bias-disable;
589                         };
590                 };
591 
592                 i2c_c_pins: i2c_c {
593                         mux {
594                                 groups = "i2c_sck_c",
595                                       "i2c_sda_c";
596                                 function = "i2c_c";
597                                 bias-disable;
598                         };
599                 };
600 
601                 i2c_c_dv18_pins: i2c_c_dv18 {
602                         mux {
603                                 groups = "i2c_sck_c_dv19",
604                                       "i2c_sda_c_dv18";
605                                 function = "i2c_c";
606                                 bias-disable;
607                         };
608                 };
609 
610                 eth_pins: eth_c {
611                         mux {
612                                 groups = "eth_mdio",
613                                        "eth_mdc",
614                                        "eth_clk_rx_clk",
615                                        "eth_rx_dv",
616                                        "eth_rxd0",
617                                        "eth_rxd1",
618                                        "eth_rxd2",
619                                        "eth_rxd3",
620                                        "eth_rgmii_tx_clk",
621                                        "eth_tx_en",
622                                        "eth_txd0",
623                                        "eth_txd1",
624                                        "eth_txd2",
625                                        "eth_txd3";
626                                 function = "eth";
627                                 bias-disable;
628                         };
629                 };
630 
631                 eth_link_led_pins: eth_link_led {
632                         mux {
633                                 groups = "eth_link_led";
634                                 function = "eth_led";
635                                 bias-disable;
636                         };
637                 };
638 
639                 eth_act_led_pins: eth_act_led {
640                         mux {
641                                 groups = "eth_act_led";
642                                 function = "eth_led";
643                         };
644                 };
645                 
646                 pwm_a_pins: pwm_a {
647                         mux {
648                                 groups = "pwm_a";
649                                 function = "pwm_a";
650                                 bias-disable;
651                         };
652                 };
653 
654                 pwm_b_pins: pwm_b {
655                         mux {
656                                 groups = "pwm_b";
657                                 function = "pwm_b";
658                                 bias-disable;
659                         };
660                 };
661 
662                 pwm_c_pins: pwm_c {
663                         mux {
664                                 groups = "pwm_c";
665                                 function = "pwm_c";
666                                 bias-disable;
667                         };
668                 };
669 
670                 pwm_d_pins: pwm_d {
671                         mux {
672                                 groups = "pwm_d";
673                                 function = "pwm_d";
674                                 bias-disable;
675                         };
676                 };
677 
678                 pwm_e_pins: pwm_e {
679                         mux {
680                                 groups = "pwm_e";
681                                 function = "pwm_e";
682                                 bias-disable;
683                         };
684                 };
685 
686                 pwm_f_clk_pins: pwm_f_clk {
687                         mux {
688                                 groups = "pwm_f_clk";
689                                 function = "pwm_f";
690                                 bias-disable;
691                         };
692                 };
693 
694                 pwm_f_x_pins: pwm_f_x {
695                         mux {
696                                 groups = "pwm_f_x";
697                                 function = "pwm_f";
698                                 bias-disable;
699                         };
700                 };
701 
702                 hdmi_hpd_pins: hdmi_hpd {
703                         mux {
704                                 groups = "hdmi_hpd";
705                                 function = "hdmi_hpd";
706                                 bias-disable;
707                         };
708                 };
709 
710                 hdmi_i2c_pins: hdmi_i2c {
711                         mux {
712                                 groups = "hdmi_sda", "hdmi_scl";
713                                 function = "hdmi_i2c";
714                                 bias-disable;
715                         };
716                 };
717 
718                 i2s_am_clk_pins: i2s_am_clk {
719                         mux {
720                                 groups = "i2s_am_clk";
721                                 function = "i2s_out";
722                                 bias-disable;
723                         };
724                 };
725 
726                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
727                         mux {
728                                 groups = "i2s_out_ao_clk";
729                                 function = "i2s_out";
730                                 bias-disable;
731                         };
732                 };
733 
734                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
735                         mux {
736                                 groups = "i2s_out_lr_clk";
737                                 function = "i2s_out";
738                                 bias-disable;
739                         };
740                 };
741 
742                 i2s_out_ch01_pins: i2s_out_ch01 {
743                         mux {
744                                 groups = "i2s_out_ch01";
745                                 function = "i2s_out";
746                                 bias-disable;
747                         };
748                 };
749                 i2sout_ch23_z_pins: i2sout_ch23_z {
750                         mux {
751                                 groups = "i2sout_ch23_z";
752                                 function = "i2s_out";
753                                 bias-disable;
754                         };
755                 };
756 
757                 i2sout_ch45_z_pins: i2sout_ch45_z {
758                         mux {
759                                 groups = "i2sout_ch45_z";
760                                 function = "i2s_out";
761                                 bias-disable;
762                         };
763                 };
764 
765                 i2sout_ch67_z_pins: i2sout_ch67_z {
766                         mux {
767                                 groups = "i2sout_ch67_z";
768                                 function = "i2s_out";
769                                 bias-disable;
770                         };
771                 };
772 
773                 spdif_out_h_pins: spdif_out_ao_h {
774                         mux {
775                                 groups = "spdif_out_h";
776                                 function = "spdif_out";
777                                 bias-disable;
778                         };
779                 };
780         };
781 
782         eth_phy_mux: mdio@558 {
783                 reg = <0x0 0x558 0x0 0xc>;
784                 compatible = "amlogic,gxl-mdio-mux";
785                 #address-cells = <1>;
786                 #size-cells = <0>;
787                 clocks = <&clkc CLKID_FCLK_DIV4>;
788                 clock-names = "ref";
789                 mdio-parent-bus = <&mdio0>;
790 
791                 external_mdio: mdio@0 {
792                         reg = <0x0>;
793                         #address-cells = <1>;
794                         #size-cells = <0>;
795                 };
796 
797                 internal_mdio: mdio@1 {
798                         reg = <0x1>;
799                         #address-cells = <1>;
800                         #size-cells = <0>;
801 
802                         internal_phy: ethernet-phy@8 {
803                                 compatible = "ethernet-phy-id0181.4400";
804                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
805                                 reg = <8>;
806                                 max-speed = <100>;
807                         };
808                 };
809         };
810 };
811 
812 &pwrc {
813         resets = <&reset RESET_VIU>,
814                  <&reset RESET_VENC>,
815                  <&reset RESET_VCBUS>,
816                  <&reset RESET_BT656>,
817                  <&reset RESET_DVIN_RESET>,
818                  <&reset RESET_RDMA>,
819                  <&reset RESET_VENCI>,
820                  <&reset RESET_VENCP>,
821                  <&reset RESET_VDAC>,
822                  <&reset RESET_VDI6>,
823                  <&reset RESET_VENCL>,
824                  <&reset RESET_VID_LOCK>;
825         reset-names = "viu", "venc", "vcbus", "bt656",
826                       "dvin", "rdma", "venci", "vencp",
827                       "vdac", "vdi6", "vencl", "vid_lock";
828         clocks = <&clkc CLKID_VPU>,
829                  <&clkc CLKID_VAPB>;
830         clock-names = "vpu", "vapb";
831         /*
832          * VPU clocking is provided by two identical clock paths
833          * VPU_0 and VPU_1 muxed to a single clock by a glitch
834          * free mux to safely change frequency while running.
835          * Same for VAPB but with a final gate after the glitch free mux.
836          */
837         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
838                           <&clkc CLKID_VPU_0>,
839                           <&clkc CLKID_VPU>, /* Glitch free mux */
840                           <&clkc CLKID_VAPB_0_SEL>,
841                           <&clkc CLKID_VAPB_0>,
842                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
843         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
844                                  <0>, /* Do Nothing */
845                                  <&clkc CLKID_VPU_0>,
846                                  <&clkc CLKID_FCLK_DIV4>,
847                                  <0>, /* Do Nothing */
848                                  <&clkc CLKID_VAPB_0>;
849         assigned-clock-rates = <0>, /* Do Nothing */
850                                <666666666>,
851                                <0>, /* Do Nothing */
852                                <0>, /* Do Nothing */
853                                <250000000>,
854                                <0>; /* Do Nothing */
855 };
856 
857 &saradc {
858         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
859         clocks = <&xtal>,
860                  <&clkc CLKID_SAR_ADC>,
861                  <&clkc CLKID_SAR_ADC_CLK>,
862                  <&clkc CLKID_SAR_ADC_SEL>;
863         clock-names = "clkin", "core", "adc_clk", "adc_sel";
864 };
865 
866 &sd_emmc_a {
867         clocks = <&clkc CLKID_SD_EMMC_A>,
868                  <&clkc CLKID_SD_EMMC_A_CLK0>,
869                  <&clkc CLKID_FCLK_DIV2>;
870         clock-names = "core", "clkin0", "clkin1";
871         resets = <&reset RESET_SD_EMMC_A>;
872 };
873 
874 &sd_emmc_b {
875         clocks = <&clkc CLKID_SD_EMMC_B>,
876                  <&clkc CLKID_SD_EMMC_B_CLK0>,
877                  <&clkc CLKID_FCLK_DIV2>;
878         clock-names = "core", "clkin0", "clkin1";
879         resets = <&reset RESET_SD_EMMC_B>;
880 };
881 
882 &sd_emmc_c {
883         clocks = <&clkc CLKID_SD_EMMC_C>,
884                  <&clkc CLKID_SD_EMMC_C_CLK0>,
885                  <&clkc CLKID_FCLK_DIV2>;
886         clock-names = "core", "clkin0", "clkin1";
887         resets = <&reset RESET_SD_EMMC_C>;
888 };
889 
890 &simplefb_hdmi {
891         clocks = <&clkc CLKID_HDMI_PCLK>,
892                  <&clkc CLKID_CLK81>,
893                  <&clkc CLKID_GCLK_VENCI_INT0>;
894 };
895 
896 &spicc {
897         clocks = <&clkc CLKID_SPICC>;
898         clock-names = "core";
899         resets = <&reset RESET_PERIPHS_SPICC>;
900         num-cs = <1>;
901 };
902 
903 &spifc {
904         clocks = <&clkc CLKID_SPI>;
905 };
906 
907 &uart_A {
908         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
909         clock-names = "xtal", "pclk", "baud";
910 };
911 
912 &uart_AO {
913         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
914         clock-names = "xtal", "pclk", "baud";
915 };
916 
917 &uart_AO_B {
918         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
919         clock-names = "xtal", "pclk", "baud";
920 };
921 
922 &uart_B {
923         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
924         clock-names = "xtal", "pclk", "baud";
925 };
926 
927 &uart_C {
928         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
929         clock-names = "xtal", "pclk", "baud";
930 };
931 
932 &vpu {
933         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
934         power-domains = <&pwrc PWRC_GXBB_VPU_ID>;
935 };
936 
937 &vdec {
938         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
939         clocks = <&clkc CLKID_DOS_PARSER>,
940                  <&clkc CLKID_DOS>,
941                  <&clkc CLKID_VDEC_1>,
942                  <&clkc CLKID_VDEC_HEVC>;
943         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
944         resets = <&reset RESET_PARSER>;
945         reset-names = "esparser";
946 };

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