1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 /dts-v1/;
8
9 #include "meson-sm1.dtsi"
10 #include "meson-khadas-vim3.dtsi"
11 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
12
13 / {
14 compatible = "khadas,vim3l", "amlogic,sm1";
15 model = "Khadas VIM3L";
16
17 vddcpu: regulator-vddcpu {
18 /*
19 * Silergy SY8030DEC Regulator.
20 */
21 compatible = "pwm-regulator";
22
23 regulator-name = "VDDCPU";
24 regulator-min-microvolt = <690000>;
25 regulator-max-microvolt = <1050000>;
26
27 pwm-supply = <&vsys_3v3>;
28
29 pwms = <&pwm_AO_cd 1 1250 0>;
30 pwm-dutycycle-range = <100 0>;
31
32 regulator-boot-on;
33 regulator-always-on;
34 };
35
36 sound {
37 model = "G12B-KHADAS-VIM3L";
38 audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
39 "TDMOUT_A IN 1", "FRDDR_B OUT 0",
40 "TDMOUT_A IN 2", "FRDDR_C OUT 0",
41 "TDM_A Playback", "TDMOUT_A OUT",
42 "TDMIN_A IN 0", "TDM_A Capture",
43 "TDMIN_A IN 13", "TDM_A Loopback",
44 "TODDR_A IN 0", "TDMIN_A OUT",
45 "TODDR_B IN 0", "TDMIN_A OUT",
46 "TODDR_C IN 0", "TDMIN_A OUT";
47 };
48 };
49
50 &cpu0 {
51 cpu-supply = <&vddcpu>;
52 operating-points-v2 = <&cpu_opp_table>;
53 clocks = <&clkc CLKID_CPU_CLK>;
54 clock-latency = <50000>;
55 };
56
57 &cpu1 {
58 cpu-supply = <&vddcpu>;
59 operating-points-v2 = <&cpu_opp_table>;
60 clocks = <&clkc CLKID_CPU1_CLK>;
61 clock-latency = <50000>;
62 };
63
64 &cpu2 {
65 cpu-supply = <&vddcpu>;
66 operating-points-v2 = <&cpu_opp_table>;
67 clocks = <&clkc CLKID_CPU2_CLK>;
68 clock-latency = <50000>;
69 };
70
71 &cpu3 {
72 cpu-supply = <&vddcpu>;
73 operating-points-v2 = <&cpu_opp_table>;
74 clocks = <&clkc CLKID_CPU3_CLK>;
75 clock-latency = <50000>;
76 };
77
78 &pwm_AO_cd {
79 pinctrl-0 = <&pwm_ao_d_e_pins>;
80 pinctrl-names = "default";
81 clocks = <&xtal>;
82 clock-names = "clkin1";
83 status = "okay";
84 };
85
86 /*
87 * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential
88 * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
89 * an USB3.0 Type A connector and a M.2 Key M slot.
90 * The PHY driving these differential lines is shared between
91 * the USB3.0 controller and the PCIe Controller, thus only
92 * a single controller can use it.
93 * If the MCU is configured to mux the PCIe/USB3.0 differential lines
94 * to the M.2 Key M slot, uncomment the following block to disable
95 * USB3.0 from the USB Complex and enable the PCIe controller.
96 * The End User is not expected to uncomment the following except for
97 * testing purposes, but instead rely on the firmware/bootloader to
98 * update these nodes accordingly if PCIe mode is selected by the MCU.
99 */
100 /*
101 &pcie {
102 status = "okay";
103 };
104
105 &usb {
106 phys = <&usb2_phy0>, <&usb2_phy1>;
107 phy-names = "usb2-phy0", "usb2-phy1";
108 };
109 */
110
111 &sd_emmc_a {
112 sd-uhs-sdr50;
113 };
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